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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Including Passive Device (e.g., Resistor, Capacitor, Etc.) Including Passive Device (e.g., Resistor, Capacitor, Etc.)Including Passive Device (e.g., Resistor, Capacitor, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/01/07 - 20070048929 - Semiconductor device with dielectric structure and method for fabricating the same A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an ... 02/22/07 - 20070042541 - Semiconductor device and its manufacture method A method for manufacturing a semiconductor device by which deterioration in the characteristics of an oxide dielectric capacitor is suppressed and the gap between capacitors and the gap between electrodes can be filled while suppressing generation of voids. The method for manufacturing a semiconductor device comprises the steps of (a) ... 02/22/07 - 20070042540 - Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier layer. A first ... 02/15/07 - 20070037344 - Semiconductor device and method for fabricating the same The semiconductor device comprises a semiconductor substrate 10, a conducting film 20 formed on the semiconductor substrate 10 and including two conductor patterns adjacent to each other; an etching stopper film covering the upper surface of the conducting film 20; an insulation film 28 which includes a contact hole which ... 02/08/07 - 20070032012 - I-shaped and l-shaped contact structures and their fabrication methods Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the ... 02/08/07 - 20070032011 - Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines ... 01/04/07 - 20070004124 - Mos field effect transistor having plurality of channels and method of fabricating the same A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are ... 12/28/06 - 20060292788 - Systems and methods of forming refractory metal nitride layers using disilazanes A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound. ... 12/28/06 - 20060292787 - Semiconductor processing methods, and semiconductor constructions The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region ... 12/28/06 - 20060292786 - Semiconductor constructions, and methods of forming semiconductor constructions The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion. ... 12/21/06 - 20060286743 - Method for manufacturing a narrow structure on an integrated circuit A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a ... 12/21/06 - 20060286742 - Method for fabrication of surface mounted metal foil chip resistors The present invention provides a method for fabricating metal foil chip resistors, comprising: providing an insulator substrate; forming a conductor layer pattern as a terminal electrode on said insulator substrate; adhering a metal foil having specific resistivity to said insulator substrate; applying the resistor wiring pattern upon said metal foil ... 12/21/06 - 20060286741 - Methods of fabricating high voltage devices Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer ... 12/14/06 - 20060281248 - Semiconductor device manufacturing method A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first ... 12/14/06 - 20060281247 - Non-volitale semiconductor memory A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric ... 11/30/06 - 20060270144 - Memory cells with vertical transistor and capacitor and fabrication methods thereof Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a ... 11/30/06 - 20060270143 - Method for manufacturing contact structures for dram semiconductor memories A method for manufacturing contact structures for DRAM semiconductor memories is disclosed. In one embodiment, contact openings are formed in a support area after execution of high-temperature processes for activating doping agents and repairing crystal defects. A low contact resistance between a conductive contact opening filling and an adjacent semiconductor ... 11/30/06 - 20060270142 - Method of fabricating memeory A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory ... 11/23/06 - 20060263973 - Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas ... 11/23/06 - 20060263972 - Atomic layer deposition of zr3n4/zro2 films as gate dielectrics The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr3N4) and zirconium oxide (ZrO2) and a method of fabricating such a dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing zirconium oxide using ... 11/23/06 - 20060263971 - Semiconductor device and method thereof A semiconductor device and a method thereof are disclosed. In the example method, a mold layer having an opening may be formed on a substrate. A conductive etchable pattern (e.g., a preliminary conductive pattern, a lower electrode pattern, etc.) may be formed within the opening. The mold layer may be ... 11/23/06 - 20060263970 - Semiconductor memory device and fabrication thereof A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the deep trench. The top of the first sidewall ... 11/23/06 - 20060263969 - Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit ... 11/23/06 - 20060263968 - Methods of forming pluralities of capacitors The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically etching individual capacitor electrode channels within a material over individual capacitor storage node locations on a substrate. The channels are at least partially filled with electrically conductive capacitor ... 11/16/06 - 20060258083 - Integrated circuit memory cells and methods of forming An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The second source/drain may be included in a digit line inner conductor ... 11/16/06 - 20060258082 - Structure of embedded capacitors and fabrication method thereof A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications usually require ... 11/02/06 - 20060246654 - Semiconductor device with resistor pattern and method of fabricating the same Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments ... 10/19/06 - 20060234439 - Maskless multiple sheet polysilicon resistor The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected ... 10/12/06 - 20060228854 - Methods for increasing photo alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in ... 10/12/06 - 20060228853 - Memory devices including spacers on sidewalls of memory storage elements and related methods A method of forming a memory device may include forming an insulating layer on a substrate, and forming a first electrode through at least a portion of the insulating layer. A memory storage element may be formed on the first electrode so that the first electrode is between the memory ... 10/12/06 - 20060228852 - Method of forming contact plugs A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on ... 09/21/06 - 20060211192 - Semiconductor memory device including storage nodes and resistors and method of manfacturing the same A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; ... 09/21/06 - 20060211191 - Method for manufacturing an electrical connecting element, and a connecting element The method according to the invention is essentially characterised in that a resistance material (5)—for example nickel or a nickel alloy—is attached on a first structured conductor layer (2)—it may be of copper or a copper alloy. Subsequently, the first structured conductor layer (5) is removed again at least at ... 08/24/06 - 20060189068 - Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture therefor The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the ... 08/10/06 - 20060177978 - Manufacturing method of semiconductor device A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form ... 08/10/06 - 20060177977 - Method for patterning fins and gates in a finfet device using trimmed hard-mask capped with imaging layer A capped trimming hard-mask patterning process to form ultra-thin structures can include depositing a hard-mask layer over a layer of patterning material, depositing an imaging layer over the hard-mask layer, patterning the imaging layer and the hard-mask layer, selectively trim etching the hard-mask layer to form a pattern hard mask, ... 07/27/06 - 20060166431 - Methods to form electronic devices and methods to form a material over a semiconductive substrate A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure ... 07/20/06 - 20060160297 - Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of ... 07/13/06 - 20060154416 - Method of pad printing in the manufacture of capacitors Deposition of a metal-containing reagent solution or suspension or a carbon nanotube-containing suspension onto a conductive substrate by various pad-printing techniques is described. In the case of a metal-containing solution or suspension, a pseudocapacitive oxide coating, nitride coating, carbon nitride coating, carbide coating, or carbon nanotube coating results. In any ... 06/29/06 - 20060141697 - Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a ... 06/29/06 - 20060141696 - Method for forming landing plug contact in semiconductor device A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation ... 05/25/06 - 20060110877 - Memory device including resistance change layer as storage node and method(s) for making the same A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) ... 05/18/06 - 20060105519 - Dram on soi In a semiconductor manufacturing process for a dynamic random access memory, a buried insulator layer such as a buried SIMOX layer between trench capacitors isolates the capacitor from the access transistor, limiting leakage, improving device performance and simplifying manufacturing. ... 03/02/06 - 20060046380 - Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second ... 03/02/06 - 20060046379 - Fabricating memory components (pcrams) including memory cells based on a layer that changes phase state A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and ... 03/02/06 - 20060046378 - Methods of fabricating mim capacitor employing metal nitride layer as lower electrode There are provided methods of fabricating a metal-insulator-metal (MIM) capacitor employing a metal nitride layer as a lower electrode. The method includes forming an insulating layer on a semiconductor substrate. A metal source gas and a nitride gas are supplied to the insulating layer, thereby depositing a metal nitride. A ... 03/02/06 - 20060046377 - Thin-film capacitor including an opening therein and a manufacturing method thereof A thin-film capacitor includes a lower electrode film, a high dielectric film and an upper electrode film disposed sequentially. One film of the three films includes first and second edge portions placed opposite to each other. Furthermore, the one film includes a first opening which extends from the first edge ... 02/23/06 - 20060040444 - Method for fabricating a three-dimensional capacitor A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed. ... 02/23/06 - 20060040443 - Methods of forming capacitor electrodes using fluorine and oxygen A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode. ... 02/16/06 - 20060035429 - Methods of forming phase-change random access memories including a confined contact hole and integrated circuit devices including the same Methods of forming a phase-change random access memory (PRAM) include forming a lower electrode layer and a node insulating layer on an active region of a semiconductor substrate. A photoresist pattern is formed on the node insulating layer that includes an opening therein. A polymer layer is formed on the ... 02/16/06 - 20060035428 - Dynamic random access memory cell and fabricating method thereof A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed ... 01/19/06 - 20060014343 - Method for forming a capacitor for an integrated circuit and integrated circuit Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal ... 01/12/06 - 20060008976 - Novel random access memory (ram) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in ... 01/05/06 - 20060003523 - Void free, silicon filled trenches in semiconductors The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature. ... 01/05/06 - 20060003522 - Semiconductor device substrate with embedded capacitor A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a ... 12/29/05 - 20050287736 - Latch-up prevention for memory cells An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always ... 12/29/05 - 20050287735 - Semiconductor storage device and method of manufacturing the same A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, ... 12/22/05 - 20050282334 - Nrom flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on ... 12/22/05 - 20050282333 - Memory cell transistor having different source/drain junction profiles connected to dc node and bc node and manufacturing method thereof A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are ... 12/08/05 - 20050272199 - Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the ... 12/01/05 - 20050266635 - Graded gexse100-x concentration in pcram The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure. ... 12/01/05 - 20050266634 - Methods of fabricating semiconductor devices including polysilicon resistors and related devices Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a ... 12/01/05 - 20050266633 - Method for fabricating capacitor A method for fabricating a capacitor is described. A metal layer is formed on a substrate, and then an insulating layer is formed over the substrate covering the metal layer. At least one opening is formed in the insulating layer exposing a portion of the metal layer, and a metal ... 11/10/05 - 20050250280 - Capacitance process by using passivation film scheme In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving as ... 11/03/05 - 20050245022 - Stacked capacitor array and fabrication method for a stacked capacitor array The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are ... 10/20/05 - 20050233518 - Electronic circuit device having silicon substrate An electronic circuit device having a silicon substrate is provided comprising: a silicon substrate having a semiconductor element and a recess; and at least one passive element which is formed by a process different from a silicon planar process by which the semiconductor element is formed. In the electronic circuit ... 09/15/05 - 20050202626 - Method for fabricating a semiconductor structure The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10′) made of silicon oxide and an overlying second hard mask layer (15; 15′) made of silicon; providing a masking ... 09/08/05 - 20050196915 - Method of fabricating analog capacitor using post-treatment technique There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor ... 09/08/05 - 20050196914 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film ... 09/01/05 - 20050191804 - Method for forming a reduced active area in a phase change memory structure A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom ... 08/18/05 - 20050181556 - Method of forming a semiconductor device having a capacitor and a resistor A method of simultaneously forming at least one capacitor, at least one resistor and at least one metal-oxide semiconductor. A structure having: an exposed oxide structure; a capacitor region within at least a portion of the exposed oxide structure; a first resistor region within at least a portion of the ... 07/21/05 - 20050158943 - Manufacturing method of semiconductor device This invention is directed to a manufacturing method of a semiconductor device having a MOS transistor and a diffusion resistance layer formed on a same semiconductor substrate, where current leakage from the diffusion resistance layer is minimized. The manufacturing method of the semiconductor device of the invention has following features. ... 06/16/05 - 20050130367 - Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the ... 06/09/05 - 20050124108 - Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon ... ### FreshPatents.com Support |