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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Self-aligned > Plural Doping Steps Plural Doping StepsPlural Doping Steps patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087497 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer ... 12/14/06 - 20060281246 - Semiconductor having structure with openings A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in ... 09/14/06 - 20060205139 - Method for forming plural kinds of wells on a single semiconductor substrate A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying ... 07/13/06 - 20060154415 - Method for manufacturing semiconductor substrate and semiconductor substrate A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then ... 07/06/06 - 20060148167 - Electronic devices A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing ... 06/29/06 - 20060141695 - Methods of forming thin layers including zirconium hafnium oxide and methods of forming gate structures, capacitors, and flash memory devices using the same Methods of forming a zirconium hafnium oxide thin layer on a semiconductor substrate by supplying tetrakis(ethylmethylamino)zirconium ([Zr{N(C2H5)(CH3)}4], TEMAZ) and tetrakis(ethylmethylamino)hafnium ([Hf{N(C2H5)(CH3)}4], TEMAH) to a substrate are provided. The TEMAZ and the TEMAH may be reacted with an oxidizing agent. The thin layer including zirconium hafnium oxide may be used for ... 06/22/06 - 20060134853 - Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with ... 06/22/06 - 20060134852 - Interconnect and head gimbal assembly with the same An interconnect for connecting a magnetic head slider and a flexible printed circuit, and a head gimbal assembly having the interconnect are provided. The interconnect includes a ground layer, a first insulation layer formed on the ground layer, and a pair of signal transferring layers formed on the first insulation ... 06/01/06 - 20060115945 - Printed transistors A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For ... 02/23/06 - 20060040442 - Bump inspection apparatus and method for ic component, bump forming method for ic component, and mounting method for ic component Unidirectional light is irradiated onto a bump-formation surface of an IC component to acquire a first overall image of the IC component, light is irradiated onto the bump-formation surface in respective inclined directions to acquire a second overall image, first bump inspection images are respectively acquired from the first overall ... 02/02/06 - 20060024881 - Methods of forming metal oxide and semimetal oxide The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide ... 01/12/06 - 20060008974 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groove. A second surface of the ... 01/05/06 - 20060003521 - Method of and apparatus for manufacturing semiconductor device A damaged layer which is necessarily produced on the exposed surface of an interconnect by flattening of a surface of a substrate for forming interconnect according to a damascene process is restored, making it possible to manufacture semiconductor devices with a high yield. A semiconductor device is manufactured by preparing ... 12/29/05 - 20050287734 - Method for fabricating trench power device Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method ... 12/22/05 - 20050282332 - Non-volatile memory cell and method of operating the same A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a ... 12/15/05 - 20050277246 - Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams. ... 09/15/05 - 20050202625 - Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process ... 09/15/05 - 20050202624 - Plasma ion implantation system A plasma ion implantation system comprises a vacuum chamber, a plasma generator configured to generate ions in the vacuum chamber, a sample holder inside the vacuum chamber, and a voltage source configured to provide a bias voltage between the sample holder and the vacuum chamber to attract ions to implant ... 08/18/05 - 20050181555 - Thin films Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric ... 07/28/05 - 20050164444 - Selective nitridation of gate oxides A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. ... 06/30/05 - 20050142730 - Method of manufacturing cmos transistor by using soi substrate In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a ... ### FreshPatents.com Support |