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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Self-aligned > Utilizing Gate Sidewall Structure > Plural Doping Steps Plural Doping StepsPlural Doping Steps patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082439 - Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has ... 02/15/07 - 20070037343 - Process for manufacturing dual work function metal gates in a microelectronics device The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a ... 12/21/06 - 20060286740 - A method for forming a device having multiple silicide types Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide ... 11/30/06 - 20060270140 - Methods for transistor formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers ... 11/30/06 - 20060270139 - Methods for transistor formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers ... 11/16/06 - 20060258080 - Vertical diode, matrix position sensitive apparatus and manufacturing method of the same A vertical diode formed by stacking semiconductor layers includes (1) a lower electrode whose surface is plasma-treated in a gas containing an element which becomes a P-type or N-type conductivity type, and (2) a non-doped semiconductor layer provided on the lower electrode. The P-type or N-type semiconductor area is formed ... 07/20/06 - 20060160296 - Methods of forming cmos constructions The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has ... 05/18/06 - 20060105518 - Ultra-shallow arsenic junction formation in silicon germanium In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20). ... 01/12/06 - 20060008973 - Selective oxide trimming to improve metal t-gate transistor A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. ... 11/03/05 - 20050245021 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that ... 06/30/05 - 20050142729 - Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ... ### FreshPatents.com Support |