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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Self-aligned Self-alignedSelf-aligned patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/24/06 - 20060189066 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide ... ### FreshPatents.com Support |