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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Including Isolation Structure > Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material Dielectric Isolation Formed By Grooving And Refilling With Dielectric MaterialDielectric Isolation Formed By Grooving And Refilling With Dielectric Material patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/04/07 - 20070004122 - Method for fabricating semiconductor memory device A method for fabricating a semiconductor memory device in which a logic circuit and a nonvolatile memory are provided on a semiconductor substrate includes the steps of: forming an isolation region; forming a protective film made of an insulating material over the semiconductor substrate in a logic circuit region and ... 12/21/06 - 20060286739 - Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying ... 12/14/06 - 20060281245 - Semiconductor device and method for manufacturing the same A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion ... 11/09/06 - 20060252197 - Method for monitoring lateral encroachment of spacer process on a cd sem A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer ... 10/12/06 - 20060228851 - Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in ... 09/21/06 - 20060211190 - Self-aligned method for defining a semiconductor gate oxide in high voltage device area A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit ... 07/20/06 - 20060160295 - Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the ... 07/20/06 - 20060160294 - Soi device with body contact self-aligned to gate A region of a semiconductor wafer is converted to an SOI structure by etching a set of isolation trenches for each transistor active area and oxidizing the sidewalls of the trenches to a depth that leaves a pillar of semiconductor that forms a body contact extending from the active area ... 06/22/06 - 20060134850 - Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface ... 01/19/06 - 20060014340 - Semiconductor device and method of manufacturing the same According to an aspect of the invention, there is provided a semiconductor device provided with a CMOS-FET circuit, comprising at least one of a tensile stress film disposed in a part of an element isolating film around an NMOS forming region and having a tensile stress, and a compressive stress ... 01/12/06 - 20060008971 - Method for fabricating shallow trench isolation layer of semiconductor device A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of forming a sacrificial layer ... 01/12/06 - 20060008970 - Optimized plating process for multilayer printed circuit boards having edge connectors A process for manufacturing printed wire boards with hard plated sliding contact tabs and soft plated wire bond pads. Sliding contact tabs are covered by a protective coating after being hard plated thus allowing the soft plating of wire bond pads without damaging the hard plated sliding contact tabs. In ... 06/23/05 - 20050136588 - Method of forming isolation regions The present invention is generally directed to various methods of forming isolation regions. In one illustrative embodiment, the method comprises forming a stack of process layers above a surface of a semiconducting substrate, the stack of process layers comprised of a first layer of insulating material formed above a surface ... ### FreshPatents.com Support |