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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Including Isolation Structure Including Isolation StructureIncluding Isolation Structure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072357 - Method of manufacturing devices having vertical junction edge Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and ... 03/01/07 - 20070048927 - Shallow trench isolation by atomic-level silicon reconstruction Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms ... 02/15/07 - 20070037340 - Fabrication method for fabricating a semiconductor structure and semiconductor structure In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises ... 11/23/06 - 20060263966 - Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the ... 10/19/06 - 20060234437 - Recessed-type field effect transistor with reduced body effect For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the ... 01/26/06 - 20060019440 - Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying ... 11/17/05 - 20050255648 - Silicon based substrate hafnium oxide top environmental/thermal top barrier layer and method for preparing A top barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment and comprises at least 65 mol % hafnium oxide. ... 06/23/05 - 20050136587 - Semiconductor device having reduced gate charge and reduced on resistance and method In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body ... ### FreshPatents.com Support |