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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > Vertical Channel Vertical ChannelVertical Channel patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/02/06 - 20060246650 - Recessed clamping diode fabrication in trench devices In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions ... 11/02/06 - 20060246649 - Method for forming gate structure in flash memory device Device isolation insulation layers passing through an insulation layer and a substrate, are formed, and a portion of them is removed. The insulation layer is removed. A gate oxide layer and a first conductive layer sequentially formed over the device isolation insulation layers, are isolated. Portions of the device isolation ... 09/21/06 - 20060211189 - Method for producing a buried semiconductor layer A method for producing a region of increased doping in an n-doped semiconductor layer which is buried in a semiconductor body of a vertical power transistor and which is arranged between a p-doped body region facing the front side contact of the power transistor and an n-doped substrate facing the ... 08/03/06 - 20060172483 - Dram arrays, vertical transistor structures and methods of forming transistor structures and dram arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to ... 07/27/06 - 20060166429 - Vertical replacement-gate junction field-effect transistor An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is ... 06/22/06 - 20060134847 - Method of manufacturing a sic vertical mosfet A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that ... 12/29/05 - 20050287732 - Method of manufacture of semiconductor device A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film, by patterning the polycrystalline silicon film, in an active cell area, a ... 12/08/05 - 20050272195 - Integrated circuit having pairs of parallel complementary finfets A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also ... ### FreshPatents.com Support |