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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > And Additional Electrical Device > Including Insulated Gate Field Effect Transistor Having Gate Surrounded By Dielectric (i.e., Floating Gate) Including Insulated Gate Field Effect Transistor Having Gate Surrounded By Dielectric (i.e., Floating Gate)Including Insulated Gate Field Effect Transistor Having Gate Surrounded By Dielectric (i.e., Floating Gate) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077699 - Multilevel programming of phase change memory cells A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase ... 03/22/07 - 20070066004 - Semiconductor device and its manufacture method A non-volatile semiconductor memory device which simultaneously possesses a non-volatile memory cell region which possesses an isolating insulation film which has been formed selectively within a semiconductor substrate, which also possesses a first electroconductive film (floating gate electrode) via a first gate insulating film which has been formed on the ... 03/22/07 - 20070066003 - Methods of forming non-volatile memory devices having trenches A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the ... 03/08/07 - 20070054448 - Nonvolatile memory device having multi-bit storage and method of manufacturing the same Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of ... 03/01/07 - 20070048923 - Flash memory with low tunnel barrier interpoly insulators Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. ... 03/01/07 - 20070048922 - Nand flash memory devices and methods of fabricating the same A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on ... 02/22/07 - 20070042539 - Method of manufacturing a non-volatile memory device In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an ... 02/15/07 - 20070037339 - Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the ... 12/28/06 - 20060292784 - Methods of forming integrated circuit devices including memory cell gates and high voltage transistor gates using plasma re-oxidation A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of ... 12/21/06 - 20060286738 - Method of forming floating-gate tip for split-gate flash memory process A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the first polysilicon layer through a CVD ... 12/14/06 - 20060281242 - Semiconductor device and fabrication method therefor A semiconductor device of the present invention includes a semiconductor substrate (10) having a bit line (14), an ONO film (16) that is provided on the semiconductor substrate (10) and has an opening (46), an interlayer insulating film (30) that is provided on the ONO film (16) and has a ... 11/30/06 - 20060270137 - Method of manufacturing non-volatile memory cell A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the ... 11/16/06 - 20060258076 - Method of manufacturing non-volatile semiconductor memory In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of ... 10/19/06 - 20060234435 - Semiconductor device having one-time programmable rom and method of fabricating the same A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The ... 10/05/06 - 20060223256 - Semiconductor memory device and method of manufacturing the same A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which ... 09/21/06 - 20060211188 - Non-volatile memory structure and method of fabrication A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least ... 09/07/06 - 20060199326 - Method and structure for forming self-aligned, dual stress liner for cmos devices A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer ... 08/24/06 - 20060189062 - Advance ridge structure for microlens gapless approach A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of openings. The plurality of patterned photoresist features can ... 07/27/06 - 20060166428 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from ... 05/11/06 - 20060099756 - Methods of forming non-volatile memory device having floating gate Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer is formed on the substrate in the cell region. A preliminary floating gate is formed ... 05/11/06 - 20060099755 - Semiconductor memory integrated circuit and its manufacturing method A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage ... 04/20/06 - 20060084219 - Advanced nrom structure and method of fabrication A method for creating a non-volatile memory array includes generating polysilicon columns on top of an oxide-nitride-oxide (ONO) layer, creating spacing elements on the sides of the polysilicon columns, implanting bit lines into the substrate at least between the spacing elements, depositing oxide filler over the bit lines, depositing a ... 04/20/06 - 20060084218 - Method and apparatus for providing an instrument playing service A method and apparatus for providing an instrument playing service in a portable terminal. In the method, an image of an instrument is projected. User finger movements on the projected instrument image are detected and sound source information corresponding to the user finger movements is read. Thereafter, an audio signal ... 04/06/06 - 20060073653 - Methods of fabricating flash memory devices with floating gates that have reduced seams Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. ... 04/06/06 - 20060073652 - Phase change memory with ovonic threshold switch A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in ... 03/02/06 - 20060046373 - Method for fabricating a semiconductor device The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the ... 02/23/06 - 20060040440 - Nand flash memory cell row and manufacturing method thereof A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of ... 01/19/06 - 20060014339 - Method of detecting one or more defects in a string of spaced apart studs A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each ... 01/12/06 - 20060008966 - Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes ... 12/29/05 - 20050287731 - Isolation trenches for memory devices A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than ... 12/22/05 - 20050282327 - Flash memory device having a graded composition, high dielectric constant gate insulator A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the ... 12/15/05 - 20050277243 - Flash memory having a high-permittivity tunnel dielectric A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be ... 10/13/05 - 20050227426 - Charge-trapping memory cell array and method for production In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material ... 09/15/05 - 20050202622 - Interconnecting conductive layers of memory devices Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap is disposed on either side of the first and second conductive layers. Each strap electrically interconnects the first and second conductive layers. ... 09/08/05 - 20050196913 - Floating gate memory structures and fabrication methods Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The ... 08/04/05 - 20050170578 - Use of pedestals to fabricate contact openings Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines ... 07/28/05 - 20050164441 - Semiconductor device and process for producing the same Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing ... 07/14/05 - 20050153502 - Flash memory device and method of manufacturing the same A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating ... 06/30/05 - 20050142726 - Method of forming gate of flash memory cell The present invention provides a method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The present invention ... 06/30/05 - 20050142725 - Method of fabricating non-volatile memory device The present invention provides a method of fabricating a non-volatile memory device, in which trench isolation can be achieved using an insulating layer that needs no separate removal process. The present invention includes sequentially forming a first insulating layer, a first conductor layer, and a second insulating layer on a ... 06/09/05 - 20050124107 - Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least ... ### FreshPatents.com Support |