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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) > And Additional Electrical Device And Additional Electrical DeviceAnd Additional Electrical Device patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.07/06/06 - 20060148162 - Soi sram device structure with increased w and full depletion An SOI device, and a method for producing the SOI device, for use in an SRAM memory having enhanced stability. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial silicon sidewall, and the performance of the FET is improved. ... 06/29/06 - 20060141692 - Method of fabricating cmos image sensor A method of fabricating a CMOS image sensor can minimize a dark current by avoiding a dry etch process of a photodiode surface. The method can also reduce a contact resistance and variation of the contact resistance of a read-out circuit unit within a unit pixel. The method includes steps ... 06/22/06 - 20060134845 - Low-voltage, multiple thin-gate oxide and low-resistance gate electrode A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in ... 05/11/06 - 20060099754 - Light guiding device A light emitting end face side front end part of an optical fiber bundle 16 is covered by a sleeve member 13 and an emitting part outer cover 14. A glass rod holding member 42, which holds a glass rod 40, is mounted to emitting part outer cover 14. Glass ... 03/16/06 - 20060057800 - Methods for treating pluralities of discrete semiconductor substrates The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the ... 03/16/06 - 20060057799 - Substrate processing apparatus A substrate processing apparatus stably and efficiently conducts a film forming process on a substrate to be processed. In the substrate processing apparatus, the substrate to be processed is supported at a position facing a heater portion, and a holding member for holding the substrate is rotated, whereby the temperature ... 01/26/06 - 20060019439 - Process for obtaining spatially-organised nanostructures on thin films A process for forming nanostructures comprising the step of applying on localised regions of a smooth thin film of bistable or multistable molecules an external perturbation with preset magnitude thereby said film undergoes a collective morphological transformation and nanostructures are formed by selforganisation of said molecules, said nanostructures having preset ... 01/12/06 - 20060008965 - Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack. ... 01/05/06 - 20060003514 - Method of forming ohmic contact to a semiconductor body A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal. ... 12/29/05 - 20050287730 - Schottky barrier cmos device and method A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant ... 12/15/05 - 20050277242 - Method for fabricating a deep trench capacitor of dram device A method for fabricating a deep trench capacitor of DRAM devices is disclosed. A substrate with a deep trench formed therein is provided. The trench is then doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the ... 12/15/05 - 20050277241 - Semiconductor device and ic card In an IC card in which an internal circuit is operated by an internal power supply formed from alternate current from outside received by an antenna, the voltage of the internal power supply sometimes changes due to the operation of the internal circuit. Therefore, the voltage controlling circuit of the ... 12/15/05 - 20050277240 - Logic components from organic field effect transistors The invention makes it possible, for the first time, to produce, despite conventional p-type MOS technology, fast logical gates based on organic field effect transistors. This is primarily due to the early saturation effect of OFETs having very thin semi-conducting layers, and, furthermore, to the use of OFETs having specific ... 11/10/05 - 20050250276 - Superlattice nanopatterning of wires and complex patterns Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by ... 11/03/05 - 20050245019 - High quality thin dielectric layer and method of making same A high quality thin dielectric layer is achieved by annealing a substrate and base oxide layer at a first temperature in a first ambient and subsequently annealing the substrate and base oxide layer at a second temperature in a second ambient, the base oxide layer overlying a top surface of ... 11/03/05 - 20050245018 - Optoelectronic component Optoelectronic component, having a housing body (2), an optoelectronic semiconductor chip (3) arranged in a recess (6) of the housing body, and having electrical terminals (1A, 1B), the semiconductor chip being electrically conductively connected to the electrical terminals of the leadframe. The housing body (2) is formed from an encapsulation ... 10/20/05 - 20050233515 - Method of etching a semiconductor device A method for etching windows 40 in a semiconductor device 10 having a metal fuse 14 embedded therein is disclosed. The method is for allowing accurate fuse blowing, in particular laser fuse blowing. The method involves the controlled removal of layers having different phase diffraction characteristics. After treatment, the remaining ... 10/06/05 - 20050221552 - Substrate support for in-situ dry clean chamber for front end of line fabrication A substrate support assembly and method for supporting a substrate are provided. In at least one embodiment, the support assembly includes a body having one or more fluid conduits disposed therethrough, and a support member disposed on a first end of the body. The support member includes one or more ... 09/29/05 - 20050215001 - Manufacturing method of semiconductor device and semiconductor device A manufacturing method of a semiconductor device disclosed herein, comprises: forming a buried insulating film in a semiconductor substrate; forming semiconductor elements isolated by the buried insulating film; cleaning a surface side of the semiconductor substrate with a cleaning solution; and covering a surface side of the buried insulating film ... 09/29/05 - 20050215000 - Etching of substrates of light emitting devices Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may ... 09/22/05 - 20050208716 - Semiconductor integrated circuit device and production method thereof A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each ... 09/15/05 - 20050202621 - Wire bond with multiple stitch bonds The invention provides a wire bond bonding a wire to a connection pad of an electronic device, and a method of forming the wire bond. A first stitch bond is formed on the connection pad, and a second stitch bond is next formed on the connection pad that is contiguous ... 09/15/05 - 20050202620 - Method to manufacture polymer memory with copper ion switching species A molecular memory cell and methods for forming a molecular memory cell, which allow for easy and inexpensive manufacturing and flexibility in memory system design. Embodiments include a non-volatile molecular memory cell, comprising: a substrate having a conductor, a superionic conductor, a polymer layer over said superionic conductor, a layer ... 09/01/05 - 20050191802 - Method of integrating the formation of a shallow junction n channel device with the formation of p channel, esd and input/output devices The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the ... 08/25/05 - 20050186724 - Method for manufacturing semiconductor integrated circuit device A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating ... 08/25/05 - 20050186723 - Methods and apparatuses for heat treatment of semiconductor films upon thermally susceptible non-conducting substrates In a method for crystallization or dopant activation heat treatment of a semiconductor film upon a thermally susceptible non-conducting substrate lying onto a susceptor, an induction coil is disposed in close proximity of the semiconductor film and disposed with the electrical current direction of the coil aligned parallel to the ... ### FreshPatents.com Support |