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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) > Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) Complementary Insulated Gate Field Effect Transistors (i.e., Cmos)Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/05/07 - 20070077698 - Method for fabricating dual-metal gate device A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the ... 04/05/07 - 20070077697 - Semiconductor device with semi-insulating substrate portions and method for forming the same A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation ... 03/29/07 - 20070072355 - Method of manufacturing semiconductor device It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate ... 03/22/07 - 20070066002 - Source capacitor enhancement for improved dynamic ir drop prevention An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides ... 03/22/07 - 20070066001 - Semiconductor device and manufacturing method thereof The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in ... 03/15/07 - 20070059875 - Semiconductor device and method of manufacturing the same, and semiconductor substrate and method of manufacturing the same A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed ... 03/15/07 - 20070059874 - Dual metal gate and method of manufacture Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned ... 03/15/07 - 20070059873 - Fabrication of single or multiple gate field plates A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a ... 03/01/07 - 20070048921 - Method for manufacturing semiconductor device A method of manufacturing a semiconductor device includes performing a first etching process on a gate electrode layer to form a gate electrode of a first transistor group including a transistor pair, and performing a second etching process different from the first etching on the gate electrode layer to form ... 03/01/07 - 20070048920 - Methods for dual metal gate cmos integration Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without ... 03/01/07 - 20070048919 - Modified hybrid orientation technology A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) ... 02/15/07 - 20070037338 - Cmos image sensor and manufacturing method thereof Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method therof, In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively ... 02/08/07 - 20070032009 - Semiconductor devices having strained dual channel layers A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium ... 02/08/07 - 20070032008 - Mos semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, ... 02/01/07 - 20070026600 - Manufacturing method of semiconductor device and semiconductor device The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region ... 02/01/07 - 20070026599 - Methods for fabricating a stressed mos device Methods are provided for fabricating a stressed MOS device. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate. The parallel MOS transistors having a common source region, a common drain region, and a common gate electrode. A first trench is ... 02/01/07 - 20070026598 - Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second ... 01/25/07 - 20070020839 - Methods to selectively protect nmos regions, pmos regions, and gate layers during epi process A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner ... 01/25/07 - 20070020838 - High performance capacitors in planar back gates cmos Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer ... 01/25/07 - 20070020837 - High performance capacitors in planar back gates cmos A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate. ... 01/18/07 - 20070015325 - Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) ... 01/11/07 - 20070010052 - Creating high voltage fets with low voltage process An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in ... 01/04/07 - 20070004120 - Method for fabricating cmos image sensor A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region in a first conductivity type semiconductor layer to form a second conductivity type first impurity region, and performing an annealing process in a gas atmosphere including first conductivity type ... 01/04/07 - 20070004119 - Cmos device with dual polycide gates and method of manufacturing the same A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well ... 01/04/07 - 20070004118 - Methods of improving drive currents by employing strain inducing sti liners A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer ... 12/28/06 - 20060292783 - Cmos transistor and method of manufacturing the same A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a ... 12/28/06 - 20060292782 - Semiconductor device and method for manufacturing the same Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film ... 12/21/06 - 20060286737 - Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. ... 12/21/06 - 20060286736 - Method for forming an electronic device An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer ... 12/14/06 - 20060281241 - Cmos fabrication A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS ... 12/14/06 - 20060281240 - Method of forming an interlayer dielectric A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and ... 12/07/06 - 20060275972 - Method of fabricating cmos inverters and integrated circuits utilizing strained surface channel mosfets A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and ... 11/30/06 - 20060270136 - High performance strained cmos devices A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in ... 11/23/06 - 20060263963 - Dual work function metal gates and methods of forming Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying ... 11/23/06 - 20060263962 - Methods of enabling polysilicon gate electrodes for high-k gate dielectrics Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high ... 11/23/06 - 20060263961 - Method for forming dual fully silicided gates and devices with dual fully silicided gates A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a different work function. The work function of each transistor type is determined by selecting a thickness of a ... 11/16/06 - 20060258075 - Gate material for semiconductor device fabrication In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step. ... 11/16/06 - 20060258074 - Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows The present invention facilitates semiconductor fabrication by providing methods of fabrication that form metal silicide gates and mitigate formation of silicide region defects near channel regions. A dielectric layer is formed over a semiconductor device (306). Polysilicon is deposited on the dielectric layer to form a gate electrode layer (308) ... 11/16/06 - 20060258073 - Method for forming a sige or sigec gate selectively in a complementary mis/mos fet device Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET ... 11/09/06 - 20060252195 - Fabrication of local interconnect lines A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure ... 11/09/06 - 20060252194 - Composite stress spacer An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET ... 11/02/06 - 20060246647 - Semiconductor cmos devices and methods with nmos high-k dielectric formed prior to core pmos silicon oxynitride dielectric formation using direct nitridation of silicon The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k ... 10/26/06 - 20060240611 - Substrate engineering for optimum cmos device performance An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has ... 10/12/06 - 20060228849 - Method of forming source/drain region of semiconductor device A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant ... 10/12/06 - 20060228848 - Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals ... 10/12/06 - 20060228847 - Method of manufacturing mos transistors First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality ... 10/05/06 - 20060223255 - Method for selectively stressing mosfets to improve charge carrier mobility A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress ... 10/05/06 - 20060223254 - Display panel drive device A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate ... 09/28/06 - 20060216882 - Using oxynitride spacer to reduce parasitic capacitance in cmos devices A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an ... 09/28/06 - 20060216881 - Method for manufacturing semiconductor device The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to ... 09/14/06 - 20060205134 - Method for manufacturing a semiconductor device and method for regulating speed of forming an insulating film A method for manufacturing a semiconductor device including sidewall insulating films with different thicknesses includes the steps of (a) selectively forming first and second gate electrode structures on first and second active regions of a silicon substrate respectively, (b) forming a first silicon oxide film on the first and second ... 09/14/06 - 20060205133 - Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide formation. A second polysilicon layer is formed over the first polysilicon layer. ... 09/07/06 - 20060199325 - Semiconductor integrated circuit device advantageous for microfabrication and manufacturing method for the same A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type which are provided in the well such that the first diffusion layers sandwich the gate electrode, the first diffusion layers ... 09/07/06 - 20060199324 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate ... 08/24/06 - 20060189061 - Cmos silicide metal gate integration The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, ... 08/24/06 - 20060189060 - Hdp-cvd methodology for forming pmd layer A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the ... 08/24/06 - 20060189059 - Intrinsic decoupling capacitor A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and ... 08/17/06 - 20060183279 - Method for selectively stressing mosfets to improve charge carrier mobility A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress ... 08/03/06 - 20060172481 - Systems and methods that selectively modify liner induced stress The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a ... 08/03/06 - 20060172480 - Single metal gate cmos device design A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a channel region defined between the source and the drain, a gate dielectric over the channel region, and a gate ... 07/27/06 - 20060166427 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film; ... 07/27/06 - 20060166426 - Methodology for placement based on circuit function and latchup sensitivity A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes ... 07/27/06 - 20060166425 - Novel gate dielectric and metal gate integration A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on ... 07/27/06 - 20060166424 - Metal gate transistor cmos process and method for making A method for forming a semiconductor device (100) includes a semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and ... 07/27/06 - 20060166423 - Removal spacer formation with carbon film A method of making a CMOS device, and a product made by the process. The process includes applying a layer of a carbon film or carbon-containing compound to a substrate. A section of the carbon is etched with a plasma, e.g., an O2, Ar, N2, or He plasma. Ion-implantation, e.g., ... 07/27/06 - 20060166422 - Sige nickel barrier structure employed in a cmos device to prevent excess diffusion of nickel used in the silicide material A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate ... 07/20/06 - 20060160293 - Cell structure of eprom device and method for fabricating the same Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes ... 07/20/06 - 20060160292 - Nfet and pfet devices and methods of fabricating same A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on ... 07/20/06 - 20060160291 - Integration of biaxial tensile strained nmos and uniaxial compressive strained pmos on the same wafer A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a ... 07/20/06 - 20060160290 - Method to fabricate variable work function gates for fusi devices An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si ... 07/06/06 - 20060148161 - Method for reducing poly-depletion in dual gate cmos fabrication process Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical ... 07/06/06 - 20060148160 - Method for fabricating cmos image sensor In a method for fabricating a CMOS image sensor, microlenses are formed with a silicon nitride layer formed on a pad such that it is possible to decrease a height of microlens and to improve a refraction ratio. In addition to main lenses in shape of curved surface, inner lenses ... 07/06/06 - 20060148159 - Cmos image sensor and fabricating method thereof A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, ... 07/06/06 - 20060148158 - Method for forming gate of semiconductor device There is provided a method for forming a gate using a gate layout of a semiconductor device. The layout includes an active region with a stepped side boundary, a plurality of gates crossing over the active region, and tabs attached to the gates on the side boundary of the active ... 07/06/06 - 20060148157 - Geometrically optimized spacer to improve device performance A CMOS device with trapezoid shaped spacers and a method for forming the same with improved critical dimension control and improved salicide formation, the CMOS device including a semiconductor substrate; a gate structure comprising a gate dielectric on the semiconductor substrate and a gate electrode on the gate dielectric; trapezoid ... 07/06/06 - 20060148156 - Gan-based permeable base transistor and method of fabrication An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. ... 07/06/06 - 20060148155 - Semiconductor fabrication and structure for field-effect and bipolar transistor devices Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After ... 06/29/06 - 20060141691 - Method for fabricating semiconductor device A method for fabricating a semiconductor memory device is provided. The method includes: forming a trench in a portion of a substrate, defined as a cell region; forming a first polysilicon layer doped with N-type impurities on regions where N-type metal-oxide-semiconductor (MOS) transistors are to be formed in the cell ... 06/29/06 - 20060141690 - Method for manufacturing a semiconductor device Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions ... 06/22/06 - 20060134844 - Method for fabricating dual work function metal gates A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming ... 06/15/06 - 20060128087 - Methods and devices for improved charge management for three-dimensional and color sensing TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably ... 06/15/06 - 20060128086 - Device having dual etch stop liner and protective layer and related methods The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device ... 06/08/06 - 20060121666 - Method for fabricating a voltage-stable pmosfet semiconductor structure A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An ... 06/08/06 - 20060121665 - Method for forming self-aligned dual salicide in cmos technologies A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding ... 06/08/06 - 20060121664 - Method for forming self-aligned dual salicide in cmos technologies A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding ... 06/08/06 - 20060121663 - Method for forming self-aligned dual fully silicided gates in cmos devices A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first ... 06/08/06 - 20060121662 - Method for forming self-aligned dual salicide in cmos technologies A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding ... 06/01/06 - 20060115944 - Methods of fabricating a semiconductor device having a node contact structure of a cmos inverter In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic ... 05/25/06 - 20060110873 - Method for fabricating cmos image sensor Form a gate electrode on a transistor region of a first conductivity type semiconductor substrate including a photodiode region and the transistor region. Form lightly-doped second conductivity type diffusion areas at both sides of the gate electrode in the photodiode region and the transistor region. Form a screen layer over ... 05/18/06 - 20060105516 - Oxidation method for altering a film structure A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed ... 05/18/06 - 20060105515 - Process options of forming silicided metal gates for advanced cmos devices Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top ... 05/11/06 - 20060099753 - Method of forming devices having three different operation voltages The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a ... 05/04/06 - 20060094182 - Transistor structure having interconnect to side of diffusion and related method A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is advantageous for use with stressed liner films since a conductor can contact ... 05/04/06 - 20060094181 - Method for fabricating semiconductor device having a trench structure Disclosed is a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having an identical width in a substrate. The method includes: selectively etching a substrate by employing tetramethylammoniumhydroxide (TMAH) solution, thereby forming ... 05/04/06 - 20060094180 - Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer. ... 04/27/06 - 20060088964 - Method of forming sram cell A method of forming an SRAM cell, having two transfer transistors, two driver transistors, and two load devices which are connected with one another in the form of a flip-flop is provided. In particular, after defining an active region and an inactive region on a silicon substrate, a gate electrode ... 04/20/06 - 20060084217 - Plasma impurification of a metal gate in a semiconductor fabrication process A semiconductor fabrication includes forming a gate dielectric overlying a semiconductor substrate and depositing a metal gate film overlying the gate dielectric. Following deposition of the metal gate film, nitrogen, carbon, and/or oxygen is introduced into the metal gate film by exposing the metal gate film to a nitrogen, carbon, ... 04/13/06 - 20060079047 - Integration of multiple gate dielectrics by surface protection A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial ... 04/13/06 - 20060079046 - Method and structure for improving cmos device reliability using combinations of insulating materials A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices includes forming a first configuration of insulating material over a first group of the CMOS devices, and forming a second configuration of insulating material over a second group of the CMOS devices. The first and said ... 04/06/06 - 20060073651 - Method for manufacturing electronic circuits integrated on a semiconductor substrate A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary ... 04/06/06 - 20060073650 - Method to selectively strain nmos devices using a cap poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a ... 03/30/06 - 20060068539 - Method of fabricating cmos type semiconductor device having dual gates According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating ... 03/23/06 - 20060063321 - Semiconductor device and method of fabricating the same A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on the gate insulating layer, the two-step gate electrode having a first gate electrode ... 03/23/06 - 20060063320 - Semiconductor process with first transistor types oriented in a first plane and second transistor types oriented in a second plane A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a ... 03/16/06 - 20060057798 - Semiconductor device and its manufacturing method The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage ... 03/16/06 - 20060057797 - Method for avoiding oxide undercut during pre-silicide clean for thin spacer fets A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical ... 03/16/06 - 20060057796 - Silicon carbide semiconductor device and its method of manufacturing method A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is ... 03/02/06 - 20060046372 - Method of fabricating semiconductor a device An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal ... 03/02/06 - 20060046371 - Methods of forming gate electrodes in semiconductor devices Method for forming gate electrode in semiconductor device are disclosed. In one example, the method may include forming a gate oxide layer on a substrate having a region where a PMOS region and a NMOS region are formed; depositing a polysilicon of rugged structure on the gate oxide layer; planarizing ... 03/02/06 - 20060046370 - Method of manufacturing a transistor with void-free gate electrode A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be deposited on the gate oxide film. P-type impurities may be implanted into the poly silicon ... 03/02/06 - 20060046369 - Semiconductor device with burried semiconductor regions A solid-state image sensor having a well of a first conductivity type; a photoelectric conversion region having a second conductivity type formed in the well storing charges obtained from a photoelectric conversion; a drain region having the second conductivity type formed in the well apart from a surface of the ... 03/02/06 - 20060046368 - Method of manufacturing schottky diode device Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on ... 03/02/06 - 20060046367 - Method to selectively recess etch regions on a wafer surface using capoly as a mask The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within ... 02/23/06 - 20060040439 - Temperature stable metal nitride gate electrode An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, ... 02/16/06 - 20060035426 - Method and apparatus for polysilicon resistor formation Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors. ... 02/16/06 - 20060035425 - Application of gate edge liner to maintain gate length cd in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove ... 02/09/06 - 20060030097 - Methods of forming different gate structures in nmos and pmos regions and gate structures so formed A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate ... 02/09/06 - 20060030096 - Methods of enabling polysilicon gate electrodes for high-k gate dieletrics Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high ... 02/09/06 - 20060030095 - Methods for elimination of arsenic based defects Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted ... 01/26/06 - 20060019438 - Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, which includes an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer having a compressive stress; and a p-channel MISFET comprising a second gate electrode and a second spacer formed ... 01/26/06 - 20060019437 - Dual work function gate electrodes obtained through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is ... 01/12/06 - 20060008964 - Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, ... 01/05/06 - 20060003513 - Formation of standard voltage threshold and low voltage threshold mosfet devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second ... 01/05/06 - 20060003512 - Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive ... 01/05/06 - 20060003511 - Method of fabricating a semiconductor device with multiple gate oxide thicknesses The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gate oxide layers with intermediate etching to remove the deposited oxide from active ... 12/22/05 - 20050282326 - Method for fabricating dual-metal gate device A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the ... 12/22/05 - 20050282325 - Structure and method to improve channel mobility by gate electrode stress modification In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case ... 12/15/05 - 20050277239 - Method for manufacturing cmos image sensor A method for manufacturing a CMOS image sensor is provided. The method includes forming a gate electrode on a semiconductor layer having defined regions of a photodiode region and a logic region, such that a gate oxide film is interposed between the semiconductor layer and the gate electrode; forming sidewall ... 12/08/05 - 20050272194 - Methods of forming integrated circuit devices including raised source/drain structures having different heights Integrated circuit devices including raised source/drain structures having different heights are disclosed. An integrated circuit device can include a first raised source/drain structure having a first height above a substrate in a first region of the integrated circuit including devices formed at a first density. The integrated circuit device can ... 12/01/05 - 20050266630 - Fabrication process of a semiconductor integrated circuit device With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in ... 11/24/05 - 20050260810 - Method for selectively forming strained etch stop layers to improve fet charge carrier mobility A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from ... 11/24/05 - 20050260809 - Semiconductor device manufacturing method There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y≧0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a ... 11/10/05 - 20050250275 - Dual work function metal gates and methods of forming Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying ... 11/10/05 - 20050250274 - Gettering using voids formed by surface transformation One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes ... 11/03/05 - 20050245017 - Structure and method to improve channel mobility by gate electrode stress modification In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case ... 11/03/05 - 20050245016 - Dual-metal cmos transistors with tunable gate electrode work function and method of making the same A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the ... 10/27/05 - 20050239242 - Structure and method of manufacturing a finfet device having stacked fins The present invention provides a device structure and method of forming a finFet device having stacked fins. The method of the present invention comprises: providing a substrate with a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor ... 10/20/05 - 20050233514 - Pmd liner nitride films and fabrication methods for improved nmos performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low ... 10/06/05 - 20050221551 - Method of forming semiconductor integrated device A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an ... 10/06/05 - 20050221550 - Dual layer semiconductor devices A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron ... 09/29/05 - 20050214999 - Method for manufacturing a mos transistor A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on ... 09/29/05 - 20050214998 - Local stress control for cmos performance enhancement A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a stress type selected from the group consisting of tensile stress and compressive stress over the respective PMOS and NMOS device regions; ... 09/29/05 - 20050214997 - Method to form local silicon-on-nothing or silicon-on-insulator wafers with tensile-strained silicon A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and ... 08/25/05 - 20050186722 - Method and structure for cmos device with stress relaxed by ion implantation of carbon or oxygen containing ions Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing ions resulting in there being no tensile stress in areas of the layer above the PMOS devices and no compressive stress in ... 07/21/05 - 20050158939 - Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of ... 07/21/05 - 20050158938 - Deep well implant structure providing latch-up resistant cmos semiconductor product A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity ... 07/21/05 - 20050158937 - Method and structure for controlling stress in a transistor channel A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of ... 07/14/05 - 20050153501 - Method for fabricating image sensor A method for fabricating an image sensor includes forming a seed layer on a semiconductor substrate, forming a blocking layer on the seed layer, partially exposing a region for transistor in an active region of the semiconductor substrate by patterning the seed layer and the blocking layer, selectively forming a ... 07/07/05 - 20050148134 - Cmos performance enhancement using localized voids and extended defects The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources ... 07/07/05 - 20050148133 - Method of making strained channel cmos transistors having lattice-mismatched epitaxial A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region having a first composition. A stress is applied at a first magnitude to a channel region of the PFET ... 07/07/05 - 20050148132 - Alignment method for fabrication of integrated ultrasonic transducer array An integrated circuit is fabricated by micromachining a hexagonal array of cMUT elements on top of a substrate comprising a hexagonal array of CMOS cells. Each cMUT element overlies a respective CMOS cell in one-to-one correspondence. During layout of the mask for micromachining the cMUT layer, either the hexagonal pattern ... 07/07/05 - 20050148131 - Method of varying etch selectivities of a film A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline film in said first region. The first ... 07/07/05 - 20050148130 - Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a hard mask and an etch stop layer on a patterned sacrificial gate electrode layer. After first and second spacers are formed on opposite sides of that patterned sacrificial layer, the patterned sacrificial layer is removed to ... 06/30/05 - 20050142724 - Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of ... 06/30/05 - 20050142723 - Method of fabricating high-voltage cmos device The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate ... 06/23/05 - 20050136584 - Strained transistor integration for cmos Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material ... 06/23/05 - 20050136583 - Advanced strained-channel technique to improve cmos performance A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the ... 06/02/05 - 20050118758 - Method for arranging layout of cmos device A method for arranging a layout of a CMOS (Complementary Metal-Oxide Semiconductor) device is provided. The current direction of the N-type MOS device is perpendicular to the P-type MOS device. The stress along one direction can be applied on both types of MOS devices to enhance the drain current and ... 06/02/05 - 20050118757 - Method for integration of silicide contacts and silicide gate metals A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in ... 06/02/05 - 20050118756 - Method for the production of image sensors The invention relates to a method for producing image sensors on the basis of TFA technology consisting including of an amorphous thin-layer system that has been applied on a crystalline ASIC. The inventive method enables the production of image sensors on the basis of TFA technology, which improve the picture ... ### FreshPatents.com Support |