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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.)Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087495 - Photomask and method for manufacturing thin film transistor An exemplary photomask (150) has a slit. The slit has at least one turning region (D1) and at least one other regions, and the slit at the at least one turning region has a narrower width than the slit at the at least one other regions. An exemplary method for ... 04/19/07 - 20070087494 - Method of manufacturing a semiconductor apparatus A method of manufacturing a semiconductor apparatus of the present invention comprises forming body diffusion layer, a gate electrode, and an interlayer dielectric over an surface of a semiconductor substrate, forming a photoresist having an opening in a region overlapping with a part of the body diffusion layer, removing the ... 04/12/07 - 20070082437 - Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon ... 03/29/07 - 20070072354 - Structures with planar strained layers A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, ... 03/29/07 - 20070072353 - Method of fabricating strained-silicon transistors and strained-silicon cmos transistors A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process ... 03/22/07 - 20070066000 - Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device including an elevated source/drain structure that can suppress emergence of a junction leak current. The method includes forming a trench on a predetermined position on a surface of a semiconductor substrate, forming an isolation layer so as to fill the trench, and so ... 03/15/07 - 20070059872 - Mos transistor gates with doped silicide and methods for making the same Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, ... 03/15/07 - 20070059871 - Semiconductor device and manufacturing method thereof In a method of manufacturing a semiconductor device, a recess is formed in a semiconductor substrate. A gate insulating film is formed on a surface of the semiconductor substrate and a surface of the recess; and a gate electrode film is deposited on the gate insulating film to fill the ... 03/08/07 - 20070054447 - Multistep etching method A multi-step etching method is provided. First, a substrate including a gate over the substrate and a spacer over the gate is provided. Then, an anisotropic etching step is performed for etching a first region and a second region in the substrate at two sides of the gate. Thereafter, an ... 03/08/07 - 20070054446 - Work function control of metals Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the ... 03/01/07 - 20070048918 - Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the ... 03/01/07 - 20070048917 - Process for producing semiconductor integrated circuit device When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W ... 03/01/07 - 20070048916 - Method for fabricating semiconductor device The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substrate 10 a hard mask 20 of a silicon oxide film 12, and a silicon nitride film 14 having a width smaller than a width of the silicon oxide film 12; etching the silicon substrate ... 02/15/07 - 20070037337 - Manufacturing method of semiconductor device A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer ... 02/15/07 - 20070037336 - Semiconductor device with improved gate resistance and method of its manufacture A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch ... 02/15/07 - 20070037335 - Dual work function cmos devices utilizing carbide based electrodes Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work ... 02/15/07 - 20070037334 - Memory device and method of manufacturing a memory device The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode ... 02/15/07 - 20070037333 - Work function separation for fully silicided gates Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a substrate, and a second metal is added to a second region of the polysilicon. A third metal is ... 02/08/07 - 20070032007 - Semiconductor device and method for fabricating the same A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating ... 02/08/07 - 20070032006 - Fabrication method of flash memory A fabrication method of a flash memory is provided. The substrate having a cell region and a peripheral circuitry region is provided. A patterned dielectric layer and a patterned conductive layer are formed on the substrate, and isolation structures are formed in the substrate. An inter gate dielectric layer and ... 02/08/07 - 20070032005 - Semiconductor device and method of fabricating the same The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; ... 02/08/07 - 20070032004 - Copper barrier reflow process employing high speed optical annealing A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ... 02/08/07 - 20070032003 - Method for forming uniaxially strained devices A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and ... 02/01/07 - 20070026597 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including a MOS transistor includes: forming a gate electrode on a semiconductor substrate via a gate insulating film; performing ion implantation on the semiconductor substrate using the gate electrode as a mask, and performing a heat treatment, thereby forming a diffusion layer in ... 02/01/07 - 20070026596 - Gate electrode structure and method of forming the same, and semiconductor transistor having the gate electrode structure and method of manufacturing the same In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is ... 02/01/07 - 20070026595 - Method for fabricating semiconductor device and method for designing semiconductor device A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate electrode of a polycrystalline silicon and having a gate length ... 02/01/07 - 20070026594 - Method and apparatus for evaluating semiconductor layers A method for evaluating semiconductor layers includes irradiating semiconductor layers on a substrate with light; measuring an optical spectrum peculiar to excitons in the semiconductor layers; and analyzing a broadening factor of optical spectral features of the optical spectrum. The method provides a quick measurement of a surface state of ... 02/01/07 - 20070026593 - Diffusion barrier for nickel silicides in a semiconductor fabrication process A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is ... 02/01/07 - 20070026592 - Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a ... 01/25/07 - 20070020835 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric ... 01/25/07 - 20070020834 - Method for forming film pattern, and method for manufacturing device, electro-optical device, electronic apparatus and active matrix substrate A method for forming a film pattern, comprises: disposing a first bank forming material to a substrate so as to form a first bank layer; disposing a second bank forming material on the first bank layer so as to form a second bank layer; and pattering the first bank layer ... 01/25/07 - 20070020833 - Method for making a semiconductor device including a channel with a non-semiconductor layer monolayer A method for making a semiconductor device may include forming at least one metal oxide semiconductor field-effect transistor (MOSFET) on a semiconductor substrate. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. ... 01/25/07 - 20070020832 - Semiconductor devices and method of fabrication A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer ... 01/25/07 - 20070020831 - Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes ... 01/25/07 - 20070020830 - Improved cmos (complementary metal oxide semiconductor) technology A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material ... 01/18/07 - 20070015324 - Fabrication method for single and dual gate spacers on a semiconductor device A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. ... 01/11/07 - 20070010051 - Method of forming a mos device with an additional layer A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain ... 01/11/07 - 20070010050 - Method for forming semiconductor devices having reduced gate edge leakage current The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch. ... 01/11/07 - 20070010049 - Thermal dissipation structures for finfets A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent ... 01/04/07 - 20070004117 - Semiconductor device and method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from ... 01/04/07 - 20070004116 - Trenched mosfet termination with tungsten plug structures A metal oxide semiconductor field effect transistor (MOSFET) device includes a termination area. The termination area has a trenched gate runner electrically connected to a trenched gate of said MOSFET. The MOSFET further includes a gate runner contact trench opened through an insulation layer covering the gate runner and into ... 01/04/07 - 20070004115 - Nand flash memory device and method of fabricating the same A NAND flash memory device includes a semiconductor substrate having a drain select transistor; a source select transistor, and memory cell transistors connected in series between the drain select transistor and the source select transistor, and an oxide film formed in the semiconductor substrate at each of a first side ... 01/04/07 - 20070004114 - Sacrificial capping layer for transistor performance enhancement A process for fabricating an n channel transistor, which results in electron mobility improvement in the channel, is described. Sacrificial capping layers comprising an oxide and nitride layer are conformally formed over a polysilicon gate after source and drain implantation, and remain in place during annealing. ... 01/04/07 - 20070004113 - Method of ic production using corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges ... 01/04/07 - 20070004112 - Method of forming thin film transistor and method of repairing defects in polysilicon layer A method of forming a thin film transistor is described. A polysilicon layer is formed over a substrate, wherein the polysilicon layer has a first region, a second region and a channel region between the first and second regions. A nitrogen doping process is carried out to dope nitrogen into ... 12/28/06 - 20060292781 - Finfets, nonvolatile memory devices including finfets, and methods of forming the same A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device ... 12/28/06 - 20060292780 - Field-effect transistor and method for producing a field-effect transistor Field-effect transistor is disclosed that includes a gate oxide, a polycrystalline layer applied on the gate oxide, and at least one spacer of polycrystalline silicon, wherein the gate oxide has a first thickness in a first region beneath the polycrystalline silicon layer and a second thickness in a second region ... 12/28/06 - 20060292779 - Structure and method for making strained channel field effect transistor using sacrificial spacer A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides ... 12/28/06 - 20060292778 - Semiconductor device and method for manufacturing the same A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel ... 12/28/06 - 20060292777 - Method for making electronic devices using metal oxide nanoparticles A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to form a semiconductor layer, and (c) optionally subjecting the resulting semiconductor layer to post-deposition processing. ... 12/28/06 - 20060292776 - Strained field effect transistors An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. ... 12/28/06 - 20060292775 - Method of manufacturing dram capable of avoiding bit line leakage A method to make DRAM capable of avoiding bit line leakage is provided. The method comprise the steps of forming transistors on substrate, forming an insulating layer to cover the substrate and the transistors, forming a poly-silicon layer over the insulating layer, forming contact holes in the poly-silicon layer and ... 12/28/06 - 20060292774 - Method for preventing metal line bridging in a semiconductor device A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a ... 12/28/06 - 20060292773 - Method of making a metal gate semiconductor device A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer ... 12/28/06 - 20060292772 - Dense pitch bulk finfet process by selective epi and etch Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate ... 12/21/06 - 20060286735 - Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped ... 12/21/06 - 20060286734 - Mim/mis structure with praseodymium titanate or praseodymium oxide as insulator material Disclosed is an electronic device with a layer succession of the metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) kind. The insulator layer contains or consists of praseodymium titanate. A metal layer or both metal layers contain titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO2) or consist of one of those ... 12/21/06 - 20060286733 - Method for manufacturing a semiconductor element A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on ... 12/21/06 - 20060286732 - Power semiconductor device A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness. ... 12/21/06 - 20060286731 - Method of fabricating conductive lines and structure of the same A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer ... 12/21/06 - 20060286730 - Semiconductor structure and method for forming thereof A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over ... 12/14/06 - 20060281239 - Cmos fabrication A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS ... 12/07/06 - 20060275970 - H-bridge drive utilizing a pair of high and low side mosfets in a common insulation housing A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided ... 12/07/06 - 20060275969 - Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually ... 12/07/06 - 20060275968 - Method for producing a contact and electronic component comprising said type of contact The invention relates to a method for the production of passivated defining surfaces (6a, 6b) between a first layer, such as a silicide (5), and an adjacent layer. Passivating elements, such as S, Se and Te are used in said layer structure during said method and the first layer is ... 11/30/06 - 20060270135 - Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die. ... 11/30/06 - 20060270134 - High-voltage metal-oxide-semiconductor devices and method of making the same An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage ion doping process. One photo mask is ... 11/30/06 - 20060270133 - Semiconductor device and its manufacturing method A semiconductor device, which can use silicon-germanium for a source/drain extension of pMOS, form a silicide layer on the source/drain, and realize a high-speed operation, is provided by comprising a gate electrode formed in a first conductive type region of a semiconductor substrate via an insulator, a first sidewall formed ... 11/23/06 - 20060263960 - Method of manufacturing a semiconductor device with different lattice properties To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A ... 11/23/06 - 20060263959 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. ... 11/16/06 - 20060258072 - Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain. ... 11/09/06 - 20060252193 - Method of forming polysilicon layers in a transistor A semiconductor transistor which is not capable of storing data is formed as follows. An insulating layer is formed over a silicon region. An undoped polysilicon layer is formed over and in contact with the insulating layer. A doped polysilicon layer is formed over and in contact with the undoped ... 11/09/06 - 20060252192 - Semiconductor device and method for fabricating the same Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed ... 11/09/06 - 20060252191 - Methodology for deposition of doped seg for raised source/drain regions A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective ... 11/09/06 - 20060252190 - Method of manufacturing spacer A method of manufacturing a spacer for a substrate having a gate structure formed thereon. The method comprises steps of forming a first oxide layer over the substrate and forming a nitride layer on the first oxide layer. A first asymmetric etching process is performed to remove a portion of ... 11/02/06 - 20060246646 - Mos device and a process for manufacturing mos devices using a dual-polysilicon layer technology with side contact A process for manufacturing a MOS device is described. The process comprising: providing a body of semiconductor material having a surface; forming a stack on the surface of the body, the stack including a first polysilicon region, an intermediate dielectric region arranged on top of the first polysilicon region, and ... 11/02/06 - 20060246645 - A mos transistor with a three-step source/drain implant A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current ... 11/02/06 - 20060246644 - Semiconductor device and method for manufacturing semiconductor device In order to manufacture a highly reliable and compact TFT, it is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a gate electrode, a source wiring and a drain wiring with high reliability, and a semiconductor device. In the method for ... 11/02/06 - 20060246643 - Memory device and semiconductor device An object of the present invention is to provide an involatile memory device that is capable of writing and erasing data at a time other than during manufacturing, and a semiconductor device having the memory device. Also, an object of the present invention is to provide a compact-sized and inexpensive ... 11/02/06 - 20060246642 - Semiconductor power device with passivation layers A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N− type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N− ... 10/26/06 - 20060240610 - Structure and method for dual-gate fet with soi substrate A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized ... 10/26/06 - 20060240609 - Semiconductor device and method for regional stress control Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried ... 10/19/06 - 20060234434 - Pecvd nitride film A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is conducted at a temperature of greater than 300° C., and utilizes ... 10/19/06 - 20060234433 - Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate comprises a layer ... 10/12/06 - 20060228846 - Process for producing soi substrate and process for regeneration of layer transferred wafer in the production A process for producing an SOI substrate includes the steps of forming an oxide film on at least the front surface of a first silicon substrate, implanting hydrogen ion from the surface of the first silicon substrate and thereby forming an ion implantation area in the inside of the first ... 10/12/06 - 20060228845 - Method for pre-retaining cb opening Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are ... 10/12/06 - 20060228844 - Integration scheme for fully silicided gate To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such as ... 10/12/06 - 20060228843 - Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to ... 10/05/06 - 20060223253 - Semiconductor device and method of manufacturing the same Provided is a semiconductor device having a structure in which: a well region of a high resistance p-type semiconductor is disposed in a given depth from a surface of an n-type or p-type semiconductor substrate; a plurality of trenches extend from the surface of the well region to a certain ... 10/05/06 - 20060223252 - Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. After forming the diffusion barrier layer, a heat treatment process ... 10/05/06 - 20060223251 - Field effect transistor and an operation method of the field effect transistor A field effect transistor includes a silicon substrate, a source electrode and a drain electrode which are formed in upper portions of the silicon substrate, and an insulator film, a PCMO film, and a gate electrode which are formed on part of the silicon substrate sandwiched between the source electrode ... 10/05/06 - 20060223250 - Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor ... 10/05/06 - 20060223249 - Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier ... 10/05/06 - 20060223248 - N+ poly on high-k dielectric for semiconductor devices The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped ... 09/28/06 - 20060216880 - Finfet devices and methods of fabricating finfet devices A semiconductor device includes a plurality of fins formed over the substrate in parallel, the fins including a first fin and a second fin adjacent to the first fin, a gate electrode formed over the substrate, the gate electrode covering a portion of the fins, and a semiconductor layer formed ... 09/21/06 - 20060211187 - Mos transistor with laser-patterned metal gate, and method for making the same A MOS transistor with a laser-patterned metal gate, and methods for its manufacture. The method generally includes forming a layer of metal-containing material on a dielectric film, wherein the dielectric film is on an electrically functional substrate comprising an inorganic semiconductor; laser patterning a metal gate from the metal-containing material ... 09/21/06 - 20060211186 - Method for forming gate in semiconductor device Disclosed herein is a method for forming a gate in a semiconductor device, which can improve the characteristics of the device. The method comprises the steps of: providing a substrate having active and field regions; selectively etching a portion of the active region to form a trench; forming on the ... 09/14/06 - 20060205132 - Scalable integrated logic and non-volatile memory A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. ... 09/14/06 - 20060205131 - Method for fabricating semiconductor device An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon, and side walls of silicon oxide are formed above an element formation region of a semiconductor substrate. In the upper portion of the element formation region of the semiconductor substrate, source ... 09/14/06 - 20060205130 - Semiconductor integrated circuit device and its manufacturing method A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in said plurality of semiconductor pillars, said plurality of nonvolatile memory ... 09/14/06 - 20060205129 - Method for manufacturing semiconductor device In a gas containing a fluorine atom in the molecule, etching of a SiN film is performed isotropically; therefore, the width of a sidewall gets smaller and it is difficult to widen the width of an LDD region. A silicon nitride film is formed over a gate electrode, a hydrogen ... 09/14/06 - 20060205128 - Integrated circuits and methods of forming a field effect transistor Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and ... 09/07/06 - 20060199323 - Semiconductor device and a method of manufacturing the same A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a ... 09/07/06 - 20060199322 - Method of manufacturing semiconductor device including air space formed around gate electrode After a HEMT is formed, side walls are formed on a semiconductor substrate. Next, a sacrificial layer is formed to cover the HEMT. Next, contact holes are formed in the sacrificial layer to expose upper surfaces of source electrodes. Next, a metal interconnect line is formed by patterning a metal ... 09/07/06 - 20060199321 - Fully salicided (fusa) mosfet structure A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop ... 09/07/06 - 20060199320 - Method for forming self-aligned, dual silicon nitride liner for cmos devices A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Portions of the first type nitride layer ... 09/07/06 - 20060199319 - Semiconductor device and manufacturing method A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different from the first conductivity type, the source region (25) being formed ... 08/31/06 - 20060194383 - Semiconductor device and method for manufacturing the same A semiconductor device includes: a second semiconductor layer formed on a side surface of a first semiconductor by epitaxial growth; a gate electrode disposed on a film formation surface of the second semiconductor layer; a source layer formed on the semiconductor layer and disposed on one side of the gate ... 08/31/06 - 20060194382 - Design and simulation methods for electrostatic protection circuits A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key ... 08/31/06 - 20060194381 - Gate structure and a transistor having asymmetric spacer elements and methods of forming the same Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a ... 08/31/06 - 20060194380 - Method for fabricating asymmetric semiconductor device A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base ... 08/31/06 - 20060194379 - Field effect transistor and method for manufacturing same A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and ... 08/24/06 - 20060189057 - Integrated electronic circuit comprising superposed components An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top ... 08/24/06 - 20060189056 - Strained channel complementary field-effect transistors and methods of manufacture A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A ... 08/24/06 - 20060189055 - Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer ... 08/24/06 - 20060189054 - Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and ... 08/24/06 - 20060189053 - Pmos transistor with discontinuous cesl and method of fabrication A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on ... 08/17/06 - 20060183278 - Field effect device having a channel of nanofabric and methods of making same Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which ... 08/17/06 - 20060183277 - Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. ... 08/10/06 - 20060177975 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric ... 08/03/06 - 20060172479 - Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated. ... 08/03/06 - 20060172478 - Method for manufacturing integrated circuit having at least one silicon-germanium heterobipolar transistor A method for manufacturing integrated circuits having at least one silicon-germanium heterobipolar transistor is provided, wherein a dielectric applied to the surface of the wafer is planarized. The dielectric having elevations produced by the thickness of monocrystalline semiconductor regions structured below the dielectric, wherein the semiconductor regions are covered by ... 08/03/06 - 20060172477 - Mos field effect transistor and manufacture method therefor An MOS field effect transistor which improves the mobility of electrons and holes of an nMOS and a pMOS by applying larger tensile stress to a stressed Si channel in a lateral direction than that applied to a conventional structure without increasing a Ge composition of a buffer SiGe layer, ... 08/03/06 - 20060172476 - Fin field effect transistor and method for manufacturing fin field effect transistor The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the ... 07/27/06 - 20060166421 - Semiconductor device fabrication method According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film ... 07/27/06 - 20060166420 - Method of manufacturing a semiconductor device In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel ... 07/20/06 - 20060160289 - Semiconductor device and method of manufacturing the same A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer ... 07/20/06 - 20060160288 - Micro-feature fill process and apparatus using hexachlorodisilane or other chlorine-containing silicon precursor A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane ... 07/13/06 - 20060154413 - Self-forming metal silicide gate for cmos devices A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) ... 07/13/06 - 20060154412 - Method for post lithographic critical dimension shrinking using thermal reflow process A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of ... 07/06/06 - 20060148153 - Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses and related devices Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided ... 07/06/06 - 20060148152 - Method of manufacturing semiconductor devices A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and then implanting impurity ions into a boundary region between ... 07/06/06 - 20060148151 - Cmos transistor junction regions formed by a cvd etching and deposition sequence This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching ... 07/06/06 - 20060148150 - Tailoring channel dopant profiles Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the ... 06/29/06 - 20060141689 - Semiconductor device and method of manufacturing the semiconductor device A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on ... 06/22/06 - 20060134843 - Mos transistor on an soi substrate with a body contact and a gate insulating film with variable thickness It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate ... 06/22/06 - 20060134842 - Method of fabricating gates A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the ... 06/15/06 - 20060128085 - Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the ... 06/15/06 - 20060128084 - Method of forming a gate pattern in a semiconductor device A gate pattern having a critical dimension after an etching process of 60-70 nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a ... 06/15/06 - 20060128083 - Method for fabricating organic thin film transistor Disclosed herein is a method for fabricating an organic thin film transistor comprising a gate electrode, a gate insulating film, source/drain electrodes and an organic semiconductor layer formed in this order on a substrate wherein the surface of the gate insulating film on which source/drain electrodes are formed is impregnated ... 06/08/06 - 20060121661 - Non-volatile memory device using mobile ionic charge and method of manufacturing the same A non-volatile memory device using mobile ionic charges and a method of manufacturing the same are provided. The method includes forming a gate dielectric layer on a semiconductor substrate, injecting mobile ionic charges into the gate dielectric layer by leading source plasma to a surface of the gate dielectric layer ... 06/08/06 - 20060121660 - Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a ... 06/08/06 - 20060121659 - Fabricating method of thin film transistor and poly-silicon layer A manufacturing method of a thin film transistor is provided. An amorphous silicon layer (a-Si layer) is formed on a substrate. A nitrogen-plasma is formed to form a silicon nitride layer on the a-Si layer, wherein the step of forming the silicone nitride layer and the step of forming the ... 06/01/06 - 20060115943 - Method of fabricating semiconductor device using low dielectric constant material film The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element ... 06/01/06 - 20060115942 - Method for manufacturing semiconductor device It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. In a manufacturing method comprising the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second ... 06/01/06 - 20060115941 - Method of fabricating transistor including buried insulating layer and transistor fabricated using the same In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer ... 06/01/06 - 20060115940 - Dual work function metal gate structure and related method of manufacture A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine. ... 06/01/06 - 20060115939 - Dual-gate device and method A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material ... 05/25/06 - 20060110872 - Method for fabricating a semiconductor structure A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned ... 05/25/06 - 20060110871 - Methods for fabricating thin film transistors Fabrication methods for thin film transistors. A metal gate stack structure is formed on an insulating substrate. The substrate is performed using thermal annealing to create an oxide layer on the sidewalls of the metal gate stack structure. A gate insulating layer is formed on the substrate covering the metal ... 05/25/06 - 20060110870 - Scalable integrated logic and non-volatile memory A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. ... 05/18/06 - 20060105514 - Thin film semiconductor device and method of manufacturing the same Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film. ... 05/18/06 - 20060105513 - Device comprising doped nano-component and method of forming the device A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising ... 05/18/06 - 20060105512 - Method to improve drive current by increasing the effective area of an electrode The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the ... 05/18/06 - 20060105511 - Method of manufacturing a mos transistor A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region ... 05/11/06 - 20060099752 - Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor ... 05/11/06 - 20060099751 - Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method An RF amplifier circuit 21 for amplifying AM broadcast signals is constituted by use of cascaded P channel MOSFETs 4 and 5. This cascade connection realizes a reduction of the feedback capacitance between the source and gate of the P channel MOSFET 4, thereby providing a stable operation. Further, using ... 05/04/06 - 20060094179 - Igbt with amorphous silicon transparent collector The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom ... 05/04/06 - 20060094178 - Method of fabricating mos transistor by millisecond anneal A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite ... 05/04/06 - 20060094177 - Semiconductor device and method for fabricating the same The semiconductor device comprises gate electrodes 50 formed on a silicon substrate 32 with a gate insulation film 48 formed therebetween, source/drain diffused layers 66n, 66p formed in the silicon substrate 32 on both sides of the gate electrodes 50, a skirt-like insulation film 58 formed on a lower part ... 05/04/06 - 20060094176 - Method for the production of a short channel field-effect transistor The invention relates to a method for fabricating a short channel field-effect transistor, comprising the steps of: forming a sublithographic gate sacrificial layer (3M), forming spacers (7S) at the side walls of the gate sacrificial layer (3M), removing the gate sacrificial layer (3M) to form a gate recess and forming ... 04/27/06 - 20060088963 - Method of manufacturing semiconductor device An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide ... 04/20/06 - 20060084216 - Transistor with strain-inducing structure in channel Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which ... 04/20/06 - 20060084215 - Semiconductor device and method for manufacturing the same Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the ... 04/20/06 - 20060084214 - Scalable gate and storage dielectric Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with ... 04/20/06 - 20060084213 - Light emitting device and method for manufacturing the same A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light ... 04/20/06 - 20060084212 - Planar substrate devices integrated with finfets and method of manufacture A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator ... 04/20/06 - 20060084211 - Method for fabricating a body contact in a finfet structure and a device including the same A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ... 04/20/06 - 20060084210 - Method of forming a low thermal resistance device and structure A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device. ... 04/20/06 - 20060084209 - Method for fabricating power mosfet A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between ... 04/13/06 - 20060079045 - Electrically erasable programmable read-only memory (eeprom) device and methods of fabricating the same An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation ... 04/13/06 - 20060079044 - Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the ... 04/13/06 - 20060079043 - Method of manufacturing semiconductor integrated circuit device A method of manufacturing a MOS transistor having sufficiently many Vth's is provided by selectively arranging a nitride film to overlap with the source and the gate electrode of the MOS transistor, and by varying an overlap amount of the nitride film with respect to the gate electrode in a ... 04/13/06 - 20060079042 - Thin film transistor and manufacturing method thereof A method for manufacturing a thin film transistor is provided. In the method, a gate electrode is formed on a substrate. A crystalline gate insulating layer is formed on an entire surface of the substrate having the gate electrode formed thereon. A microcrystalline silicon layer and a doped amorphous silicon ... 04/06/06 - 20060073649 - Method for reduced n+ diffusion in strained si on sige substrate Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N ... 03/30/06 - 20060068538 - Manufacturing method of semiconductor device A method of manufacturing a semiconductor device comprises the following steps: a step of depositing a silicon oxide film on the top surface of an epitaxial layer of the region where a high withstand voltage MOS transistor is formed; a step of subsequently depositing a silicon oxide film on the ... 03/30/06 - 20060068537 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer ... 03/30/06 - 20060068536 - Method for manufacturing semiconductor device, and semiconductor device and electronic device It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevented from scattering by providing a region where ... 03/30/06 - 20060068535 - Methods of fabricating semiconductor devices Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen ... 03/23/06 - 20060063319 - Semiconductor device and method of manufacturing the same A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the ... 03/23/06 - 20060063318 - Reducing ambipolar conduction in carbon nanotube transistors Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode. ... 03/16/06 - 20060057795 - Method of manufacturing a semiconductor integrated circuit device In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a ... 03/16/06 - 20060057794 - Semiconductor devices including high-k dielectric materials and methods of forming the same A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second ... 03/16/06 - 20060057793 - Semiconductor device and manufacturing method of the same The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n−-type offset drain region, an n-type offset drain region, ... 03/16/06 - 20060057792 - Semiconductor device having conductive spacers in sidewall regions and method for forming A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34) is formed at a top surface and a sidewall of ... 03/16/06 - 20060057791 - Method of fabricating micro-chips A method of fabricating micro-chips, including: (a) providing a substrate; (b) forming a first single-crystal layer on a top surface of the substrate; (c) forming a second single-crystal layer on a top surface of the first single-crystal layer; (d) forming integrated circuits in the second single-crystal layer; (e) forming a ... 03/09/06 - 20060051914 - Manufacturing method of semiconductor device An amorphous semiconductor film and a semiconductor film including an element selected from Group 15 of the periodic table are formed over a substrate. An island-shaped region including an island-shaped amorphous semiconductor film and an island-shaped semiconductor film is formed. A source electrode and a drain electrode are formed over ... 03/09/06 - 20060051913 - Piezoelectric element and head for jetting liquid and method for manufacturing them Provided are a piezoelectric element in which favorable crystallinity can be obtained with improved uniformity, breakage of a piezoelectric film can be prevented, and thereby stable displacement properties can be obtained, a liquid-jet head using the piezoelectric element and a manufacturing method thereof. Steps of forming a piezoelectric layer are ... 03/02/06 - 20060046365 - Method of manufacturing a thin film transistor substrate and stripping composition A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping ... 03/02/06 - 20060046364 - Method for forming a gate structure through an amorphous silicon layer and applications thereof A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in ... 02/23/06 - 20060040438 - Method for improving the thermal stability of silicide An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface ... 02/16/06 - 20060035424 - Electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. ... 02/16/06 - 20060035423 - Organic electronic component comprising the same organic material for at least two functional layers The present invention describes an organic electronic component, such as an organic field effect transistor (OFET), in which a single organic material serves for at least two functional layers, for example as conductive and as semiconductive functional material. Moreover, the invention describes an efficient method for producing, in one process ... 02/09/06 - 20060030094 - Method of manufacturing a semiconductor device with a strained channel A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element ... 02/09/06 - 20060030093 - Strained semiconductor devices and method for forming at least a portion thereof A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. ... 02/09/06 - 20060030092 - Low threshold voltage pmos apparatus and method of fabricating the same A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner ... 02/02/06 - 20060024875 - Semiconductor integrated circuit device and process for manufacturing the same In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate ... 02/02/06 - 20060024874 - Methods of forming a multi-bridge-channel mosfet A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a ... 02/02/06 - 20060024873 - Method of incorporating stress into a transistor channel by use of a backside layer The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 ... 01/26/06 - 20060019436 - Transistor of semiconductor device and method of manufacturing the same Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor ... 01/19/06 - 20060014338 - Method and structure for strained finfet devices A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device. ... 01/12/06 - 20060008963 - Method for forming polysilicon local interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, ... 01/12/06 - 20060008962 - Manufacturing method of semiconductor integrated circuit device The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and ... 01/12/06 - 20060008961 - Method of forming mos transistor having fully silicided metal gate electrode Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is ... 01/12/06 - 20060008960 - Fabrication of an eeprom cell with sige source/drain regions An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. ... 01/12/06 - 20060008959 - Layer arrangement and memory arrangement The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally ... 01/05/06 - 20060003509 - Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the ... 01/05/06 - 20060003508 - Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control ... 01/05/06 - 20060003507 - Integrated circuit devices including a dual gate stack structure and methods of forming the same Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of ... 12/29/05 - 20050287729 - Method of forming a nanocluster charge storage device In one embodiment, a method of forming a nanocluster charge storage device is provided. A first region of a semiconductor device is identified for locating one or more non-charge storage devices. A second region of the semiconductor device is identified for locating one or more charge storage devices. A gate ... 12/29/05 - 20050287728 - Method for forming a bottom gate thin film transistor using a blend solution to form a semiconducting layer and an insulating layer An improved method of forming a semiconducting polymer layer protected by an insulating polymer layer is described. In the method, a material for forming a semiconducting polymer and an insulating polymer are dissolved in a solvent. The blended solution is deposited on a substrate where the semiconducting polymer and insulating ... 12/29/05 - 20050287727 - [mos transistor and fabrication thereof] A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and ... 12/22/05 - 20050282323 - Hybrid substrate and method for fabricating the same A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on ... 12/22/05 - 20050282322 - Retaining ring with conductive portion A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The non-conductive portion contacts the substrate during polishing. The conductive portion is electrically biased during polishing to reduce the edge effect that ... 12/22/05 - 20050282321 - High-voltage mos device and fabrication thereof A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped ... 12/15/05 - 20050277238 - Method of manufacturing a semiconductor device The present invention provides a method of manufacturing a semiconductor device comprising: preparing a support substrate; forming first and second active regions and a field region in a surface of the support substrate; forming a first gate insulating film in the first and second active regions; covering the entire surface ... 12/15/05 - 20050277237 - Structure from which an integrated circuit may be fabricated and a method of making same Deep silicidation of a polysilicon gate electrode following high temperature annealing of a source/drain under the gate may damage the gate oxide. This damage is prevented by forming the gate electrode as two polysilicon layers separated by a chemical oxide. During annealing the chemical oxide prevents the grains of one ... 12/08/05 - 20050272193 - Method for manufacturing semiconductor device Disclosed is a method for manufacturing a semiconductor device. According to such a method, in forming a MOSFET to which a double spacer structure is applied, a first spacer of an oxide film is formed after only an upper gate conductive layer is primarily patterned, and then a second spacer ... 12/08/05 - 20050272192 - Methods of forming fin field effect transistors using oxidation barrier layers and related devices A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing ... 12/08/05 - 20050272191 - Replacement gate process for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a sacrificial layer on a substrate, and forming a trench within the sacrificial layer. After forming a dummy gate electrode within the trench, a hard mask is formed on the dummy gate electrode and within the trench. ... 12/01/05 - 20050266629 - Fabrication method for organic semiconductor transistor having organic polymeric gate insulating layer Provided is a method for fabricating an organic semiconductor transistor having an organic polymeric gate insulating layer. The method includes forming an organic gate insulating layer on a substrate by a vapor deposition method using organic monomer sources, and causing a polymerization reaction to occur in the organic gate insulating ... 12/01/05 - 20050266628 - Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric ... 12/01/05 - 20050266627 - Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of ... 12/01/05 - 20050266626 - Method of fabricating heteroepitaxial microstructures An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial ... 12/01/05 - 20050266625 - Cmos image sensor and fabricating method thereof A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n-type ion implantation region for a photodiode beneath a surface of the semiconductor substrate, the first n-type ion implantation region ... 12/01/05 - 20050266624 - Boron incorporated diffusion barrier material A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy ... 12/01/05 - 20050266623 - Trench power mosfet in silicon carbide and method of making the same A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region ... 12/01/05 - 20050266622 - Method for forming a low thermal budget spacer A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, ... 11/24/05 - 20050260808 - Mosfet structure with high mechanical stress in the channel The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the ... 11/24/05 - 20050260807 - Method for making a semiconductor structure using silicon germanium Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on ... 11/24/05 - 20050260806 - High performance strained channel mosfets by coupled stress effects Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices ... 11/17/05 - 20050255644 - Semiconductor device having both memory and logic circuit and its manufacture A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in ... 11/17/05 - 20050255643 - Method of forming fin field effect transistor using damascene process A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part ... 11/10/05 - 20050250273 - Display device and manufacturing method of the same The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is ... 11/10/05 - 20050250272 - Biosensor performance enhancement features and designs Isolation of semiconductor based biosensors is described. The present invention is directed to prevention of undesirable influences including, but not limited to, chip leakage current. Several forms of sensor isolation and other protective means affect protection from adverse chip influences. The effect of biochemical attachment outside the sensor active region ... 11/10/05 - 20050250271 - Dual work function gate electrodes Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. ... 11/10/05 - 20050250270 - Process of manufacturing thin film transistor A process of producing a thin film transistor includes forming a gate line on a substrate by first exposure and development processes. A source electrode, a drain electrode and a semiconductor channel are formed by second exposure and development processes. An island-shaped transistor is formed by third exposure and development ... 11/03/05 - 20050245015 - Method for manufacturing a semiconductor device having a dual-gate structure A method of manufacturing a semiconductor device having a dual-gate structure includes the steps of forming P-type and N-type gate silicon layers in different regions; implanting P-type or N-type impurities into the P-type and N-type gate silicon layers; depositing a metallic film on the P-type and N-type gate silicon layers; ... 11/03/05 - 20050245014 - Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures ... 11/03/05 - 20050245013 - Method for manufacturing a complementary metal-oxide semiconductor sensor A method for manufacturing a complementary metal-oxide semiconductor sensor is provided. The present method provides a semiconductor structure including a plurality of conductors thereon. An inter-metal dielectric layer is formed on the conductors. A silicon nitride film is applied on the inter-metal dielectric layer. An oxide layer is formed on ... 11/03/05 - 20050245012 - High performance cmos transistors using pmd linear stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a ... 11/03/05 - 20050245011 - Micromachine and method of manufacturing the micromachine In a micromachine (20) including: an input electrode (7b), an output electrode (7a), and a support electrode (7c) disposed on a substrate (4); and a band-shaped vibrator electrode (15) formed by laying a beam (vibrating part) (16) over the output electrode (7a) with a space part (A) interposed between the ... 10/27/05 - 20050239241 - High speed lateral heterojunction misfets realized by 2-dimensional bandgap engineering and methods thereof A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of ... 10/20/05 - 20050233513 - Mos transistor having a recessed gate electrode and fabrication method thereof A MOS transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes an isolation layer formed at a predetermined region of a semiconductor substrate to define an active region and double trench regions |formed in the active region. The double trench region is ... 10/13/05 - 20050227424 - Semiconductor devices having a field effect transistor and methods of fabricating the same A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. ... 10/06/05 - 20050221548 - Semiconductor device having a laterally modulated gate workfunction and method of fabrication A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric ... 09/29/05 - 20050214996 - Method of manufacturing a nonvolatile semiconductor memory device Nonvolatile semiconductor memory devices and methods for manufacturing thereof, which provide inhibiting the shortcutting of the channel due to the creation of the bird's beak to promote the manufacturing of the devices with higher-density or higher-integration, lowering the operation voltage and improving the characteristics of maintaining the electric charge, without ... 09/29/05 - 20050214995 - Lateral dmos structure with lateral extension structure for reduced charge trapping in gate oxide A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a ... 09/29/05 - 20050214994 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a conductive layer formed on the insulating film, and an etch-stop insulating film formed within the conductive layer to stop etching. ... 09/22/05 - 20050208715 - Method of fabricating fin field effect transistor using isotropic etching technique Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its ... 09/15/05 - 20050202619 - Thin film device supply body, method of fabricating thin film device, method of transfer, method of fabricating semiconductor device, and electronic equipment A technique is described in which a layer to be transferred is easily peeled and transferred to a transferred body that is pliable or flexible. Also, a method of fabricating a semiconductor device using these peeling and transfer techniques, and electronic equipment fabricated with the semiconductor device is described. A ... 09/15/05 - 20050202618 - Semiconductor device and manufacturing method of the same A manufacturing method of a semiconductor device disclosed herein comprises: forming a convex first protrusion; forming a first film, of which a surface is higher than the first protrusion; forming a mask portion on the first film; and etching the first film with the mask portion as a mask. ... 09/15/05 - 20050202617 - Gate structure for a transistor and method for fabricating the gate structure A gate structure includes a gate electrode layer stack with a doped polysilicon layer and a gate metal layer. Between the doped polysilicon layer and the gate metal layer is a barrier layer made of metal nitride for suppressing a chemical reaction between metal and silicon. A contact layer made ... 09/15/05 - 20050202616 - Mim structure and fabrication process with improved capacitance reliability An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to ... 09/15/05 - 20050202615 - Nano-enabled memory devices and anisotropic charge carrying arrays Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A thin film of nanoelements is formed on the substrate above a channel region. ... 09/01/05 - 20050191801 - Method for fabricating a field effect transistor A method for fabricating a field effect transistor, in which, after the etching of the gate electrode, the removal of the etching mask is omitted since the etching mask serves as a gate dielectric. The etching mask or the dielectric has a self-assembled monolayer of an organic compound. ... 09/01/05 - 20050191800 - Method for integrated manufacturing of split gate flash memory with high voltage mosfets A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in ... 08/25/05 - 20050186721 - Manufacturing process of semi-conductor device Exemplary embodiments discourage or prevent impurities from mixing in a film of a semiconductor layer in a manufacturing process of a semiconductor device. A manufacturing process of a semiconductor device includes first forming a semiconductor layer, second removing hydrogen from inside the semiconductor layer, and third terminating by combining elements ... 08/11/05 - 20050176196 - Method of fabricating organic field effect transistors Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a ... 08/11/05 - 20050176195 - Decoupling capacitor A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating ... 08/11/05 - 20050176194 - Transistor arrray, manufacturing method thereof and image processor An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors ... 08/11/05 - 20050176193 - Method of forming a gate of a semiconductor device In a method of forming a gate of a semiconductor device, a gate insulating layer and a polysilicon layer are successively formed on a substrate that is partitioned into a field region and an active region. A hard mask is formed on the polysilicon layer. The hard mask overlaps with ... 08/11/05 - 20050176192 - Planarization method of manufacturing a superjunction device A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method ... 08/11/05 - 20050176191 - Method for fabricating a notched gate structure of a field effect transistor A method of fabricating a gate structure of a field effect transistor comprising a gate dielectric that is notched beneath a gate electrode using an isotropic plasma etch process. In one embodiment, the etch process uses a gas comprising a halogen gas (e.g., chlorine (Cl2)), a hydrocarbon gas (e.g., methane ... 08/04/05 - 20050170576 - Transistor with reduced short channel effects and method A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second ... 08/04/05 - 20050170575 - Method of fabricating a dual gate oxide A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing ... 07/28/05 - 20050164440 - Salicided mos device and one-sided salicided mos device, and simultaneous fabrication method thereof A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first ... 07/28/05 - 20050164439 - Low volt/high volt transistor A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process ... 07/28/05 - 20050164438 - Method for manufacturing a semiconductor device A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source/drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting ... 07/28/05 - 20050164437 - Method of manufacturing semiconductor device In a method of manufacturing a semiconductor device, a preliminary metal silicide layer is selectively formed on a substrate having a transistor, the transistor having source/drain regions. A capping layer having a thermal expansion coefficient greater than that of the preliminary metal silicide layer is formed on the substrate having ... 07/21/05 - 20050158936 - Semiconductor device, method of manufacturing the same, and method of designing the same An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method ... 07/21/05 - 20050158935 - Method of forming a metal gate in a semiconductor device In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a ... 07/21/05 - 20050158934 - Semiconductor devices having field effect transistors and methods of fabricating the same A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity ... 07/21/05 - 20050158933 - Semiconductor device having a plurality of gate electrodes and manufacturing method thereof A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor ... 07/21/05 - 20050158932 - Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, comprises: providing a gate insulation layer of a high dielectric constant containing a metal element on a surface of a semiconductor substrate, part of which becoming a channel; providing a first conductive layer containing a silicon element on the surface of said gate ... 07/14/05 - 20050153500 - Method for fabricating a mos transistor A method for fabricating a MOS transistor in a semiconductor device is disclosed. An example method subjects a surface of a semiconductor substrate to thermal oxidation to form an oxide film for forming a gate insulating film, deposits a polysilicon layer on the oxide film for forming a gate, applies ... 07/14/05 - 20050153499 - Method of fabricating semiconductor device A method of fabricating a semiconductor device, provide a simplification of the fabricating process by removing a step of forming an oxide film, and vapor depositing a nitride film, after forming a gate. The method of fabricating the semiconductor device includes the steps of forming a trench, a gate insulating ... 07/14/05 - 20050153498 - Method of manufacturing p-channel mos transistor and cmos transistor A method of manufacturing a p-channel MOS transistor including forming a structure by subsequently stacking gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate. The method also includes forming first offset spacer layers on sides of the gate conductive layer pattern, forming a second-offset-spacer-layer insulating ... 07/14/05 - 20050153497 - Method of forming a fet having ultra-low on-resistance and low gate charge In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a ... 07/14/05 - 20050153496 - Low stress sidewall spacer in integrated circuit technology A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low ... 07/14/05 - 20050153495 - Silicon - germanium virtual substrate and method of fabricating the same A method of forming a relaxed silicon-germanium layer for accommodation of an overlying silicon layer formed with tensile strain, has been developed. The method features growth of multiple composite layers on a semiconductor substrate, with each composite layer comprised of an underlying silicon-germanium-carbon layer and of an overlying silicon-germanium layer, ... 07/14/05 - 20050153494 - Method of forming fet silicide gate structures incorporating inner spacers A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the ... 07/07/05 - 20050148129 - Organic semiconductor device having an active dielectric layer comprising silsesquioxanes An organic field effect transistor (FET) is described with an active dielectric layer comprising a low-temperature cured dielectric film of a liquid-deposited silsesquioxane precursor. The dielectric film comprises a silsesquioxane having a dielectric constant of greater than 2. The silsesquioxane dielectric film is advantageously prepared by curing oligomers having alkyl(methyl) ... 07/07/05 - 20050148128 - Method of manufacturing a closed cell trench mosfet Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at ... 07/07/05 - 20050148127 - Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a ... 07/07/05 - 20050148126 - Low voltage cmos structure with dynamic threshold voltage A method for dynamically varying a threshold voltage of a complimentary metal oxide semiconductor (CMOS) includes providing a substrate pickup formed a semiconductor material type which is complimentary to the semiconductor material type of a well thereof, so as to define a diode. The diode is at least partially turned ... 07/07/05 - 20050148125 - Low cost source drain elevation through poly amorphizing implant technology A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We ... 06/30/05 - 20050142722 - Method for fabricating gate electrode of semiconductor device A method of fabricating a gate electrode used for more flexible device design and higher device integrity is disclosed. A disclosed method comprises: forming a first gate electrode by etching the first insulating layer and the first polysilicon layer; forming a second insulating layer and a second polysilicon layer on ... 06/30/05 - 20050142721 - Methods of fabricating nonvolatile memory using a quantum dot A method of fabricating a nonvolatile memory using quantum dots is disclosed. An example method sequentially forms a first insulation layer and a second insulation layer on a substrate where a predetermined device is formed. The example method also forms a hard mask by etching the second insulation layer, deposits ... 06/30/05 - 20050142720 - Method for fabricating mos field effect transistor A method of fabricating a MOS field effect transistor. A gate insulating film and a gate conductive film are formed on a semiconductor substrate. The gate conductive film is patterned to form a first gate conductive film having a thin thickness and a second gate conductive film having a thick ... 06/30/05 - 20050142719 - Method of fabricating mos transistor A method of fabricating a MOS transistor includes forming a gate insulating layer on a semiconductor substrate in an active area isolated by a device isolation layer. A gate electrode is formed on a portion of the gate insulating layer. A thin insulating layer is formed to cover a top ... 06/30/05 - 20050142718 - Semiconductor device having a dual-damascene gate and manufacturing method thereof A method of manufacturing a semiconductor device having a dual-damascene gate including forming LDD regions by forming a gate oxide film on a semiconductor substrate, and by implanting lowly-concentrated impurities in the semiconductor substrate in accordance with a predetermined LDD pattern, and forming a nitride film on the gate oxide ... 06/30/05 - 20050142717 - Method of forming transistors with ultra-short gate feature A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed ... 06/30/05 - 20050142716 - Method of manufacturing semiconductor device, film-forming apparatus, and storage medium In a decompressed atmosphere and a heating atmosphere, a vapor of a hafnium organic compound is reacted with, e.g., a disilane gas in a reacting vessel, so as to form a hafnium silicate film on a silicon film. By reacting a dichlorosilane gas with a dinitrogen oxide gas, a silicon ... 06/30/05 - 20050142715 - Semiconductor device with high dielectric constant insulator and its manufacture A semiconductor device has: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a high dielectric constant insulating film including a first oxide layer formed above the silicon oxide layer and made of a high dielectric constant film having a dielectric constant higher than ... 06/30/05 - 20050142714 - Method of fabricating thin film transistor array substrate A method of fabricating a thin film transistor array substrate is provided. The method includes forming a first conductive pattern group on a substrate using a first etch resist and a first soft mold, the first conductive pattern group including a gate electrode and a gate line; forming a gate ... 06/30/05 - 20050142713 - Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, ... 06/30/05 - 20050142712 - Method for forming gate dielectric layer Provided is a method for forming a gate dielectric layer, in which a plasma oxide layer is finely formed by plasma at a temperature of 200° C. or below, and an atomic layer deposition (ALD) oxide layer is deposited. Further, the gate dielectric layer according to the present invention can ... 06/30/05 - 20050142711 - Method of manufacturing a semiconductor device Provided is a method of manufacturing a semiconductor device. In the method, an insulation spacer is formed thicker than a target thickness on sidewalls of a gate line formed on a semiconductor substrate. The thickness of the insulation spacer is adjusted by means of a wet etching process, so that ... 06/23/05 - 20050136582 - Method and device for automated layer generation for double-gate finfet designs In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a ... 06/23/05 - 20050136581 - Semiconductor memory cell and semiconductor memory device An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or ... 06/23/05 - 20050136580 - Hydrogen free formation of gate electrodes The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that ... 06/23/05 - 20050136579 - Method for manufacturing a metal oxide transistor having reduced 1/f noise The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting ... 06/16/05 - 20050130362 - Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die. ... 06/16/05 - 20050130361 - Method to reduce junction leakage current in strained silicon on silicon-germanium devices A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation ... 06/16/05 - 20050130360 - Piezo-tft cantilever mems A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially ... 06/16/05 - 20050130359 - Method and apparatus for elimination of excessive field oxide recess for thin si soi A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the ... 06/16/05 - 20050130358 - Strained finfets and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an ... 06/16/05 - 20050130357 - Method for manufacturing a thin film transistor using poly silicon A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the ... 06/09/05 - 20050124106 - Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting ... 06/09/05 - 20050124105 - Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same are provided. An underlayer film including nitrogen is formed on a predetermined region on an element isolation region, the predetermined region extending from a border of an active element forming region to the element isolation region side. Silicon or a ... 06/09/05 - 20050124104 - Methods of fabricating semiconductor device having t-shaped gate and l-shaped spacer There are provided methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer. In the method, an insulating layer and a sacrificial layer are formed in sequence on a semiconductor substrate having a vertical gate pattern. By etching the sacrificial layer, a sacrificial spacer is formed. ... 06/09/05 - 20050124103 - Method for manufacturing nand flash device Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch ... 06/09/05 - 20050124102 - Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric ... 06/09/05 - 20050124101 - Oxide/nitride stacked in finfet spacer process In a FinFET integrated circuit, the fins are formed with a body thickness in the body area and then thickened in the source/drain area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the gates are covered by a composite gate cover layer to prevent ... 06/02/05 - 20050118755 - Phosphoric acid free process for polysilicon gate definition A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a ... 06/02/05 - 20050118754 - Method for fabricating semiconductor devices using strained silicon bearing material A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second ... 06/02/05 - 20050118753 - Low cost fabrication method for high voltage, high drain current mos transistor A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions ... ### FreshPatents.com Support - Terms & Conditions |