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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions > On Insulating Substrate Or Layer (e.g., Tft, Etc.) > Having Insulated Gate > Plural Gate Electrodes (e.g., Dual Gate, Etc.) Plural Gate Electrodes (e.g., Dual Gate, Etc.)Plural Gate Electrodes (e.g., Dual Gate, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/01/07 - 20070048914 - Method of fabricating dual gate electrode of cmos semiconductor device In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form ... 01/25/07 - 20070020827 - Methods of forming semiconductor device A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type ... 01/04/07 - 20070004107 - Methods for fabricating integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped ... 12/28/06 - 20060292765 - Method for making a finfet including a superlattice A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups ... 12/14/06 - 20060281236 - Method and apparatus for improving stability of a 6t cmos sram cell The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate ... 11/30/06 - 20060270127 - Method of forming dual gate variable vt device A dual gate device having independently adjusted voltage thresholds with improved performance and reliability and method for forming the same, the method including providing a semiconductor substrate comprising a first gate structure on a first gate dielectric layer overlying a high voltage threshold (HVT) portion of the semiconductor substrate; then ... 10/19/06 - 20060234431 - Doping of semiconductor fin devices A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. ... 07/13/06 - 20060154409 - Method for fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every ... 04/06/06 - 20060073647 - Semiconductor device and manufacturing method thereof A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain ... 01/19/06 - 20060014336 - Method of forming double-gated silicon-on-insulator (soi) transistors with corner rounding A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, ... 09/15/05 - 20050202607 - Method of forming finfet gates without long etches A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that ... 08/11/05 - 20050176186 - Field effect transistor and method for manufacturing the same In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of ... 07/21/05 - 20050158927 - Structure and method of forming a notched gate field effect transistor The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then ... 06/30/05 - 20050142703 - Dual-gate transistor device and method of forming a dual-gate transistor device Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor ... ### FreshPatents.com Support |