FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents

Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions

Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Semiconductor Device Manufacturing: Process


Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions



Reducing wafer distortion through a high cte layer
08/28/14 - 20140242759 - Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of...

Through-substrate vias
12/06/12 - 20120309135 - A method of etching through-substrate vias comprising depositing a layer of embossable material on a first side and a second side of a thin-film stack, the thin-film stack including a base substrate, embossing the embossable material deposited on the first side and the second side of the thin-film stack with...

Implantation shadowing effect reduction using thermal bake process
07/01/10 - 20100167472 - A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a...

Semiconductor device and fabrication method for the semiconductor device
07/01/10 - 20100167473 - A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field...

Method of producing a field effect transistor arrangement
02/18/10 - 20100041185 - A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer...

Method for fabricating a cmos-compatible mems device
02/11/10 - 20100035387 - A method for fabricating a CMOS-compatible MEMS device is disclosed. In particular, disclosed is a method of ordering the acts in the fabrication process of the two device types such that one device type will not be damaged by the fabrication process of the other device type. One aspect of...

Field effect semiconductor diodes and processing techniques
02/04/10 - 20100029048 - Field effect semiconductor diodes and improved processing techniques for forming the field effect semiconductor diodes having semiconductor layers forming a source, a body and a drain of a field effect device, the semiconductor layers forming pedestals having an insulating layer and a gate on sides thereof vertically spanning the body...

Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby
10/15/09 - 20090258463 - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite...

Method for fabricating a nitride fet including passivation layers
06/11/09 - 20090148985 - A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current...

Method of manufacturing nanowires parallel to the supporting substrate
05/14/09 - 20090124050 - the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire....