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Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active RegionsMaking Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/22/07 - 20070065990 - Recursive spacer defined patterning A method for the patterning of a plurality of fins in a MugFET device is provided. The method involves depositing at least one temporary pattern using photolithography. Further processing steps include a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very ... 03/08/07 - 20070054440 - Method for fabricating a device with flexible substrate and method for stripping flexible-substrate A method for fabricating a device with flexible substrate includes providing a rigid substrate. Then, a flexible substrate layer is directly formed on the rigid substrate, wherein the flexible substrate layer fully contacts the rigid substrate and a contact interface is formed. A device structure is formed on the flexible ... 03/01/07 - 20070048909 - Superjunction device with improved ruggedness An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension ... 03/01/07 - 20070048908 - Method and apparatus for fabricating a carbon nanotube transistor A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least ... 03/01/07 - 20070048907 - Methods of forming nmos/pmos transistors with source/drains including strained materials and devices so formed A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein. ... 03/01/07 - 20070048906 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed in which a doping depth of an ion implanted dopant is prevented from being increased during annealing, so as to form a junction having a depth of 20 nm or below without any problem in the technology of 65 nm or ... 02/22/07 - 20070042535 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate ... 02/08/07 - 20070031999 - Non-volatile memory cells and methods of manufacturing the same Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least ... 02/01/07 - 20070026578 - Method for forming a silicided gate A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally treated ... 01/25/07 - 20070020820 - Process for forming an electronic device including discontinuous storage elements A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can ... 01/18/07 - 20070015317 - Method of forming metal line and contact plug of flash memory device A method of forming a metal line and a contact plug of a flash memory device, wherein if first, second, and third etch processes are performed on an anti-reflection film and regions (a region in which a contact plug through which a gate is exposed is formed/a region in which ... 01/04/07 - 20070004099 - Nand flash memory device and method of manufacturing the same A method of manufacturing a non-volatile memory device includes forming a first conductive layer over a tunnel dielectric layer that is provided on a semiconductor substrate. A non-conductive layer is formed over the first conductive film. The non-conductive layer is etched to define a stack structure between first and second ... 11/30/06 - 20060270119 - Methods of forming implant regions relative to transistor gates The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form at least one ... 11/23/06 - 20060263948 - Method for manufacturing semicondutor device A gate oxide film, a gate electrode and low-concentration N type diffusion layers are first formed in a device forming region of a P type silicon substrate. A insulating film is deposited over them and anisotropically etched to form sidewalls. Subsequently, a gate oxide film, a gate electrode and low-concentration ... 08/24/06 - 20060189044 - High reliability multilayer circuit substrates and methods for their formation A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow ... 08/24/06 - 20060189043 - Trench-gate electrode for finfet device A FinFET device having a trench-gate electrode, and a method of manufacture, is provided. The trench-gate electrode may be fabricated by forming a mask layer on a substrate having a semiconductor layer, e.g., silicon, formed thereon. A trench is formed in the mask layer and fins are formed in the ... 08/17/06 - 20060183272 - Atomic layer deposition of zr3n4/zro2 films as gate dielectrics The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr3N4) and zirconium oxide (ZrO2) and a method of fabricating such a dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing zirconium oxide using ... 07/13/06 - 20060154406 - Method of manufacturing transistor, method of manufacturing electro-optical device, and method of manufacturing electronic device A method of manufacturing a transistor includes disposing a droplet containing a bank material as a solute or a dispersoid on a substrate, drying the droplet to form a bank, ejecting a conductive material on a part of the bank to form a first conductive region and a second conductive ... 06/29/06 - 20060141682 - Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, ... 05/18/06 - 20060105505 - Method for producing a semiconductor component and semiconductor component produced by the same A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode. ... 05/11/06 - 20060099744 - System and method for improved dopant profiles in cmos transistors According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer ... 05/04/06 - 20060094167 - Embedded rom device using substrate leakage A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques ... 05/04/06 - 20060094166 - Method of manufacturing a thin film transistor, a thin film transistor manufactured by the method, a method of manufacturing flat panel display device, and a flat panel display device manufactured by the method Provided are a method of manufacturing a plastic substrate having a TFT, a substrate manufactured thereby, a method of manufacturing a flat panel display device, and a flat display device manufactured thereby, which can be used for a flexible flat display device. The method includes: preparing a film in which ... 04/27/06 - 20060088959 - Processing method and processing apparatus A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby ... 04/13/06 - 20060079030 - Method of fabricating t-type gate Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking ... 04/06/06 - 20060073643 - Transistor with doped gate dielectric A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped region of the workpiece are outdiffused into the gate dielectric, creating a ... 03/30/06 - 20060068529 - Self-aligned split-gate nand flash memory and fabrication process Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with ... 03/23/06 - 20060063314 - Field effect transistor and method of manufacturing the same A field effect transistor according to one embodiment of the present invention is a field effect transistor which is supposed to be operated under a temperature condition at 300 K or less, comprising: an n-channel field effect transistor having a gate electrode formed by a gate electrode material having a ... 03/09/06 - 20060051903 - Method of manufacturing thin film semiconductor device, and thin film semiconductor device TFTs are formed on a substrate, and a layer insulation film containing no hydroxyl group in at least a lowermost layer film is formed in the state of covering the TFTs. Thereafter, a heat treatment is conducted in a moisture atmosphere, whereby oxygen or hydrogen is bound to dangling bonds ... 01/19/06 - 20060014329 - Nanodots formed on silicon oxide and method of manufacturing the same A nanodot material including nanodots formed on silicon oxide, and a method of manufacturing the same, is provided. The nanodot material includes a substrate, a silicon oxide layer, and a plurality of nanodots on the silicon oxide layer. ... 01/12/06 - 20060008950 - Vertical tunneling transistor The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis ... 01/05/06 - 20060003499 - Removing a high-k gate dielectric A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid. ... 11/24/05 - 20050260798 - Method of forming a negative differential resistance device A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed. ... 11/17/05 - 20050255638 - Trench corner effect bidirectional flash memory cell A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the ... 11/10/05 - 20050250258 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed ... 10/06/05 - 20050221541 - Ultra thin back-illuminated photodiode array fabrication methods Ultra thin back-illuminated photodiode array fabrication methods providing backside contact by diffused regions extending through the array substrate. In accordance with the methods, a matrix is diffused into one surface of a substrate, and at a later stage of the substrate processing, the substrate is reduced in thickness and a ... 09/01/05 - 20050191795 - Method of manufacture of finfet devices with t-shaped fins and devices manufactured thereby An FET device comprises a semiconductor structure with a source island, a drain island over a horizontal surface of a substrate comprising an insulating material. A channel structure over the horizontal surface of the substrate connects between the drain and the source, with the channel structure comprising a horizontal semiconductor ... 07/14/05 - 20050153485 - Narrow-body damascene tri-gate finfet A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in ... 07/07/05 - 20050148120 - Polycide gate stucture and manufacturing method thereof A polycide gate structure and the manufacturing method thereof are provided. The manufacturing method includes the following steps of: (a) providing a substrate; (b) forming a polysilicon layer and a silicide layer upon the substrate separately; (c) removing a part of the silicide layer for defining a silicide structure having ... ### FreshPatents.com Support |