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Semiconductor Device Manufacturing: Process > Making Device Array And Selectively Interconnecting > Using Structure Alterable To Conductive State (i.e., Antifuse) Using Structure Alterable To Conductive State (i.e., Antifuse)Using Structure Alterable To Conductive State (i.e., Antifuse) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.12/28/06 - 20060292754 - Antifuse element and method of manufacture An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and ... 11/23/06 - 20060263946 - Recessed gate dielectric antifuse A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the ... 06/29/06 - 20060141679 - Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum ... 06/22/06 - 20060134837 - Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum ... 06/15/06 - 20060128072 - Method of protecting fuses in an integrated circuit die A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; ... 06/15/06 - 20060128071 - Integrated antifuse structure for finfet and cmos devices A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in ... 08/04/05 - 20050170563 - Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between ... 06/30/05 - 20050142698 - Method for fabricating split gate flash memory device A method for fabricating a split gate flash memory includes depositing a second conductive layer for forming a control gate on a semiconductor substrate having a first conductive layer, an insulating layer, and an oxide layer on both sides of the first conductive layer formed thereon, filling an anti-implant protective ... ### FreshPatents.com Support |