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Semiconductor Device Manufacturing: Process > Making Device Array And Selectively Interconnecting > With Electrical Circuit Layout With Electrical Circuit LayoutWith Electrical Circuit Layout patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/04/07 - 20070004097 - Substrate warpage control and continuous electrical enhancement A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as ... 11/09/06 - 20060252185 - Inkjet printing system and driving method thereof An inkjet printing system is provided, which includes a first stage mounted with a mother glass including a plurality of substrates and a plurality of alignment keys, a head unit having at least one inkjet head, an alignment key position sensor for sensing positions of the alignment keys to generate ... 10/05/06 - 20060223241 - Electronic device fabrication A system performs a method including contact printing one of a wetting agent and a non-wetting agent on a semiconductor and inkjet printing an electrically conductive material proximate said one of the wetting agent and the non-wetting agent. ... 09/28/06 - 20060216869 - Lithographic apparatus, device manufacturing method, code reading device and substrate A two-dimensional mark has an array of pixels, and one or more reference marks. The array of pixels is used to encode an identifier for the substrate and/or any other desired information. In an embodiment, the array is 8 by 8 pixels providing 264 unique symbols, assuming a binary system ... 09/21/06 - 20060211178 - Fabrication of lean-free stacked capacitors For fabricating lean-free stacked capacitors, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support ... 09/14/06 - 20060205121 - Method and system for high-speed, precise micromachining an array of devices A method and system for high-speed, precise micromachining an array of devices are disclosed wherein improved process throughput and accuracy, such as resistor trimming accuracy, are provided. The number of resistance measurements are limited by using non-measurement cuts, using non-sequential collinear cutting, using spot fan-out parallel cutting, and using a ... 08/24/06 - 20060189041 - Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to ... 06/29/06 - 20060141678 - Forming a nanotube switch and structures formed thereby Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising a power pad, and attaching a nanotube comprising at least one side chain to the power pad. ... 05/04/06 - 20060094164 - Semiconductor integrated device, design method thereof, designing apparatus thereof, program thereof, manufacturing method thereof, and manufacturing apparatus thereof Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 provided insulated from a transistor diffusion layer 11, wirings 13 and 14 connected to the gate 12, a wiring 15 parallel to ... 04/27/06 - 20060088958 - Integrated circuit with multi-length output transistor segment A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the ... 03/02/06 - 20060046353 - Optimizing dynamic power characteristics of an integrated circuit chip The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes ... ### FreshPatents.com Support |