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Semiconductor Device Manufacturing: Process > Making Device Array And Selectively Interconnecting Making Device Array And Selectively InterconnectingMaking Device Array And Selectively Interconnecting patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087484 - Heating element of a printhead having resistive layer over conductive layer A heating element of a printhead has a conductive layer deposited over a substrate, and a resistive layer deposited over and in electrical contact with the conductive layer. ... 04/12/07 - 20070082431 - Programmable fuse with silicon germanium A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the ... 03/15/07 - 20070059867 - Method of manufacturing an optical module Manufacturing an optical module includes providing a frame, attaching a light-emitting diode chip and a sensor chip to the frame, and forming overcoats on the light-emitting diode chip and the sensor chip. Each of the overcoats includes a lens. The overcoats can prevent internal chips from being damaged and suffering ... 02/15/07 - 20070037322 - End electrode structure of a surface-mounted resettable over-current protection device The present invention relates to an end electrode structure of a surface-mounted resettable over-current protection device. A polymer-based sheet is punched with a mold for manufacturing a plurality of H-shaped through-holes separated at an equal interval, such that several strip-shaped sheets are formed. Then, a first pair of electrodes and ... 01/25/07 - 20070020818 - Esd protection device in high voltage and manufacturing method for the same Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one ... 12/21/06 - 20060286723 - Electrode structure, fabrication method thereof and pdp utilizing the same An electrode structure for a front board of a plasma display panel (PDP). The electronic structure connects all the sustain electrodes on the front board to prevent data transformation errors caused by holes. The fabrication method of the electronic structure is also disclosed. ... 12/07/06 - 20060275957 - Semiconductor device A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their ... 12/07/06 - 20060275956 - Cross-linked carbon nanotubes Cross-linked carbon nanotube arrays forming a three-dimensional structure and methods of use including high thermal conductivity, high strength applications where repeated cycling is known, and chemical storage. ... 12/07/06 - 20060275955 - Patterned nanorod arrays and methods of making same In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In ... 11/16/06 - 20060258059 - Contact portion and manufacturing method thereof, thin film transistor array panel and manufacturing method thereof A method of manufacturing a contact portion is provided, which includes: forming a first signal line on a substrate (110), forming a insulating layer (140) covering the first signal line and having a contact hole (182, 185) exposing the first signal line; forming a contact layer (700) on the exposed ... 11/09/06 - 20060252184 - Semiconductor integrated circuit and electronic equipment In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in ... 09/14/06 - 20060205120 - Flash memory cell arrays having dual control gates per memory cell charge storage element A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory ... 09/07/06 - 20060199310 - Semiconductor integrated circuit and semiconductor device A semiconductor integrated circuit includes a substrate having a main surface to which a first stress is applied; a first channel conductive field effect transistor placed in a first region of the main surface of the substrate, the carrier mobility of a channel of the first channel conductive field effect ... 08/17/06 - 20060183271 - High density stepped, non-planar nitride read only memory A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The ... 06/15/06 - 20060128070 - Non-volatile memory device and fabricating method thereof A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern. ... 06/08/06 - 20060121650 - Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond ... 05/25/06 - 20060110861 - Integrated circuit with multi-length power transistor segments A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At ... 05/25/06 - 20060110860 - Self-adjusting serial circuit of thin layers and method for production thereof The invention relates to a self-adjusting serial circuit of thin layers and method for production thereof. The invention is characterised in that electrically conducting conductor tracks (20) are applied to a substrate (10), whereupon several main deposit layers (30, 40, 50) of conducting, semi-conducting or insulating materials are applied to ... 05/11/06 - 20060099743 - Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells. ... 03/16/06 - 20060057783 - Methods of forming fuses using selective etching of capping layers A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse and removing the capping layer from the fuse to expose a fuse metal film thereunder. ... 12/29/05 - 20050287717 - Methods and devices for forming nanostructure monolayers and devices including such monolayers Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). ... 10/20/05 - 20050233505 - Method of manufacturing a semiconductor memory device Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating ... 09/15/05 - 20050202599 - Method of forming metal pattern having low resistivity Disclosed herein is a method for forming a metal pattern with a low resistivity. The method comprises the steps of: (i) coating a photocatalytic compound onto a substrate to form a photocatalytic film layer; (ii) coating a water-soluble polymeric compound onto the photocatalytic film layer to form a water-soluble polymer ... 08/25/05 - 20050186715 - Method of an array of structures sensitive to esd and structure made therefrom A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic ... 08/25/05 - 20050186714 - Method of fabricating an integrated circuit through utilizing metal layers to program randomly positioned basic units A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit ... 07/07/05 - 20050148117 - Method for fabricating a flash-preventing window ball grid array semiconductor package A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a through hole and has a surface formed with a plurality of wire-bonding portions, ball-bonding portions and intended-exposing regions. A chip ... 06/30/05 - 20050142697 - Fabrication method of semiconductor integrated circuit device A probe card is formed of a main board and a sub-board located above the principal surface of the main board. The sub-board is located inside of an internal circumferential pad region of the main board. Relays are arranged in a line along the external circumference of the upper surface ... 06/16/05 - 20050130352 - High density dram with reduced peripheral device area and method of manufacture A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously. ... 06/16/05 - 20050130351 - Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a ... 06/09/05 - 20050124096 - Manufacturing methods for printed circuit boards A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first ... 06/09/05 - 20050124095 - Sram device having high aspect ratio cell boundary A static random access memory (SRAM) device including a substrate and an SRAM unit cell. The substrate includes an n-doped region interposing first and second p-doped regions. The SRAM unit cell includes: (1) a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped ... 06/02/05 - 20050118750 - Wiring board sheet and its manufacturing method,multilayer board and its manufacturing method A wiring board sheet which enables the miniaturization of a wiring board by mounting electric components (10) in an insulation layer (4) to increase the quantity of mounting electric components, has a high reliability, and undergoes a complicated manufacturing process, and a method for manufacturing the wiring board sheet A ... ### FreshPatents.com Support |