REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Semiconductor Device Manufacturing: Process > Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor > Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device > Stacked Array (e.g., Rectifier, Etc.) Stacked Array (e.g., Rectifier, Etc.)Stacked Array (e.g., Rectifier, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/12/07 - 20070082429 - Semiconductor substrate for build-up packages The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward ... 03/22/07 - 20070065987 - Stacked mass storage flash memory package A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent ... 03/22/07 - 20070065986 - Method for manufacturing substrate with cavity A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second ... 03/15/07 - 20070059862 - Multiple chip semiconductor package A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality ... 02/15/07 - 20070037321 - semiconductor device and a manufacturing method of the same The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material ... 01/18/07 - 20070015314 - Adhesive/spacer island structure for multiple die package An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of ... 12/28/06 - 20060292746 - Stacked die in die bga package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. ... 12/28/06 - 20060292745 - Stacked die in die bga package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. ... 11/30/06 - 20060270112 - Overhang support for a stacked semiconductor device, and method of forming thereof A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer ... 11/23/06 - 20060263939 - Device and method for including passive components in a chip scale package The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the ... 11/23/06 - 20060263938 - Stacked module systems and method A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and ... 11/02/06 - 20060246624 - Semiconductor device with semiconductor chip and rewiring layer and method for producing the same The invention relates to a semiconductor device with a semiconductor chip and a rewiring layer, the semiconductor chip being embedded in a housing plastics composition by its rear side contact. The active top side of the semiconductor chip forms a coplanar overall top side with the top side of the ... 10/12/06 - 20060228830 - Chip-embedded support-frame board wrapped by folded flexible circuit for multiplying packing density The present invention includes a chip-embedded support-frame wrapped-by-flex-circuit package assembly. The package assembly includes a flex circuit having a plurality of patterned connecting-traces. The package assembly further includes a plurality of semiconductor chips mounted on the flex circuits wherein the semiconductor chips having a plurality of contact terminals connected to ... 10/05/06 - 20060223233 - Apparatus and method for heating substrates An apparatus for processing substrates is disclosed. In one embodiment, the apparatus includes a housing and a plurality of stacked cell structures in the housing. An actuator is adapted to move the plurality of stacked cell structures inside of the housing while substrates in the stacked cell structures are being ... 10/05/06 - 20060223232 - Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof A method for manufacturing a semiconductor device includes the steps of (a) preparing a wafer including a first circuit formation region and a first surrounding region, (b) laminating a first chip on the first circuit formation region, (c) pouring a first underfill into a first space between the first circuit ... 09/07/06 - 20060199307 - Ultra thin dual chip image sensor package structure and method for fabrication A stacked image sensor package contains an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is ... 09/07/06 - 20060199306 - Chip structure and manufacturing process thereof A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer ... 08/31/06 - 20060194368 - Thin film translator array panel and a method for manufacturing the panel A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant ... 08/24/06 - 20060189033 - Integrated circuit package-in-package system A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first ... 08/24/06 - 20060189032 - Process for assembling a double-sided circuit component A process for producing a circuit component having a double-sided circuit device between a pair of substrates. The process entails depositing a solder material on contact areas on surfaces of the substrates, placing a first of the substrates within a cavity in a receptacle, and then placing a lead member ... 08/10/06 - 20060177967 - Manufacturing method of semiconductor device A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a ... 08/03/06 - 20060172463 - Semiconductor multi-package module having wire bond interconnect between stacked packages A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate ... 08/03/06 - 20060172462 - Semiconductor multi-package module having inverted land grid array (lga) package stacked over ball grid array (bga) package A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a ... 08/03/06 - 20060172461 - Semiconductor stacked multi-package module having inverted second package A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing ... 07/27/06 - 20060166405 - Manufacturing method of semiconductor device A method of manufacturing a semiconductor device including a die pad section, a first semiconductor chip having a surface on which a first electrode section is formed, a second semiconductor chip having a surface on which a second electrode section is formed, a support member having a surface, lead terminal ... 07/27/06 - 20060166404 - Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially planar member and at a location that ... 07/27/06 - 20060166403 - Fabrication of advanced silicon-based mems devices A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a ... 07/20/06 - 20060160271 - Stacked semiconductor module The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable ... 06/15/06 - 20060128061 - Fabrication of stacked die and structures formed thereby Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die ... 06/15/06 - 20060128060 - Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided ... 06/08/06 - 20060121645 - Method of fabrication of stacked semiconductor devices A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the ... 06/01/06 - 20060115930 - Semiconductor device and method of fabricating the same, circuit board, and electronic instrument A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the ... 06/01/06 - 20060115929 - Die-to-die connection method and assemblies and packages including dice so connected A method for assembling semiconductor dice includes orienting at least one second semiconductor die with the active surface thereof facing the active surface of a first semiconductor die. A structure on an active surface of one of the semiconductor dice may interact with a peripheral edge or other feature of ... 05/04/06 - 20060094160 - Die stacking scheme An improved semiconductor die stacking scheme is provided. In accordance with one embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. In accordance with another embodiment of the present invention a multiple die semiconductor assembly is provided. Each embodiment relates generally to a ... 04/13/06 - 20060079023 - Semiconductor device and manufacturing method for the same A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, ... 04/06/06 - 20060073637 - Method for manufacturing semiconductor device and semiconductor device A semiconductor device includes: a connecting body including a connecting electrode; and at least one semiconductor chip stacked on the connecting body, the semiconductor chip including: a substrate; and a trans-substrate conductive plug that penetrates the substrate, the trans-substrate conductive plug having a first terminal that is provided on an ... 04/06/06 - 20060073636 - Fabrication of stacked die and structures formed thereby Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die ... 04/06/06 - 20060073635 - Three dimensional package type stacking for thinner package application A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is ... 03/30/06 - 20060068523 - Integrated circuit package Two integrated circuits 1, 3, 101, 103 having circuitry on one of their major surfaces 11, 31, 111, 131 are ground on their opposite major surfaces 13, 33 to reduce their thickness. The ground integrated circuits are then adhered together to form a composite body 7 and placed in a ... 03/16/06 - 20060057776 - Wafer stacking package method A method of wafer stacking packaging. The method comprises providing a die array including a plurality of singulated first dies cut from a first wafer; providing a second wafer with inseparate the second dies and an adhesive layer on an active surface thereof; pre-cuting the second wafer to a specified ... 03/09/06 - 20060051896 - Stacking circuit elements A method of stacking dice in an electronic circuit includes controlling a size of a hole made in a connection pad on each die of said dice to selectively provide an electrical connection to a particular die in the stack. Additionally, a method of stacking dice in an electronic circuit ... 02/16/06 - 20060035409 - Methods and apparatuses for providing stacked-die devices Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each ... 01/19/06 - 20060014319 - Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When ... 01/12/06 - 20060008946 - Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When ... 01/12/06 - 20060008945 - Integrated circuit stacking system and method The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, ... 01/12/06 - 20060008944 - Substrate having built-in semiconductor apparatus and manufacturing method thereof A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor chip and protrudes from a side surface of the first semiconductor ... 12/08/05 - 20050272183 - Arrayed ultrasonic transducer An ultrasonic transducer comprises a stack having a first face, an opposed second face and a longitudinal axis extending therebetween. The stack comprises a plurality of layers, each layer having a top surface and an opposed bottom surface, wherein the plurality of layers of the stack comprises a piezoelectric layer ... 12/01/05 - 20050266614 - Method of manufacturing semiconductor device and method of manufacturing electronic device A method of manufacturing a semiconductor device includes mounting a first semiconductor chip on each partitioned region of a frame substrate partitioned for each first semiconductor package; mounting a second semiconductor package, where a second semiconductor chip is mounted, on each partitioned region of the frame substrate so as to ... 10/27/05 - 20050239234 - Method of making assemblies having stacked semiconductor chips A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member ... 10/20/05 - 20050233497 - Method of forming a multi-die semiconductor package Some embodiments of the invention relate to a method of packaging multiple dice into a semiconducting device. The method includes placing a first capsule that includes a first die onto a front side of a tape substrate, placing a second capsule that includes a second die onto the front side ... 10/20/05 - 20050233496 - Method of making assemblies having stacked semiconductor chips A stacked microelectronic assembly comprises a flexible sheet having an obverse surface and a reverse surface and including at least a first panel and a second panel. The second panel and the first panel are adjacent to each other, the second panel including terminals on the reverse surface for mounting ... 10/06/05 - 20050221534 - Stress-relief layer and stress-compensation collar in contact arrays, and processes of making same A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is ... 09/22/05 - 20050208706 - Method of creating multi-layered monolithic circuit structure containing integral buried and trimmed components A method of creating a multi-layered monolithic circuit structure wherein individual layers of standard alumina thick film ceramic substrate and the resistors, inductors, capacitors, and other circuit componentry printed thereon are fired, and the circuit componentry trimmed or otherwise adjusted to achieve a desired degree of precision prior to combining ... 09/15/05 - 20050202594 - Vacuum sealed microdevice packaging with getters One embodiment of the invention relates to a microdevice package containing getters for maintaining a constant vacuum level within the sealed microdevice package. A stacked wafer assembly, containing a plurality of microdevice packages, is formed by aligning a bottom cover wafer with a center wafer. The bottom cover wafer includes ... 09/01/05 - 20050191791 - Methods for dicing wafer stacks to provide access to interior structures Methods for dicing water stacks are provided. Preferably, the method includes the steps of: (1) providing a wafer stack having a first wafer and a second wafer; (2) exposing a portion of the first wafer by removing a portion of the second wafer; and (3) dicing the exposed portion of ... 08/25/05 - 20050186706 - Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has ... 08/04/05 - 20050170558 - Method of forming a stack of packaged memory dice A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry. ... 07/21/05 - 20050158912 - Low profile multi-ic chip package connector A low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the ... 07/07/05 - 20050148113 - Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (bga) package A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball ... 06/30/05 - 20050142695 - Induction-based heating for chip attach A method for bonding a semiconductor die to a substrate is described. The method comprises arranging a semiconductor die, an interconnect, and a substrate in a suitable configuration and using induction heating to form the bond. ... 06/30/05 - 20050142694 - Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges Memory chips are assembled into a stack with an insertion-pin frame between pins of two stacked memory chips. The insertion-pin frame is not bent or formed into 3-dimensional shapes but is flat, improving use in standard surface-mount processes such as solder printing onto the insertion-pin frame. Flat insertion pins held ... ### FreshPatents.com Support |