REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Semiconductor Device Manufacturing: Process > Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor > Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device > Flip-chip-type Assembly Flip-chip-type AssemblyFlip-chip-type Assembly patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087479 - Method of manufacturing low cte substrates for use with low-k flip-chip package devices Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one ... 03/22/07 - 20070065985 - Bonding apparatus and method of bonding for a semiconductor chip A method of bonding and a bonding apparatus for a semiconductor chip that apply ultrasonic vibration to the semiconductor chip to bond the semiconductor chip to a substrate carry out leveling effectively at low cost and in a short time and can improve the bonding between the semiconductor chip and ... 03/01/07 - 20070048904 - Radiant energy heating for die attach Methods and systems for attaching a chip to a next level package by directing radiant energy at the chip back side while substantially preventing irradiation of the next level package are described. ... 03/01/07 - 20070048903 - Multi-chip package type semiconductor device A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on ... 03/01/07 - 20070048902 - Microfeature workpieces, carriers, and associated methods Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can include temporarily attaching the microfeature workpiece to a carrier with a releasable connector, wherein the connector is at least partially metallic. The method can further include performing a manufacturing process ... 03/01/07 - 20070048901 - Wafer-level package and ic module assembly method for the wafer-level package A wafer-level package and an IC module assembly method for a wafer-level package are provided in the present invention. The method comprises forming a metal bump on a wafer, applying a high polymer resin coating to the wafer, grinding a surface of the resin coating, printing an endpoint on the ... 02/22/07 - 20070042530 - Electronic package for image sensor, and the packaging method thereof A semiconductor device package and method for its fabrication are provided. The semiconductor device package generally includes at least one semiconductor die and a substrate coupled to the semiconductor die. The semiconductor die is provided with a front side defining a sealing area, and a first solder sealing ring pad ... 02/22/07 - 20070042529 - Methods and apparatus for high-density chip connectivity Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a ... 02/15/07 - 20070037320 - Multichip packages with exposed dice Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip ... 02/15/07 - 20070037319 - Semiconductor package with contact support layer and method to produce the package A semiconductor package comprises a substrate which includes a plurality of conducting traces and upper contact areas on its upper surface and a second plurality of lower conductive traces and external contact areas on its bottom surface and external conducting members attached to the external contact areas. The semiconductor package ... 02/01/07 - 20070026571 - Roll-to-roll fabricated encapsulated semiconductor circuit devices An encapsulated semiconductor device, comprising a first substrate having an electrically conductive surface; a second substrate having an electrically conductive pattern disposed thereon; and a pattern of semiconductor elements, each of the semiconductor elements having a first conductor and a second conductor. The encapsulated semiconductor device includes an adhesive having ... 02/01/07 - 20070026570 - Roll-to-roll fabricated electronically active device An electronically active sheet, comprising a first substrate having an electrically conductive surface; a second substrate having an electrically conductive pattern disposed thereon; at least one semiconductor element having a first conductor and a second conductor. The electronically active sheet includes an adhesive having at least one semiconductor element fixed ... 02/01/07 - 20070026569 - Semiconducting device with folded interposer Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the ... 02/01/07 - 20070026568 - Methods for bonding and devices according to such methods A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ... 01/18/07 - 20070015313 - Submount of semiconductor laser diode, method of manufacturing the same, and semiconductor laser diode assembly using the submount Provided is a submount flip-chip bonded to a semiconductor laser diode chip with stepped first and second electrodes. The submount includes a substrate having first and second surfaces which are separated by a step height corresponding to a height difference between the first and second electrodes; first and second metal ... 01/04/07 - 20070004086 - Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows ... 01/04/07 - 20070004085 - Underfill device and method An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. ... 12/21/06 - 20060286716 - Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package A method for producing a flip-chip mounting electronic component having plural terminals (3) dotted on a mounting face (1) and conductors formed on the terminals (3) realizes flip-chip mounting capable of shortening the distance between bumps (7). To realize this, a step of coating the mounting face (1) with a ... 12/14/06 - 20060281224 - Compliant passivated edge seal for low-k interconnect structures A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and ... 12/14/06 - 20060281223 - Packaging method and package using the same The invention achieves the above-identified object by providing a packaging, comprising steps of: (a) providing an integrated circuit unit having an active surface, a plurality of bumps disposed thereon; (b) providing a substrate having a first surface and a second surface, a plurality of pads disposed on the first surface, ... 12/07/06 - 20060275951 - Microelectronic assemblies having low profile connections A microelectronic assembly includes a first microelectronic element having a first face and contacts accessible at the first face, and a layer of a dielectric material having a bottom surface contacting the first microelectronic element, a top surface facing away from the first microelectronic element and holes extending between the ... 11/30/06 - 20060270111 - Integrated circuit package substrate having a thin film capacitor structure This invention relates to the manufacture of a substrate, such as a package substrate or an interposer substrate, of an integrated circuit package. A base structure is formed from a green material having a plurality of via openings therein. The green material is then sintered so that the green material ... 11/30/06 - 20060270110 - Method for connecting a semiconductor chip onto an interconnection support A method electrically connects a semiconductor chip, having contact pads, with an interconnection support, having a substrate and reception pads. The method comprises a step of growing a first metal layer on the contact pads of the chip and a step of growing a second metal layer on the reception ... 11/30/06 - 20060270109 - Manufacturing method for an electronic component assembly and corresponding electronic component assembly Manufacturing method for an electronic component assembly and corresponding electronic component assembly The present invention provides a manufacturing method for an electronic component assembly and to a corresponding electronic component assembly. The method comprises the steps of: providing a substrate having a first and a second side and having at ... 11/23/06 - 20060263937 - Interposer, method of fabricating the same, and semiconductor device using the same An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating ... 11/23/06 - 20060263936 - Surface roughening method for embedded semiconductor chip structure A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on ... 11/23/06 - 20060263935 - Method of bonding a microelectronic die to a substrate and arrangement to carry out method A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die ... 11/16/06 - 20060258049 - Method of bonding solder pads of flip-chip package Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having ... 10/26/06 - 20060240595 - Method and apparatus for flip-chip packaging providing testing capability A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second ... 10/19/06 - 20060234423 - System for providing a redistribution metal layer in an integrated circuit A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder ... 10/12/06 - 20060228829 - Method for fabricating a flip chip package A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed ... 10/05/06 - 20060223231 - Packing method for electronic components A packaging method which makes possible firm connection of electronic components having bump areas and a wiring board having a pad electrode portion with secure electrical conduction is to be provided. To achieve this object, according to the packaging method which makes possible firm connection of electronic components having bump ... 09/28/06 - 20060216860 - Flip chip interconnection having narrow interconnection sites on the substrate A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the ... 09/28/06 - 20060216859 - Package structure of semiconductor and wafer-level formation thereof In wafer-level formation of a package structure of semiconductor, multitudes of conductive connection structures are formed protruded from a transparent substrate. Multitudes of grooves are formed in a semiconductor wafer and an adhesive is filled therein. The wafer and the transparent substrate are jointed in which each of the conductive ... 09/21/06 - 20060211172 - System and method to increase die stand-off height In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, ... 09/21/06 - 20060211171 - Underfill on substrate process and ultra-fine pitch, low standoff chip-to-package interconnections produced thereby Disclosed are methods and substrates suitable for flip-chip assembly. Underfill processing used to produce the substrates provides for lead-free, eutectic solder, and other alloy reflow based flip-chip interconnects for 10-20 μm peripheral and area array I/O pitch. The methods and substrates utilize underfill materials with tailored properties along with a ... 08/31/06 - 20060194367 - Semiconductor device production method and semiconductor device A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask ... 08/24/06 - 20060189031 - Semiconductor device and manufacturing method thereof Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package ... 08/10/06 - 20060177966 - Package or pre-applied foamable underfill for lead-free process A B-stageable or pre-formed film underfill encapsulant composition that is used in the application of lead-free electronic components to substrates. The composition comprises an expandable microsphere, thermoplastic resin, thermoset resin, a latent catalyst, and a solvent. Various other additives, such as adhesion promoters, flow additives and rheology modifiers may also ... 08/10/06 - 20060177965 - Semiconductor device and process for producing the same Before a semiconductor chip having a plurality of bumps is mounted on a mount substrate (3) having a plurality of bumps (4) by flip chip bonding, a resist layer (5) having a thickness larger than that of the bumps (4) is formed on the mount substrate (3) with the bumps. ... 08/03/06 - 20060172460 - Semiconductor device and method of manufacture thereof, circuit board and electronic instrument A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern ... 07/27/06 - 20060166402 - Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the ... 07/20/06 - 20060160270 - Method for producing an anisotropic conductive film on a substrate This invention relates to a process for manufacturing an anisotropic conducting film comprising a layer of electrically insulating material and conducting through inserts, the said process comprising the following steps: a) formation on a substrate of at least one layer of material with through holes, the said layer being called ... 06/22/06 - 20060134834 - Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in ... 06/22/06 - 20060134833 - Packaged semiconductor die and manufacturing method thereof Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the ... 06/22/06 - 20060134832 - Manufacturing method of semiconductor device The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mother chip, and ... 06/22/06 - 20060134831 - Integrated circuit packaging using electrochemically fabricated structures Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, ... 06/22/06 - 20060134830 - Method and system for performing die attach using a flame Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are described and claimed. ... 06/22/06 - 20060134829 - Wafer scale integration of electroplate 3d structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural ... 06/15/06 - 20060128059 - Compact system module with built-in thermoelectric cooling An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The ... 05/25/06 - 20060110852 - Methods to achieve precision alignment for wafer scale packages Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed ... 05/25/06 - 20060110851 - Methods for forming co-planar wafer-scale chip packages Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed ... 05/18/06 - 20060105497 - Forming a stress compensation layer and structures formed thereby Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening. ... 05/11/06 - 20060099737 - Flip-chip semiconductor device utilizing an elongated tip bump A flip-chip type semiconductor device includes a semiconductor chip having electrode pads formed and arranged on a chip surface thereof. Sprout-shaped metal bumps are bonded to the electrode pads on the chip, and an adhesive resin layer is formed on the chip surface of the chip such that tip ends ... 05/11/06 - 20060099736 - Flip chip underfilling A method of underfilling an integrated circuit that is mounted to a first side of a package substrate having an opposing second side. A void is provided, which extends completely through the package substrate and is disposed under the integrated circuit. The package substrate is disposed with the second side ... 04/27/06 - 20060088955 - Chip package, chip packaging, chip carrier and process thereof A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of ... 04/27/06 - 20060088954 - Electronic component with cavity fillers made from thermoplast and method for production thereof An electronic component and a method for fabricating it is disclosed, where the component comprises a semiconductor chips which has flip-chip contacts. These contacts are fixed on a rewiring substrate, the interspace between the rewiring substrate and the semiconductor chip being filled with a thermoplastic. The glass transition temperature of ... 04/20/06 - 20060084201 - Parts for deposition reactors Processing methods and internal reactor parts avoid peeling and particle generation caused by differences in the coefficients of thermal expansion (CTE's) between reactor parts and films deposited on the reactor parts in hot wall CVD chambers. Conventional materials for reactor parts have relatively low CTE's, resulting in significant CTE differences ... 04/13/06 - 20060079022 - Frame attaching process A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the ... 04/13/06 - 20060079021 - Method for flip chip package and structure thereof A method for flip chip package and structure thereof is disclosed. The present invention is using an eutectic bonding process to connect a chip and a heatsink for enhancing thermal dissipation capability from the chip to the heatsink and ensuring the chip working well. The method for flip chip package ... 04/06/06 - 20060073634 - Mechanism and process for compressing chips A chip compressing mechanism is provided. The chip compressing mechanism essentially comprises a loading component, a head component and a gimbal. The head component is disposed under the loading component, with a gap in-between. The gimbal is disposed between the loading component and the head component to support the gap ... 03/30/06 - 20060068522 - Semiconductor device with improved heat dissipation, and a method of making semiconductor device A semiconductor device includes a semiconductor chip, a heat dissipation member for dissipating heat generated by the semiconductor chip, and a coupling member which thermally couples the semiconductor chip to the heat dissipation member, wherein the coupling member is made of metal and deformable to absorb a stress generated between ... 03/30/06 - 20060068521 - Method of fabricating microelectronic package using no-flow underfill technology and microelectronic package formed according to the method A method of fabricating a microelectronic package, a package fabricated according to the method, and a system including the package. The method comprises: providing a substrate and a die each having pre-solder bumps thereon; placing a patterned underfill film onto the substrate, the film having a filler therein, being substantially ... 03/23/06 - 20060063305 - Process of fabricating flip-chip packages A process of fabricating flip-chip packages is disclosed. First, a substrate having a carrying surface is provided. Next, a chip is provided, wherein the chip has an active surface, a plurality of bonding pads are disposed on the active surface and on each bonding pad a bump is disposed. Afterwards, ... 03/16/06 - 20060057775 - Method of forming a wafer backside interconnecting wire A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to ... 03/09/06 - 20060051895 - Method for manufacturing electronic component-mounted board A method for manufacturing an electronic component-mounted board (X) includes a temperature raising step for heating an electronic component (30A), with a solder bump electrode (31) containing a solder material, to a first temperature higher than the melting point of the solder material, while also heating a wiring board (X′), ... 03/09/06 - 20060051894 - Method for bonding flip chip on leadframe A method for bonding flip chip on leadframe is disclosed. A leadframe including a plurality of leads is provided. The leadframe is oxidized to form an oxidation layer from the upper surface of the leads. Each lead has a flip-chip bonding portion covered by the oxidation layer. A flip chip ... 02/23/06 - 20060040426 - Circuitized substrate, method of making same and information handling system using same A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, ... 02/23/06 - 20060040425 - Circuit element and method of manufacturing the same There is provided a circuit element using an organic semiconductor that maintains the characteristics of organic semiconductors in a stable manner for a long period, is highly durable against various kinds of stresses, impacts, etc. from outside and has excellent reliability. The circuit element comprises a circuit portion including an ... 02/09/06 - 20060030076 - Semiconductor device The semiconductor device of the present invention is capable of restricting alloying metals and improving electrical connection between a semiconductor chip and a mount board. The semiconductor device comprises: the semiconductor chip having terminal sections; and bumps for electrical connection, the bumps being formed at the terminal sections. Each of ... 02/09/06 - 20060030075 - Manufacturing method of semiconductor device In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can ... 02/09/06 - 20060030074 - Method for connecting substrate and composite element The invention relates to a process for joining substrates having electrical, semiconducting, mechanical and/or optical components, and to a composite element. The process is to be suitable for the substrates which are to be joined substantially irrespective of material and in particular also for sensitive substrates, is to have a ... 01/19/06 - 20060014318 - Electronic component having at least one semiconductor chip on a circuit carrier and method for producing the same An electronic component includes at least one semiconductor chip, which has an active chip top side with contact areas and has a chip rear side arranged on a carrier top side of a circuit carrier. The circuit carrier and the chip top side are covered by a common rewiring layer ... 01/19/06 - 20060014317 - Integrated circuit package having reduced interconnects A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating ... 01/19/06 - 20060014316 - Method of making a semiconductor chip assemby with a metal containment wall and a solder terminal A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip ... 12/29/05 - 20050287706 - Electronic device package An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to which the die will be fixed. The die is placed on the discrete die attach. The die attach, in an embodiment, is an epoxy resin ... 12/29/05 - 20050287705 - Flip chip on leadframe package and method for manufacturing the same A flip chip on leadframe package includes a leadframe, a non-flow underfilling material and a flip chip. The leadframe has a plurality of inner leads. Each inner lead has an upper surface and a lower surface. A coating region is defined on the upper surfaces. The non-flow underfilling material is ... 12/22/05 - 20050282313 - Methods for modifying semiconductor devices to stabilize the same and semiconductor device assembly One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. The one or more stabilizers may be formed on or secured to the surface. Upon assembly of the semiconductor device component face down upon a higher-level substrate ... 12/22/05 - 20050282312 - Semiconductor device and manufacturing method thereof A semiconductor device is provided which includes a first semiconductor chip, a substrate onto which the first semiconductor chip is flip-chip bonded and on which a concave is formed along one side of the first semiconductor chip which is flip-chip bonded, a second semiconductor chip which is flip-chip bonded onto ... 12/22/05 - 20050282311 - Flip-chip substrate and flip-chip bonding process thereof A flip-chip substrate for bonding with a chip is provided. The chip has an active surface with a plurality of bonding pads and each bonding pad has a bump thereon. The flip-chip substrate has a plurality of contact pads that correspond in positions with the bonding pads on the chip ... 12/15/05 - 20050277227 - Chip scale package with open substrate A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the ... 12/15/05 - 20050277226 - High density flip chip interconnections A printed circuit board has, on one surface thereof, a plurality of metallic pads forming or leading to wire traces. The printed circuit board surface is solder mask free and a substantially runless soldering alloy is used to connect I/O solder bumps on a flip chip to the metallic pads. ... 12/01/05 - 20050266613 - Integrated circuit packages with reduced stress on die and associated methods Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed ... 12/01/05 - 20050266612 - Top layers of metal for high performance ic's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within ... 12/01/05 - 20050266611 - Flip chip packaging method and flip chip assembly thereof The present invention discloses a semi-etching method, which comprises the steps of etching a flip chip bump when producing a lead frame for packaging; electroplating a metal such as gold, silver, or solder onto the flip chip bump by an electroplating process; electrically connecting the bond pad of a chip ... 11/24/05 - 20050260794 - Method for fabrication of wafer level package incorporating dual compliant layers A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and ... 11/10/05 - 20050250249 - Method of making an electronic package An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at ... 11/10/05 - 20050250248 - Reworkable b-stageable adhesive and use in waferlevel underfill A reworkable thermoset epoxy-containing material that allows for a reworkable assembly such as a reworkable waferlevel underfilled miocroelectronic package. A method for using the reworkable thermoset material in the formation of a microelectronic package using this material. ... 10/13/05 - 20050227413 - Method for depositing a solder material on a substrate The present invention is related to a method for providing solder material on a predetermined area on a substrate. In various embodiments, the solder material is deposited on a wetting layer which lies within an area on a substrate having a confinement layer. Further a packaging method and package are ... 09/29/05 - 20050214977 - Microelectronic packaging and methods for thermally protecting package interconnects and components Apparatus and methods are provided wherein the reflowable electrically conductive interconnect material coupling the interconnects and/or land-side components of a microelectronic package is protected from elevated temperatures, such as those associated with reflow processes and environments which exceed the melting temperature of the interconnect material. One embodiment of the method ... 09/22/05 - 20050208705 - Semiconductor device package and method of production and semiconductor device of same A semiconductor device including a semiconductor device package providing a capacitor in its circuit board and a semiconductor chip mounted on that package, wherein the capacitor is provided directly under a semiconductor chip mounting surface of the circuit board on which the semiconductor chip is to be mounted and the ... 09/22/05 - 20050208704 - Methods including fabrication of substrates and other semiconductor device components with collars on or around the contact pads thereof Methods for fabricating carrier substrates and other semiconductor device components include disposing a collar around at least a portion of a contact. The collar may be formed by a programmed material consolidation process. The programmed material consolidation process may be effected in conjunction with a feature recognition technique, such as ... 09/22/05 - 20050208703 - Method of producing an electronic component with flexible bonding pads A method for producing an electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least ... 09/15/05 - 20050202593 - Flip chip packaging process and structure thereof A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need ... 09/08/05 - 20050196898 - Process of plating through hole A process of plating through hole is provided. First, a through hole is formed on a substrate. The through hole is connected to a first surface and a second surface of the substrate. Next, a photoresist layer is formed on the inner wall of the through hole, the first surface ... 08/18/05 - 20050181539 - Semiconductor device and method of manufacturing same A semiconductor device having a first semiconductor element placed over a second semiconductor element, so that an edge of the first semiconductor element is not placed over a predetermined circuit in the second semiconductor element, and wherein a size of the first semiconductor element is smaller than a size of ... 08/18/05 - 20050181538 - Semiconductor device for wire-bonding and flip-chip bonding package and manufacturing method thereof A manufacturing method of a semiconductor device for a wire-bonding and flip-chip bonding package mainly comprises the following steps. First, a chip having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, an under bump metallurgy layer having an aluminum layer, a nickel-vanadium ... 07/28/05 - 20050164428 - Flip chip packaging process employing improved probe tip design The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The ... 07/21/05 - 20050158911 - Process for producing circuit board having built-in electronic part The present invention provides a process for producing a circuit board having built-in electronic parts, which comprises the steps of: disposing two wiring circuit boards each having an electronic part mounted thereon so that the electronic-part-mounting sides of the respective circuit boards face each other; disposing a resin layer between ... 06/30/05 - 20050142693 - Semiconductor device with intermediate connector A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes ... 06/16/05 - 20050130350 - Flip clip attach and copper clip attach on mosfet device A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped ... 06/16/05 - 20050130349 - Electronic parts built-in substrate and method of manufacturing the same An electronic parts built-in substrate of the present invention includes a wiring substrate having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts having a larger area than an area of the first electronic parts a bump of ... ### FreshPatents.com Support |