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Semiconductor Device Manufacturing: Process > Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged SemiconductorPackaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.04/19/07 - 20070087478 - Semiconductor chip package and method for manufacturing the same A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate ... 04/19/07 - 20070087477 - Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same R×N2×L≦4×103 ... 04/19/07 - 20070087476 - Apparatus for improved power distribution in wirebond semiconductor packages A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting ... 04/19/07 - 20070087475 - Method and apparatus for peeling surface protective film A method and an apparatus for peeling a surface protective film attached on the surface of a semiconductor wafer are provided. A heating block is set in proximity to the whole surface of the semiconductor wafer, and the whole surface protective film is heated by the heating block. Thus, the ... 04/19/07 - 20070087474 - Assembly process for out-of-plane mems and three-axis sensors A method of assembling a three dimensional micromachined structure comprising the steps of defining a cavity in a holder wafer having a thick upper layer, providing a plurality of fingers in the thick upper layer extending from the holder wafer into the cavity, and disposing an out-of-plane wafer into the ... 04/19/07 - 20070087473 - Method for manufacturing semiconductor package substrate A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the ... 04/19/07 - 20070087472 - Methods for magnetically directed self assembly A fluidic assembly method includes dispersing a number of functional blocks in a fluid to form a slurry. Each of the functional blocks includes at least one element and a patterned magnetic film comprising at least one region. The fluidic assembly method further includes immersing at least a portion of ... 04/19/07 - 20070087471 - Semiconductor package and method of manufacturing the same A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the ... 04/12/07 - 20070082428 - Semiconductor device protective structure and method for fabricating the same The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The ... 04/05/07 - 20070077684 - Resistance welded solder crimp for joining stranded wire to a copper lead-frame A method of connecting stranded wire to a lead-frame body 10 includes the provision of a stranded wire 12. It is ensured that insulation is stripped from an end 14 of the stranded wire. An electrically conductive lead-frame connection structure 16 is associated with the lead-frame body. The end 14 ... 03/29/07 - 20070072340 - Electronic device with inductor and integrated componentry Semiconductor devices and methods for their assembly are described in which inductor elements and additional passive or active circuit components may be combined in novel configurations. An electronic device and associated methods provide an inductor element encapsulated within a dielectric package, the inductor package having a plurality of electrical contacts ... 03/29/07 - 20070072339 - Process for fabricating chip package structure A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier ... 03/29/07 - 20070072338 - Method for separating package of wlp The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy ... 03/22/07 - 20070065981 - Semiconductor system-in-package A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, ... 03/22/07 - 20070065980 - Method of manufacturing semiconductor chip A insulation film removing tape 38 is pasted on a metal film 34 so as to cover an opening portion 32, then an insulation film 17 is formed so as to cover the side wall of a through hole 21 from the second major surface 11B side of the semiconductor ... 03/22/07 - 20070065979 - Methods and systems for pack-size-oriented rounding Methods and systems are provided for packing a required quantity of products, wherein a plurality of different packages for packing the products and a plurality of packaging specifications comprising rounding rules are provided. In one implementation, a method is provided comprising determining a packaging specification out of a plurality of ... 03/22/07 - 20070065978 - Method for manufacturing micro-machined switch using pull-up type contact pad The present invention relates to the manufacture of a semiconductor switch for use in a variety of communication systems, and particularly to the manufacture of a RF micro-machined switch of pull-up type, wherein an electrostatic electrode is used so as to cause the contact pad involved in the operation of ... 03/15/07 - 20070059860 - Method for manufacturing semiconductor package A die for encapsulating an IC structural body having bonding wires with a molt resin is provided with at least one first half having an ejector-pin-through-hole and at least one second half coupled together to form a cavity therebetween. An ejector pin having a mirror-finished surface at a tip end ... 03/08/07 - 20070054438 - Carrier-free semiconductor package with stand-off member and fabrication method thereof A carrier-free semiconductor package with a stand-off member and a fabrication method thereof are proposed. A carrier with a recessed portion and a plurality of electrical contacts on a surface of the carrier is provided. At least one chip is mounted to the recessed portion of the carrier and is ... 03/01/07 - 20070048900 - Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling microelectronic devices Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by ... 03/01/07 - 20070048899 - Wafer level package and method for making the same The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plurality of second caves ... 03/01/07 - 20070048898 - Wafer level hermetic bond using metal alloy with raised feature Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the ... 03/01/07 - 20070048897 - Method and apparatus for depositing conductive paste in circuitized substrate openings A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the ... 03/01/07 - 20070048896 - Conductive through via structure and process for electronic device carriers Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon ... 02/22/07 - 20070042528 - Defining electrode regions of electroluminescent panel An electroluminescent panel includes a partial electroluminescent panel base, a layer of electrically isolated conductive areas next to the partial electroluminescent panel base, and an activatable conductive layer next to the layer of electrically isolated conductive areas. The activatable conductive layer is selectively activated to electrically connect selected electrically isolated ... 02/22/07 - 20070042527 - Microelectronic package optionally having differing cover and device thermal expansivities A microelectronic package is provided that includes a microelectronic device and a cover. The device and the cover are typically substantially immobilized relative to each other. The cover typically has a higher coefficient of thermal expansion while the device has a higher effective stiffness. The package may be formed in ... 02/15/07 - 20070037318 - Method and apparatus for flip-chip bonding Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and ... 02/15/07 - 20070037317 - Method and device for attaching a chip in a housing A method and the associated device for attaching at least one micromechanical chip in a housing which is optically transparent to radiation of at least one predefined transmission wavelength, in which an adhesive layer is applied between the chip and the housing and the adhesive layer is irradiated through the ... 02/01/07 - 20070026567 - Semiconductor module comprising components for microwave engineering in plastic casing and method for the production thereof A semiconductor module (1) has components (6) for microwave engineering in a plastic casing (7). The semiconductor module (1) has a principal surface (8) with an upper side (9) of a plastic package molding compound (10) and at least one active upper side (11) of a semiconductor chip (12). Disposed ... 01/25/07 - 20070020807 - Protective structures and methods of fabricating protective structures over wafers A method of fabricating a protective structure and a packaged structure are described. ... 01/25/07 - 20070020806 - Method and structure for forming strained si for cmos devices A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only ... 01/25/07 - 20070020805 - Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the ... 01/25/07 - 20070020804 - Method of manufacturing electronic circuit device The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting ... 01/25/07 - 20070020803 - Semiconductor device and manufacturing method of the same An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at ... 01/25/07 - 20070020802 - Packaging method for segregating die paddles of a leadfram The present invention relates to a packaging method for segregating die paddles of a leadframe. The method comprising: (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the ... 01/25/07 - 20070020801 - Ic chip mounting method The present invention provides an IC chip mounting method for mounting two or more IC chips on a base, including: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by ... 01/25/07 - 20070020800 - Ic chip mounting method An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into ... 01/18/07 - 20070015312 - Method for forming bump protective collars on a bumped wafer A method of forming bump protective collars is disclosed. A wafer has an active surface with a plurality of bonding pads and a passivation layer. A plurality of reflowed bumps are formed over the bonding pads. A photoresist is coated on the active surface. Using the reflowed bumps as a ... 01/18/07 - 20070015311 - Structure of mounting electronic component and method of mounting the same The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the ... 01/18/07 - 20070015310 - Polyceramic-coated tool for applying a flowable composition A tool is provided for applying a flowable composition onto a receiving surface. The tool includes a polyceramic coating on a surface thereof and may take the form of a stencil or mold. Also provided are an apparatus and a method that uses the tool. In use, the tool is ... 01/18/07 - 20070015309 - Electronic part manufacturing method Provided is a method of manufacturing an electronic part in which a circuit element (3) is formed on a surface of a ceramic substrate (1) and conductive balls (2) are used as terminals of the electronic part. After the ceramic substrate (1) and the conductive balls (2) are fixed, the ... 01/04/07 - 20070004084 - Chip and multi-chip semiconductor device using thereof and method for manufacturing same The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process ... 01/04/07 - 20070004083 - Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression support In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal ... 01/04/07 - 20070004082 - Method for manufacturing semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate; ... 01/04/07 - 20070004081 - Method for manufacturing a thermal interface material An exemplary method for manufacturing a thermal interface material includes the steps of: providing a first substrate having a first surface and an opposite second substrate having an opposite second surface spaced apart a predetermined distance; forming a number of carbon nanotubes from one of the first the second surfaces; ... 01/04/07 - 20070004080 - Hermetic seals for micro-electromechanical system devices The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on ... 01/04/07 - 20070004079 - Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of fbar chips A device package includes a device substrate and a cap mounted on the device substrate. The device substrate includes a contact pad. The cap defines a via with a slightly sloped sidewall through the cap, a contactor extending from an interior surface of the cap, a contactor pad over the ... 12/28/06 - 20060292743 - Stacked die in die bga package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. ... 12/28/06 - 20060292742 - Manufacturing method for packaged semiconductor device A semiconductor device in which moisture penetration into the package interior is suppressed, comprising a rewiring layer formed by plating, with improved reliability of electrical characteristics. On the main surface of a semiconductor chip comprising circuit elements and formed on a wafer, a passivation film opposing the circuit elements is ... 12/28/06 - 20060292741 - Heat-dissipating semiconductor package and fabrication method thereof A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined ... 12/28/06 - 20060292740 - High temperature packaging for electronic components, modules and assemblies A high temperature semiconductor packaging, a method for making the same packaging are providing. The packaging comprises a mounting platform, a semiconductor die positioned above the platform and a layer of high temperature passivation coating. ... 12/28/06 - 20060292739 - Method and apparatus to boost high-speed i/o signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers ... 12/28/06 - 20060292738 - Flex on suspension with a heat-conducting protective layer for reflowing solder interconnects A FOS is provided for electrically connecting a data transfer head with a PCCA. The FOS comprises a polymeric layer supporting an electrical trace. The electrical trace comprises an uninsulated pad surface configured for electrically engaging a solder interconnect of the PCCA. The polymeric layer comprises a continuous portion covering ... 12/28/06 - 20060292737 - Grid array connection device and method A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid ... 12/21/06 - 20060286714 - Semiconductor device and system having semiconductor device mounted thereon There is provided a semiconductor device that is capable of reducing wring density of the wiring pattern on a mounting board on which it is mounted, thereby facilitating routing of the wiring pattern. Pads are formed which are connected to pads on a bare chip by bonding wires. There are ... 12/21/06 - 20060286713 - Methods of fabricating semiconductor devices including trench device isolation layers having protective insulating layers and related devices A method of fabricating a semiconductor device includes forming an active region including opposing sidewalls and a surface therebetween protruding from a substrate. A protective insulating layer is formed on the sidewalls of the active region, and extends away from the substrate to beyond the surface of the active region. ... 12/21/06 - 20060286712 - Thermal interface with a patterned structure An interface is formed by pressing a patterned first surface and a second surface together, with a particle-loaded interface material in between. The first surface is fabricated with a pattern of channels designed to redistribute the velocity gradients that occur in the interface material during interface formation in order to ... 12/21/06 - 20060286711 - Signal isolation in a package substrate Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected ... 12/21/06 - 20060286710 - Method for bonding substrates, bonded substrate, and direct bonded substrare The present invention relates to a method for laminating substrates, including the steps of locating a surface of a first substrate and a surface of a second substrate at positions close to each other or partially bringing them in contact with each other; supplying a volatile liquid between the surface ... 12/14/06 - 20060281220 - Semiconductor device packaging substrate and semiconductor device packaging structure A packaging substrate for a semiconductor device includes: a solder resist on a surface of the packaging substrate, the solder resist having a first opening portion for mounting the semiconductor device; and a speed adjusting opening portion for adjusting a flow speed of an underfill resin when the underfill resin ... 12/14/06 - 20060281219 - Chip-based thermo-stack A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at ... 12/07/06 - 20060275949 - Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, aNd conductors on a backside of the substrate. A method for fabricating the ... 11/30/06 - 20060270108 - Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of the contact, ... 11/30/06 - 20060270107 - Method of making semiconductor bga package having a segmented voltage plane A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of ... 11/30/06 - 20060270106 - System and method for polymer encapsulated solder lid attach System and method for a polymer encapsulated solder lid attach. A preferred embodiment comprises one or more metallic islands distributed throughout the combination attach, wherein each metallic island overlays one or more heat producing portions of the integrated circuit die, and a polymer encapsulant to encircle each metallic island and ... 11/30/06 - 20060270105 - Method of assembling semiconductor devices with leds Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED ... 11/30/06 - 20060270104 - Method for attaching dice to a package and arrangement of dice in a package The invention relates to a method and arrangement for assembling and packaging single and multiple semiconductor dice with an intermediate arranged interposer. The interposer is arranged onto the backside of a die within the wafer composite and thereby during the wafer level process. Preferably the interposer is printed by a ... 11/23/06 - 20060263932 - Semiconductor device manufacturing method and apparatus used in the semiconductor device manufacturing method A semiconductor device manufacturing method includes forming circuit devices and a plurality of electrode pads within a semiconductor chip formation region. The method also includes forming, on the main surface of the semiconductor wafer, an insulating film which exposes a portion of each of the electrode pads. The method also ... 11/23/06 - 20060263931 - Wafer level packaging of materials with different coefficents of thermal expansion An electromechanical device package includes a cap material permanently bonded to a device wafer encapsulating an electromechanical device. An intermediate material is used to bond the device and capping material together at a low temperature, and a structure including the intermediate material emanating from either the device or cap material, ... 11/23/06 - 20060263930 - Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method A method of manufacture of an electronic substrate, having a process of embedding electronic components in a substrate, and a process of ejecting liquid droplets containing a conductive material, to form a wiring pattern connected to the external connection electrodes of the electronic components embedded in the substrate. ... 11/23/06 - 20060263929 - Method and apparatus for attaching an ic package to a pcb assembly A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a plurality of contact pads on a PCB. At least one of a plurality of solder balls of an IC device are ... 11/23/06 - 20060263928 - Assembly of a semiconductor die attached to substrate with oxazoline derivative bearing an electron donor or acceptor functionality An assembly of a semiconductor die attached to a substrate is made with a composition comprising compounds that contain an oxazoline functionality and an electron acceptor or an electron donor functionality. Electron donor functionalities include styrenic, cinnamyl, and vinyl ether groups. Electron acceptor functionalities include maleimide, acrylate, fumarate, and maleate ... 11/16/06 - 20060258046 - Method of producing a universal semiconductor housing with precrosslinked plastic embedding compounds An electronic component and a blank have plastic embedding compounds of a first and a second plastic layer. Semiconductor chips are embedded in the first plastic layer in such a way that their marginal sides are surrounded by a bead. The second plastic layer compensates for the unevenness of a ... 11/16/06 - 20060258045 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to ... 11/16/06 - 20060258044 - Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to ... 11/09/06 - 20060252180 - Method for a low profile multi-ic chip package connector A method for a low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In ... 11/09/06 - 20060252179 - Integrated circuit packaging structure and method of making the same The invention provides an integrated circuit packaging and method of making the same. The integrated circuit packaging includes a substrate, a semiconductor die, a heat-dissipating module, and a protection layer. The substrate has an inner circuit formed on a first surface, and an outer circuit formed on a second surface ... 11/09/06 - 20060252178 - Method of fabricating wafer level package A method of fabricating wafer level package is provided. The method includes the following steps. Firstly, a wafer having a front surface and a rear surface is provided, and the front surface has several conductive pads. Next, a supporting material is attached on the front surface. Then, several holes are ... 11/09/06 - 20060252177 - Semiconductor package with selective underfill and fabrication method therfor A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder ... 11/02/06 - 20060246623 - Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one ... 11/02/06 - 20060246622 - Stacked die package for peripheral and center device pad layout device An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device is disclosed. An outer peripheral portion of the second semiconductor device overhangs both the ... 11/02/06 - 20060246621 - Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same A microelectronic die and a microelectronic package including the die. The package includes: a substrate; and a microelectronic die bonded to the substrate. The die comprises: a die substrate; a thermally conductive structure extending through the substrate, the thermally conductive structure being configured to conduct heat through a thickness of ... 10/26/06 - 20060240593 - Solid electrolytic capacitor and method for manufacturing the same In the present invention, a capacitor element including a valve action metal, an oxide film layer formed on the surface of the valve action metal, and a solid electrolytic layer formed on the oxide film layer is provided with an organic compound having a boiling point of not lower than ... 10/26/06 - 20060240592 - Integrated circuit package and method for producing it An integrated circuit includes a first integrated circuit flip chip (105, 205, 305) is bonded to first electric contacts (102, 202, 302) which are an inner part (104, 204, 304) of a planar array (103, 203, 303) of electric contacts. Second electric contacts (106, 206, 306) on the flip chip ... 10/19/06 - 20060234422 - Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors ... 10/19/06 - 20060234421 - Method of forming a substrateless semiconductor package A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate ... 10/19/06 - 20060234420 - Electronic device In an electronic device having an interposer substrate as an MCM structure, heat dissipation properties are enhanced while the reliability of joint between the interposer substrate and a mother board is maintained. In the invention, a metal core base material of great heat capacity and high thermal conductivity is used ... 10/05/06 - 20060223230 - Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on ... 10/05/06 - 20060223229 - Ball grid array package and process for manufacturing same A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a first surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a ... 10/05/06 - 20060223228 - Ceramic substrate and method of breaking same A ceramic substrate (100) includes a top surface, a plurality of identification marks (104), a protective compound (110), a bottom surface, and a plurality of grooves (106). The top surface includes a first area and a second area. The first area is defined at one or more edges portions of ... 10/05/06 - 20060223227 - Molding method for foldover package A method of making a microelectronic assembly including the steps of depositing one or more microelectronic elements onto a flexible substrate and folding the substrate so that a first region of the substrate forms a first run and a second region of the substrate forms a second run overlaying the ... 10/05/06 - 20060223226 - Organic substrates with integral thin-film capacitors, methods of making same, and systems containing same An organic substrate, thin-film capacitor composite includes two plates that are accessed through deep and shallow vias. The organic substrate, thin-film capacitor composite includes integral structure with at least one trace in the organic substrate. The composite is able to be coupled with an interposer. The composite is also part ... 10/05/06 - 20060223225 - Method, system, and apparatus for transfer of integrated circuit dies using an attractive force A method, system, and apparatus for transferring integrated circuit dies is described. A die receptacle structure has a first surface. The first surface has a plurality of cells formed therein. Each cell is configured to contain an integrated circuit die. A bottom surface of each cell is configured to attract ... 10/05/06 - 20060223224 - Substrate for reticle and method of manufacturing the substrate, and mask blank and method of manufacturing the mask blank In a reticle substrate is used for forming a reticle held on a stepper and has main surfaces opposing each other, side faces, and chamfered surfaces formed between main surfaces and side faces, a flatness-measuring area is defined as an area excluding a peripheral area of a width of 3 ... 09/28/06 - 20060216858 - Vertically stacked semiconductor device A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer ... 09/28/06 - 20060216857 - Chip-scale package for integrated circuits A chip-scale packaged IC is made by bonding one or more singulated die chips (from an IC wafer) to a common substrate, such as a single cap wafer (or a portion thereof) and cutting (singulating) the substrate to yield individual, chip-scale packaged ICs. Alternatively, each die chip is bonded to ... 09/28/06 - 20060216856 - Wafer-level package for integrated circuits A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die ... 09/28/06 - 20060216855 - Schottky diode device with aluminium pickup of backside cathode An integrated circuit package includes a semiconductor chip having a passivation layer forming the top surface of the semiconductor chip and a metal pad formed on the passivation layer and a discrete electronic device having a first terminal formed on a first surface and a second terminal formed on a ... 09/28/06 - 20060216854 - Circuit board and process for producing the same A method for manufacturing a circuit board (7); in which, an electronic component is injected into a resin substrate at a low temperature, and then the resin substrate is improved in its heat withstanding property. The manufacturing method comprises the steps of softening by heat a resin substrate which contains ... 09/21/06 - 20060211170 - Semiconductor device and manufacturing method of the same A semiconductor device includes an N-type semiconductor region formed in a semiconductor substrate; a p-type semiconductor region formed in a region deeper in the semiconductor substrate than the N-type semiconductor region; and a heavy metal capturing region formed in a portion of the p-type semiconductor region to capture heavy metal ... 09/21/06 - 20060211169 - Vacuum packaged single crystal silicon device A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of ... 09/21/06 - 20060211168 - Semiconductor integrated circuit arrangement device and method An arrangement device including: a photography section, which photographs a first mark and a second mark in a state in which a semiconductor integrated circuit to which the first mark is applied and a member to which the second mark is applied, which member is to be used in combination ... 09/21/06 - 20060211167 - Methods of producing a package for semiconductor chips Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple ... 09/21/06 - 20060211166 - Methods of producing a package for semiconductor chips The inventive method is based on the a idea of releasing a mechanical connection between the semiconductor chip and the supporting substrate during the manufacturing of the packing. The mechanical connection required for producing the electrical contacts between the semiconductor chip and the supporting substrate ensues only temporarily. As a ... 09/14/06 - 20060205112 - Semiconductor package fabrication A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module. ... 09/14/06 - 20060205111 - Method for producing chip stacks and chip stacks formed by integrated devices The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a ... 09/07/06 - 20060199304 - Pcb contact arrangement A printed circuit board for mounting electrical components such as LEDs has outward edge protrusions on which an electrically conductive material is deposited such that the board itself can be used to make electrical contact in a pre-existing, commercially available fitting, such as a screw-in or base fitting designed to ... 09/07/06 - 20060199303 - Carrier for substrate film The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments ... 09/07/06 - 20060199302 - Semiconductor device and a manufacturing method of the same A semiconductor device is manufactured by adhering a fixing tape to plural leads of a lead frame comprising a copper alloy, mounting a semiconductor chip on a tab of the lead frame, electrically connecting the leads to electrodes a of the semiconductor chip via bonding wires, forming a sealing resin ... 09/07/06 - 20060199301 - Methods of making a curable composition having low coefficient of thermal expansion and an integrated circuit and a curable composition and integrated circuit made there from Disclosed is a method for making a low CTE curable composition. In one embodiment, the method comprises mixing together (i) from 0.1 to 60.0% by weight of a nanoparticle composition and (ii) from 20.0 to 90.0% by weight of a curable binder to provide a premixture, based on the total ... 09/07/06 - 20060199300 - Ic chip solder bump structure and method of manufacturing same Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical ... 09/07/06 - 20060199299 - Method for reducing assembly-induced stress in a semiconductor die A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, ... 09/07/06 - 20060199298 - Creation of hermetically sealed dielectrically isolating trenches The invention relates to a method and an assembly for forming structures that are dielectrically insulated from each other by means of filled hermetically sealed isolation trenches for the formation of mechanical-electrical sensor structures, which require for their functioning a hermetically sealed cavity, in which are located the moveable sensor ... 08/31/06 - 20060194366 - Multi-chip ball grid array package A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an ... 08/31/06 - 20060194365 - Microelectronic assemblies having compliancy A microelectronic assembly includes a microelectronic element, such as a semiconductor wafer or semiconductor chip, having a first surface and contacts accessible at the first surface, and a compliant layer overlying the first surface of the microelectronic element, the compliant layer having openings in substantial alignment with the contacts of ... 08/31/06 - 20060194364 - Micro-component packaging process and set of micro-components resulting from this process A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the ... 08/24/06 - 20060189030 - Heat shrinkable insulated packaging A method for preparing an insulating packaging material for a container is disclosed. A first layer of insulating material can be placed around a container, a second layer of heat-shrinkable material can be placed around the first layer and heat can be applied to heat-shrink the layer and conform the ... 08/24/06 - 20060189029 - Method for efficient annealing of plated semiconductor package leads A method for completing an assembled semiconductor device, which has metallic leads for connection to external parts. The method comprises the step (202) of encapsulating the assembled device with a polymeric precursor so that at least portions of the leads remain un-encapsulated. Without significant delay, these un-encapsulated lead portions are ... 08/24/06 - 20060189028 - Wafer having alternating design structure and method for manufacturing semiconductor package using the same The present invention relates to a wafer having an alternating design structure and a method for manufacturing a semiconductor package using the wafer. The present invention is conceived to solve all the aforementioned problems associated with the related art wafer having the lattice design arrangement and method for manufacturing a ... 08/17/06 - 20060183270 - Tools and methods for forming conductive bumps on microelectronic elements A method of making a microelectronic assembly includes providing a microelectronic element having a front face and contact pads accessible at the front face, providing a dispensing tool containing a molten metal and having a discharge port for dispensing the molten metal, and aligning the discharge port of the dispensing ... 08/17/06 - 20060183269 - Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a semiconductor wafer having semiconductor chips which are arranged in rows and columns and have active top surfaces and back surfaces, the active top surfaces being provided with ... 08/10/06 - 20060177964 - Semiconductor module and method for producing a semiconductor module The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15′, 15″); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a ... 08/10/06 - 20060177963 - Process for producing copy protection for an electronic circuit It has proven particularly advantageous for the copy-protect layer (4) to be produced by applying a silicate glass by evaporation coating, since this means that an etching process which dissolves the copy-protect layer also attacks the substrate (1), in such a manner that the semiconductor structures (2) are at least ... 08/03/06 - 20060172457 - Chip-stacked semiconductor package and method for fabricating the same A chip-stacked semiconductor package and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers, and a heat sink module plate including a plurality of heat sinks are provided, wherein a plurality of through holes are formed around each of the ... 08/03/06 - 20060172456 - Device packages having stable wirebonds A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in ... 07/27/06 - 20060166401 - Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication therefor A hybrid electronic circuit package (102, FIG. 1) includes non-insertable conductive features (110) and insertable conductive features (112) at a surface of the package. A hybrid receptacle (120), such as a socket, for example, includes non-insertable contacts (124) and insertable contacts (126), which are positioned in a complementary manner with ... 07/27/06 - 20060166400 - Electronic assembly with integrated io and power contacts In some example embodiments, an integrated circuit, electronic assembly and method provide a current path for supplying power to a processor. As an example, the integrated circuit includes a base having power contacts that extend from an upper surface of base. The integrated circuit further includes a substrate that is ... 07/27/06 - 20060166399 - Integrated circuit die connection methods and apparatus This invention generally relates to methods and apparatus for connecting to an integrated circuit die, in particular where the die includes both analogue/microwave radio frequency (rf) circuitry and digital circuitry. A method of connecting a die having both microwave radio frequency (rf) circuitry and digital circuitry to a substrate of ... 07/27/06 - 20060166398 - Off-grid decoupling of ball grid array (bga) devices and method A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, ... 07/27/06 - 20060166397 - Thermal enhanced package for block mold assembly A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a ... 07/20/06 - 20060160269 - Method and apparatus for avoiding dicing chip-outs in integrated circuit die A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the ... 07/20/06 - 20060160268 - Exposure equipment and control method of the same A controller controls a wafer carrier to move from a SMIF-POD to transfer and collect a wafer between a space of a transfer unit through a thermal chamber. The wafer carrier is returned into the SMIF-POD, when the wafer is exposed, to be kept waiting in the SMIF-POD until the ... 07/20/06 - 20060160267 - Under bump metallurgy in integrated circuits An integrated circuit package and method of manufacture is provided. A substrate having a number of contact pads exposed through a passivation layer thereon has a first under bump metallurgy layer over at least one of the contact pads. A top under bump metallurgy layer of copper having a thickness ... 07/13/06 - 20060154402 - Tile-based routing method of a multi-layer circuit board and related structure A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned ... 07/06/06 - 20060148129 - Silicon direct bonding method A silicon direct bonding method including preparing two silicon substrates having corresponding bonding surfaces, forming a trench in at least one bonding surface of the two silicon substrates, and thermally bonding the two silicon substrates to one another. The trench may be along a dicing line. The trench may communicate ... 07/06/06 - 20060148128 - Signal transfer film, display apparatus having the same and method of manufacturing the same A signal transfer film includes a base film, a lead line formed on the base film and a passivation layer protecting the lead line. The passivation layer includes a nonlinear edge portion formed at a boundary region between the lead line and the passivation layer. The nonlinear edge portion of ... 07/06/06 - 20060148127 - Method of manufacturing a cavity package A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of ... 07/06/06 - 20060148126 - Method for manufacturing printed wiring board There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring ... 06/29/06 - 20060141668 - Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages ... 06/29/06 - 20060141667 - Bare die socket A socket for removably mounting a bare die to a substrate, such as a printed circuit board. This socket is formed by insert molding signal conductors in an insulative housing. A ground structure is separately provided to control the impedance of the signal conductors and to reduce cross talk. The ... 06/29/06 - 20060141666 - Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby The present invention relates to a method for producing a module including an integrated circuit die on a substrate. A substrate is provided, a metallization structure is provided which includes a conductive path and a metallization contact pad on the substrate. The integrated circuit die is placed onto the substrate, ... 06/22/06 - 20060134827 - Microlenses including a plurality of mutually adhered layers of optically transmissive material and systems including the same Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor, a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one ... 06/22/06 - 20060134826 - Methods of forming semiconductor packages The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods ... 06/22/06 - 20060134825 - Injection-molded package for mems inertial sensor Methods of packaging devices such as MEMS devices are disclosed. An illustrative method of packaging a device in accordance with an illustrative embodiment of the present invention can include the steps of providing a substrate having an device provided therein or thereon, attaching a cap to the substrate and sealing ... 06/15/06 - 20060128058 - Wafer bonding of micro-electro mechanical systems to active circuitry A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active ... 06/15/06 - 20060128057 - Xerographic micro-assembler Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of ... 06/08/06 - 20060121644 - Method for die attaching A method for die attaching is disclosed. At first, at least one die and a die-attach preform are separately provided. The die-attach preform is picked and placed upon a die carrier. Then, the die is picked and placed upon the die-attach preform. The die and the die carrier are heated ... 06/01/06 - 20060115926 - Methods of forming conductive elements using organometallic layers and flowable, curable conductive materials A conductive element is formed on a substrate by forming an organometallic layer on at least a portion of a surface of the substrate, heating a portion of the organometallic layer, and removing an unheated portion of the organometallic layer. In other methods, a flowable, uncured conductive material may be ... 06/01/06 - 20060115925 - Methods of fabricating a microlens including selectively curing flowable, uncured optically trasmissive material A microlens for use in an imaging device may be fabricated by disposing a flowable, uncured optically transmissive material in at least one layer onto a surface of a substrate, selectively curing at least a portion of the flowable, uncured optically transmissive material, and removing the flowable, uncured optically transmissive ... 05/25/06 - 20060110850 - Method for two-stage transfer molding device to encapsulate mmc module A method for fabricating a semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined ... 05/25/06 - 20060110849 - Method for stacking bga packages and structure from the same The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first ... 05/25/06 - 20060110848 - Off-width pitch for improved circuit card routing Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding ... 05/18/06 - 20060105496 - Device and method for fabricating double-sided soi wafer scale package with through via connections A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. A through buried oxide via connects the chip(s) to the ... 05/18/06 - 20060105495 - Device and method for reshaping the interconnection elements of an electronic module using the stress reflow method and, in particular, for restoring the flatness thereof A method and device are provided to reshape a set of conducting elements which are distributed over the inner face of an electronic module, said set of conducting elements forming means of positioning the module on a motherboard and/or electromagnetic armour means for the inner face of the module and/or ... 05/18/06 - 20060105494 - Method and apparatus for cleaning and sealing display packages A method and apparatus for cleaning and sealing components of a display utilizes continuous isolation of the components between the cleaning step and the sealing step. This limits exposure of the components to contaminants and isolates the components from oxidizing agents which can cause an oxide to form on the ... 05/11/06 - 20060099733 - Semiconductor package and fabrication method The present invention provides a first wafer and a second wafer having a device. A separation layer is formed on the first wafer. A cap is formed on the separation layer. The cap and the second wafer are bonded using a gasket. The first wafer is separated from the cap ... 05/04/06 - 20060094159 - Methods of manufacturing interposers with flexible solder pad elements Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped ... 05/04/06 - 20060094158 - Fabrication method of packaging substrate and packaging method using the packaging substrate A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate ... 05/04/06 - 20060094157 - Structure of mounting electronic component and method of mounting the same The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the ... 05/04/06 - 20060094156 - Semiconductor package substrate with embedded resistors and method for fabricating the same A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on ... 05/04/06 - 20060094155 - Method of manufacturing a wafer assembly A method of manufacturing a wafer assembly involves a chip wafer onto which a cover wafer is deposited, the chip wafer includes an active face and an inactive face, the active face includes chip elements, the cover wafer being provided with a chip-element-receiving cavity located above a chip element, the ... 04/27/06 - 20060088953 - Method for flip chip bonding by utilizing an interposer with embedded bumps The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a ... 04/20/06 - 20060084200 - Individually adaptable device surface The invention relates to device with electronic component which covers at least a part of a surface of the device. In order, even with large-scale mass production of a device, to allow the greatest possible individualization there is provision for the electronic component to feature both a number of switch ... 04/20/06 - 20060084199 - Processing method during a package process A processing method for preventing the lead fingers of a lead-frame from over-wetting and the conductive bumps from necking. After a flip chip is mounted to the lead fingers and before the reflowing process is conducted, the whole package structure is reversed so that conductive bumps are inclined to flow ... 04/20/06 - 20060084198 - Electrostatically actuated low response time power commutation micro-switches The field of the invention is that of microsystems of the electrostatically actuated microswitch type that are used in electronics to carry out switching functions, especially in the microwave field for mobile telephony and radars. The object of the invention is to improve the performance of the switch by reducing ... 04/13/06 - 20060079019 - Method for manufacturing wafer level chip scale package using redistribution substrate The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One ... 04/06/06 - 20060073633 - Protective interleaf for stacked wafer shipping A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions extending from a first surface thereof. The interconnection conductor material portions have a maximum height. An interleaf member is located between the first and second wafers. A ... 04/06/06 - 20060073632 - Die handling system A system may include singulation of a semiconductor wafer to separate a plurality of integrated circuit die that are integrated into the semiconductor wafer; coupling of a support to an integrated circuit substrate of one of the plurality of integrated circuit die, and decoupling of the one integrated circuit die ... 03/23/06 - 20060063304 - Structure and method of high performance two layer ball grid array substrate A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to ... 03/23/06 - 20060063303 - Packaging method, packaging structure and package substrate for electronic parts A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the ... 03/23/06 - 20060063302 - Apparatus and method for high density multi-chip structures Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which ... 03/23/06 - 20060063301 - Manufacturing method of a multi-layer circuit board with an embedded passive component A manufacturing method of a multi-layer circuit board with an embedded passive component includes providing a single layer plate having a dielectric layer and a first conductive foil, heating the single layer plate to melt the dielectric layer, pressing a passive component into the second surface of melting dielectric layer, ... 03/23/06 - 20060063300 - Structural design for flip-chip assembly An integrated circuit package comprises a semiconductor die located on a substrate in a flip-chip configuration, an encapsulant layer overlying the non-active surface of the semiconductor die and at least a portion of the surface of the substrate adjacent the die, and a heat spreader comprising a thermally conductive material. ... 03/16/06 - 20060057772 - Method for forming a redistribution layer in a wafer structure The present invention relates to a method for forming a redistribution layer in a wafer structure. The method comprises: (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive ... 03/16/06 - 20060057771 - Low cost fabrication of microelectrode arrays for cell-based biosensors and drug discovery methods A method for making a plurality of low-cost microelectrode arrays (MEAs) on one substrate utilizing certain unmodified printed circuit board (PCB) fabrication processes and selected materials. In some embodiments, a MEA device is composed of a thin polymer substrate containing patterned conductive traces. Coverlays on both sides of the substrate ... 03/16/06 - 20060057770 - Method for packaging chip and package assembly produced thereby A method for packaging a chip is rather than a conventional package technology and can improve the ability of packaging a photoelectric chip in order to save materials and costs. A chip package assembly is produced by preparing a transparent substrate in advance, a chip is electrically connected to a ... 03/16/06 - 20060057769 - Use of conductive carbon black/graphite mixtures for the production of low-cost electronics The invention relates to conductive polymer solutions which can be employed for the production of organic electronic components. To this end, particles of carbon black and graphite are used in the form of microplatelets in polymer solutions. ... 03/16/06 - 20060057768 - Semiconductor element heat dissipating member, semiconductor device using same and manufacturing same A semiconductor element heat dissipating member is provided which has excellent heat dissipation characteristics and adhesion characteristics and enables production of a semiconductor device at a low cost. A semiconductor device using the same, and a method of producing the same are also provided. The semiconductor element heat dissipating member ... 03/09/06 - 20060051892 - Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the ... 03/09/06 - 20060051891 - Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the ... 03/09/06 - 20060051890 - Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the ... 03/09/06 - 20060051889 - Chip assembly reinforcement Reinforced IC assemblies and methods useful for manufacturing the same are described. A reinforced IC assembly has a mounting surface for receiving a semiconductor die and a semiconductor die affixed to the mounting surface with an underfill material interposed between the mounting surface and the semiconductor die. Fillet material reinforces ... 03/02/06 - 20060046349 - Semiconductor device manufacturing method and apparatus used in the semiconductor device manufacturing method A semiconductor device manufacturing method includes forming circuit devices and a plurality of electrode pads within a semiconductor chip formation region. The method also includes forming, on the main surface of the semiconductor wafer, an insulating film which exposes a portion of each of the electrode pads. The method also ... 03/02/06 - 20060046348 - Semiconductor chip packages and methods for fabricating the same Semiconductor chip packages of a wafer level and method for fabricating the same are disclosed, in which a wafer electrode pad is connected with an external circuit by a via-electrode penetrating a silicon wafer. An illustrated example package includes a wafer having a first surface and a second surface opposite ... 03/02/06 - 20060046347 - Die package, conductive element, semiconductor device including same, microlens, system including same, and methods of manufacture A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at least one semiconductor die and at least partially cured substantially as a whole. Method of forming conductive elements such as traces, vias, ... 03/02/06 - 20060046346 - Methods for packaging microfeature devices and microfeature devices formed by such methods Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of microelectronic dies on and/or in the substrate. The ... 02/23/06 - 20060040424 - Semiconductor device substrate, semiconductor device, and manufacturing method thereof A method of manufacturing a semiconductor device substrate includes the steps of: arranging on a base a temporary fixing member for temporarily fixing an electronic component; temporarily fixing the electronic component on the base by the temporary fixing member; forming a substrate body on the base and the electronic component; ... 02/23/06 - 20060040423 - Attachment of integrated circuit structures and other substrates to substrates with vias Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The ... 02/23/06 - 20060040422 - Microelectronic devices and methods for manufacturing and operating packaged microelectronic device Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged microelectronic device comprises a die including integrated circuitry, a first casing coating at least a portion of the die, a heat sink proximate to the die, and a second casing on ... 02/23/06 - 20060040421 - Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors ... 02/16/06 - 20060035408 - Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components A method for designing a spacer to be used in a stacked multi-chip module includes configuring a spacer layer that is nonconfluent or includes voids. The spacer layer is configured to at least partially space the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement ... 02/16/06 - 20060035407 - Semiconductor substrate structure and processing method thereof A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite ... 02/16/06 - 20060035406 - Method of forming a composite polymer material inside trenches of a semiconductor substrate to form a composite polymer structure A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite ... 02/09/06 - 20060030073 - Methods for securing components of semiconductor device assemblies to each other with adhesive materials that include pressure-sensitive and curable components A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least temporarily secure the semiconductor device component and the other element to each other. The pressure-sensitive component of the adhesive material temporarily ... 02/09/06 - 20060030072 - Methods for securing packaged semiconductor devices to carrier substrates A method for securing a semiconductor device to a carrier substrate includes inserting a semiconductor device with a plurality of stub contacts extending from a bottom edge thereof into a receptacle of an alignment device associated with the carrier substrate. Upon attachment of the alignment device to a carrier substrate ... 02/09/06 - 20060030071 - Method for processing base The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both ... 02/09/06 - 20060030070 - Packaging structure and method of an image sensor module This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein ... 02/09/06 - 20060030069 - Packaging method for manufacturing substrates A method for manufacturing IC substrate is provided, including using the bottom plating technique to form copper columns to elevate the |