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Semiconductor Device Manufacturing: Process > With Measuring Or Testing > Electrical Characteristic Sensed > Utilizing Integral Test Element Utilizing Integral Test ElementUtilizing Integral Test Element patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.03/29/07 - 20070072319 - Integrated circuit capacitor structure Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first ... 01/18/07 - 20070015297 - Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate ... 01/11/07 - 20070010034 - Deposition stop time detection apparatus and methods for fabricating copper using the same A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide ... 01/04/07 - 20070004063 - Technique for evaluating a fabrication of a die and wafer The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known ... 12/28/06 - 20060292715 - Method for fabricating a metal-insulator-metal capacitor A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening ... 12/21/06 - 20060286691 - Capacitance modeling A method of modeling capacitance for all practical 2D on-chip wire structures including coplanar and microstrip structures. The method includes using a field lines approach (600) to obtain capacitance expressions for structure components, combining the expressions (704) for components of the subject structure and obtaining a capacitance expression (705) for ... 10/12/06 - 20060228818 - Edge temperature compensation in thermal processing particularly useful for soi wafers A retuning process particularly useful with an Ar/H2 smoothing anneal by rapid thermal processing (RTP) of a silicon-on-insulator (SOI) wafer performed after cleavage. The smoothing anneal or other process is optimized including a radial temperature profile accounting for the edge ring and exclusion zone and the vertically structured SOI stack ... 09/14/06 - 20060205099 - Die testing using top surface test pads Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within ... 06/01/06 - 20060115911 - Layout verification method and method for designing semiconductor integrated circuit device using the same To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification ... 03/30/06 - 20060068514 - Method of detecting un-annealed ion implants A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s). ... 02/09/06 - 20060030062 - Micromachined wafer strain gauge A micromachined strain gauge comprising a plastically deformable piezoresistive microstructure formed on a surface of a substrate so that deformation of the substrate plastically deforms the microstructure to thereby change the resistance of the microstructure. The stress in the substrate can be determined from the change in the resistance of ... 02/02/06 - 20060024853 - Structure for monitoring semiconductor polysilicon gate profile Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of ... 02/02/06 - 20060024852 - Temperature sensor for high power very large scale integration circuits Disclosed is a temperature sensor for an integrated circuit having at least one field effect transistor (FET) having a polysilicon gate, in which a current and a voltage is supplied to the polysilicon gate, changes in the current and the voltage of the polysilicon gate are monitored, wherein the polysilicon ... 12/08/05 - 20050272174 - Test structures in unused areas of semiconductor integrated circuits and methods for designing the same The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the ... 06/30/05 - 20050142674 - Fabrication method of semiconductor integrated circuit device Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or ... 06/30/05 - 20050142673 - Method for manufacturing semiconductor device A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on ... ### FreshPatents.com Support |