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Semiconductor Device Manufacturing: Process > With Measuring Or Testing > Electrical Characteristic Sensed Electrical Characteristic SensedElectrical Characteristic Sensed patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.02/22/07 - 20070042514 - Method and apparatus for cooling a blade server A method and apparatus adapted to cool a circuit board in a rack-mountable housing includes transferring heat from a heat source on the board to a primary heat storage medium positioned at an edge of the board or within a rack-mountable housing using at least one heat pipe, transferring heat ... 01/04/07 - 20070004062 - Display panel, display panel inspection method, and display panel manufacturing method A method of inspecting a display panel, which is capable of distinguishing between whether an EL panel is a good product or a defective product before sealing of the display panel, is provided. In a first method of inspection, a conductive film is patterned to forming pixel electrodes after measuring ... 12/07/06 - 20060275935 - Testing electromigration at multiple points of a single node Systems and methods for testing the reliability of a semiconductor component are disclosed herein. One embodiment of a method for testing reliability, among others, comprises providing simulation code of a standard cell, wherein the standard cell represents the semiconductor component. The method includes extracting foliage points of a node of ... 11/30/06 - 20060270073 - Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width ... 10/12/06 - 20060228817 - Dispensable capacitor manufacturing process A dispensable capacitor manufacturing process allowing easier process, capacity correction facilitating, and reduced production cost essentially involves dispensing conductive epoxy between two soldering points on a PCB, use of laser to cut on the surface of solidified epoxy spaced grooves in different forms, heated dielectric material then permeated, insulation layer ... 09/28/06 - 20060216841 - Method, system and computer-readable code for testing of flash memory Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are ... 08/17/06 - 20060183257 - Method for analyzing electrolytic copper plating solution, and analyzing device therefor and production method for semi-conductor product Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of 0.1-20 A/dm2. The potential change is determined at a working electrode rotation of 100-7500 rpm, and the fillability with the solution is judged from ... 08/03/06 - 20060172445 - Method for determining properties of a film, and apparatus for realizing the method A method for determining properties or a thin film includes the steps of: providing a piezoelectric substrate; providing a slanted finger interdigital transducer unit that includes a transmitter port and a receiver port on the piezoelectric substrate; forming the thin film on the piezoelectric substrate between the transmitter port and ... 07/27/06 - 20060166385 - Method for measuring peak carrier concentration in ultra-shallow junctions A method is disclosed for determining peak carrier concentration in ultra shallow junctions of semiconductor samples. A region of the surface of the sample is periodically excited. The effects of the excitation are monitored by a probe beam. Synchronous detection produces in-phase (I) and quadrature (Q) signals. These signals are ... 07/27/06 - 20060166384 - Method for manufacturing industrial products and combination of masks for manufacturing the same A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product ... 07/13/06 - 20060154388 - Integrated metrology chamber for transparent substrates The embodiments of the invention relate to a method and apparatus for measuring the etch depth between etching for an alternate phase shift photomask in a semiconductor photomask processing system. The apparatus for measuring the etch depth of a substrate in an etch processing system comprises a measurement cell coupled ... 07/06/06 - 20060148113 - Chain resistance pattern and method of forming the same A chain resistance pattern and a method of forming the same enable a test pattern to obtain maximum measurement results using minimum area and enable accurate detection of process errors. The chain resistance pattern includes an active layer for receiving an externally applied optical signal, a plurality of conductive layers ... 07/06/06 - 20060148112 - Electrode design Electrodes of a double-layer capacitor are designed so that sub-capacitors formed at each electrode are stressed substantially equally at the rated voltage of the double-layer capacitor. In an exemplary embodiment, each electrode includes a current collector and an active electrode layer, such as a layer of activated carbon. The electrodes ... 06/15/06 - 20060128041 - Misalignment test structure and method thereof A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The ... 06/01/06 - 20060115910 - Method for predicting lifetime of insulating film ∫0TBDIdt=Q (1) ... 04/20/06 - 20060084191 - Packaging method for an electronic element A packaging method for an electronic element has: etching portions of a top surface of a metal board to form recesses between raised unetched segments and filling the recesses with a dielectric material of high density polymer; forming multiple solder balls respectively on the raised unetched segments; coating the solder ... 03/23/06 - 20060063286 - Using a time invariant statistical process variable of a semiconductor chip as the chip identifier A method for providing an identifier for a semiconductor chip after the manufacture of the semiconductor chip using a fabrication process includes selecting one or more circuit elements formed on the semiconductor chip where each of the circuit elements having an electrical parameter that has a time-invariant statistical process variation, ... 03/23/06 - 20060063285 - Methods for measuring die temperature Methods for measuring device temperature. In one example, device temperature may be determined by measuring a voltage across a diode arranged to provide electrostatic discharge protection for the die and calculating the die temperature using the voltage measured across the diode. Alternatively, other components on the die, not dedicated to ... 03/02/06 - 20060046324 - Method and apparatus for testing tft array A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a ... 01/19/06 - 20060014309 - Temporary chip attach method using reworkable conductive adhesive interconnections A method for temporary chip attach to determine known good die using a reworkable conductive adhesive interconnection between the chip carrier and die. The die is easily separated from the chip carrier after test, without the use of potentially damaging shear forces, by subjecting the TCA assembly to a rework ... 01/12/06 - 20060008929 - Method and apparatus for the improvement of material/voltage contrast A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal ... 12/29/05 - 20050287685 - Localizing a temperature of a device for testing Wafers or other structures comprising a plurality of dies or devices are tested at non-ambient temperatures by inducing a first heat flux through a substantial portion of a surface of the structure to modify a temperature of the structure and inducing a second heat flux through a local area of ... 12/29/05 - 20050287684 - Apparatus and method for detecting soft breakdown of a dielectric layer of a semiconductor wafer To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that ... 12/29/05 - 20050287683 - Method and apparatus for determining generation lifetime of product semiconductor wafers To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a ... 12/08/05 - 20050272173 - Method for testing contact open in semiconductor device The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching ... 09/29/05 - 20050214960 - Surface shape recognition sensor and method of manufacturing the same A method of manufacturing a surface shape recognition sensor. A sacrificial film is formed on an interlevel dielectric to cover a lower electrode while keeping an upper portion of a support electrode exposed. An upper electrode is formed on the sacrificial film and support electrode. The sacrificial film is selectively ... 09/15/05 - 20050202577 - Manufacturing and testing of electrostatic discharge protection circuits A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or ... 09/15/05 - 20050202576 - Compliant contact structures, contactor cards and test system including same, and methods of fabrication and use A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally ... 09/08/05 - 20050196884 - Method of evaluating semiconductor device The present invention provides a method of evaluating a semiconductor device having an ESD protective element, wherein a MOSFET is formed on the same substrate, comprising a step (electric characteristic measurement) for measuring an electric characteristic of the MOSFET, a step (snapback characteristic measurement) for measuring a snapback characteristic of ... 09/08/05 - 20050196883 - Evaluation method using a teg, a method of manufacturing a semiconductor device having a teg, an element substrate and a panel having the teg, a program for controlling dosage and a computer-readable recording medium recording the program The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs ... 07/28/05 - 20050164416 - Method for processing an integrated circuit Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The ... 07/21/05 - 20050158890 - Silicon-on-insulator channel architecture for automatic test equipment A channel architecture for use in automatic test equipment is disclosed. The channel architecture comprises pattern generation circuitry and timing circuitry responsive to the pattern generation circuitry to generate timing signals. Formatting circuitry coupled to the output of the timing circuitry generates pulse waveforms for application to pin electronics circuitry. ... 07/14/05 - 20050153467 - Method of monitoring introduction of interfacial species A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the ... 06/16/05 - 20050130334 - Self-aligned contact process implementing bias compensation etch endpoint detection and methods for implementing the same A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having ... 06/09/05 - 20050124085 - Process for preparation of semiconductor wafer surface A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate. ... ### FreshPatents.com Support |