With Measuring Or Testing

With Measuring Or Testing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/12/07 - 20070082417 - Method and structure for reducing prior level edge interference with critical dimension measurement
A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via ...

04/05/07 - 20070077667 - Semiconductor wafer test system
A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates ...

04/05/07 - 20070077666 - Efficient provision of alignment marks on semiconductor wafer
A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each ...

04/05/07 - 20070077665 - Tool for creating customized user interface definitions for a generic utility supporting on-demand creation of field device editor graphical user interfaces
A customization tool is described in association with a universal device type manager (DTM) utility. The customization tool includes a set of user interfaces and associated functionality that facilitates creating a set of customized templates for a particular device type. The customized templates define access to device data via graphical ...

03/29/07 - 20070072318 - Method for predicting the formation of silicon nanocrystals in embedded oxide matrices
A method for predicting the formation of silicon nanocrystals in an oxide matrix is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. Kinetic models are then built by utilizing the fundamental data for a set of ...

03/29/07 - 20070072317 - Method for predicting contributions of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation
A method for predicting the contribution of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. The fundamental data are then utilized to ...

03/29/07 - 20070072316 - Wiring pattern determination method and computer program product thereof
A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions that can be accommodated in positionable windows nearest to the respective tentatively designed plated lead positions, in a template ...

03/29/07 - 20070072315 - Method and system for reliability similarity of semiconductor devices
A method and system for reliability similarity of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, and determining a first reliability associated with the first plurality of semiconductor devices. The first reliability is represented by at least a first ...

03/29/07 - 20070072314 - Method of preparing an integrated circuit die for imaging
Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene ...

03/29/07 - 20070072313 - Anisotropic conductive connector and circuit device inspection method
It is an object to provide an anisotropically conductive connector having an excellent repetitive use durability and a method of inspecting a circuit device having a high inspection efficiency which are used in the inspection of the circuit device such as a semiconductor integrated circuit having a solder projected electrode. ...

03/22/07 - 20070065956 - Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe
There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe ...

03/15/07 - 20070059851 - Multiple point gate oxide integrity test method and system for the manufacture of semiconductor integrated circuits
A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a ...

03/15/07 - 20070059850 - Method and system for derivation of breakdown voltage for mos integrated circuit devices
A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and ...

03/15/07 - 20070059849 - Method and system for barc optimization for high numerical aperture applications
A method is described for setting up lithographic processing of a substrate. The lithographic processing uses a bottom anti-reflective coating for minimizing the substrate reflectivity. Such bottom anti-reflective coating typically is characterized by a set of selectable BARC parameters, such as the thickness, real refractive index, and/or absorption coefficient. The ...

03/15/07 - 20070059848 - Method of controlling impurity doping and impurity doping apparatus
Disclosed here is a method of controlling a dose amount of dopant to be doped into object (1) to be processed in plasma doping. According to the method, the doping control is formed of the following processes: determining the temperature of object (1), the amount of ions having dopant in ...

03/08/07 - 20070054423 - Method for controlling thickness distribution of a film
A method for forming an oxide film includes a first in-situ steam generation (ISSG) process using a 1%-H2 concentration in the ambient gas and a subsequent second ISSG process using a 5%-H2 concentration in the ambient gas, wherein the second ISSG process compensates an in-plane thickness distribution of the film ...

03/08/07 - 20070054422 - Test structure for electrically verifying the depths of trench-etching in an soi wafer, and associated working methods
The aim of the invention is to discover a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of these trenches should be increased, the production of refuse should be prevented, ...

03/01/07 - 20070048883 - Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device
By measuring an electric characteristic of a test pad that is connected to a plurality of test vias formed in accordance with a specified process flow for forming contacts and vias of a semiconductor device, one or more process specific parameters may quantitatively be estimated. Thus, a fast and precise ...

02/22/07 - 20070042512 - Apparatus and method of predicting performance of semiconductor manufacturing process and semiconductor device, and manufacturing method of semiconductor device
Apparatus and method of predicting performance of a semiconductor manufacturing process and device, which reduces simulation resources to predict the performance distribution in the wafer and manufacturing method of a semiconductor device are disclosed. According to one aspect, it is provided a performance prediction apparatus comprising a uniform mesh data ...

02/22/07 - 20070042511 - Substrate processing apparatus and substrate processing method
A substrate processing apparatus performs a chemical solution process in a chemical solution process room that is partially formed within a chamber. During the chemical solution process, the substrate processing apparatus seals the chemical solution process room, and measures the pressure within the chemical solution process room, and controls the ...

02/22/07 - 20070042510 - In situ process monitoring and control
Systems and methods for monitoring a semiconductor manufacturing process are provided. The method includes: performing a semiconductor manufacturing process step on a wafer; directing light having a known wavelength at the wafer; monitoring a predetermined spectral range of light transmitted through a selected region of the wafer to detect an ...

02/15/07 - 20070037301 - Method and apparatus for monitoring precision of wafer placement alignment
A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the ...

02/15/07 - 20070037300 - Systems and methods for plasma processing of microfeature workpieces
Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured ...

02/08/07 - 20070031982 - Method of classifying defects and apparatus for performing the method
In a method of classifying defects, actual information with respect to actual defects by each of processes on an object on which the processes are sequentially carried out is obtained. The actual information is accumulated in sequence of the processes to obtain composite information by each of the processes with ...

02/01/07 - 20070026547 - Cluster tool and method for process integration in manufacture of a gate structure of a field effect transistor
A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to ...

02/01/07 - 20070026546 - Method of detecting misalignment of ion implantation area
A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of ...

02/01/07 - 20070026545 - Methods and systems for controlling semiconductor device manufacturing processes
A first process time period for a manufacturing process is determined, and a thickness of a material on a sample semiconductor substrate using the first process time period is measured. If the thickness is not within a desired thickness range, a second process time period for the manufacturing process for ...

02/01/07 - 20070026544 - Impurity diffusion simulation method, impurity diffusion simulation apparatus, and impurity diffusion simulation program
The as-implanted concentration profile of impurity atoms in the semiconductor substrate is calculated, and a number of interstitial atoms to be generated in the semiconductor substrate by one impurity atom implanted with the ion implantation is set based on a peak concentration of the calculated as-implanted concentration profile of impurity ...

01/25/07 - 20070020783 - Method of feed forward control of scanned rapid thermal processing
A thermal processing system and method including scanning a line beam of intense radiation in a direction transverse to the line direction for thermally processing a wafer with a localized effectively pulsed beam of radiant energy. The thickness of the wafer is two-dimensionally mapped and the map is used to ...

01/25/07 - 20070020782 - Method of monitoring a semiconductor manufacturing trend
A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test ...

01/25/07 - 20070020781 - Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program
A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display ...

01/25/07 - 20070020780 - Method of processing semiconductor substrate responsive to a state of chamber contamination
In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the ...

01/25/07 - 20070020779 - Quantum dot conjugates in a sub-micrometer fluidic channel
A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of ...

01/25/07 - 20070020778 - Method and monitor structure for detecting and locating ic defects
A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity ...

01/25/07 - 20070020777 - Controlling system for gate formation of semiconductor devices
A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may ...

01/18/07 - 20070015296 - Methods and systems for characterizing semiconductor materials
Methods for determining parameters of a semiconductor material, for example, non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GeOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates are described. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The ...

01/18/07 - 20070015295 - Methods and systems for characterizing semiconductor materials
Methods for determining parameters of a semiconductor material, in particular non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The critical points ...

01/11/07 - 20070010033 - Method and system for deposition tuning in an epitaxial film growth apparatus
A method of calculating a process parameter for a deposition of an epitaxial layer on a substrate. The method includes the steps of measuring an effect of the process parameter on a thickness of the epitaxial layer to determine a gain curve for the process parameter, and calculating, using the ...

01/04/07 - 20070004059 - Method of measuring alignment of measurement pattern
A resist pattern for alignment measurement being shrunk by a heat flow includes a plurality of positive type or negative type line patterns. Widths of spaces between the line patters are greater than twice those of the line patterns. Alternatively, the resist pattern comprises a box-shaped or slit-shaped measurement pattern ...

01/04/07 - 20070004058 - Semiconductor manufacturing device with transfer robot
Semiconductor manufacturing equipment is disclosed and comprises a robot comprising a robotic arm adapted to transfer a wafer from a wafer cassette in a load lock chamber to a processing chamber with proper alignment and positioning without the need to intermediately pass through a support chamber specially adapted to align ...

01/04/07 - 20070004057 - Substrate processing method
A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit ...

01/04/07 - 20070004056 - Systems and methods for direct silicon epitaxy thickness measuring
Systems and methods for measuring thickness of an epitaxial layer grown on a silicon wafer. An oxide layer is generated on a side of the silicon wafer. One or more posts of oxide are created from the oxide layer by masking and removing unwanted oxide. An epitaxial layer is grown ...

01/04/07 - 20070004055 - Method for regulating temperature and circuit therefor
A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including ...

12/28/06 - 20060292713 - Semiconductor integrated circuit device
To provide a semiconductor device which can be down-sized and integrated to a high degree. A semiconductor device including a rewiring mixedly includes an input/output (I/O) cell connected to a probing pad; and another input/output (I/O) cell having no probing pad. ...

12/28/06 - 20060292712 - Process for the detection of a malfunction in a device for wire sawing and device for practicing said process
The invention relates to a process for the detection of malfunctions, in particular the detection of breakage of a wire in a wire sawing device. The process consists in applying an alternating signal to the layer of wires (4) of the sawing device and measuring the variations of voltage or ...

12/28/06 - 20060292711 - Mechanical integrity evaluation of low-k devices with bump shear
A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). ...

12/28/06 - 20060292710 - Sensor and method for detecting electric contact degradation
A probe cell monitors conditions within electrical power transmission and switchgear apparatus to detect degradation of stressed components. The probe cell is a hardware simulation of components of a specific unit of electrical power apparatus, including electrodes between which an electric field gradient is established. The probe cell electrodes accumulate ...

12/28/06 - 20060292709 - Method for fabricatiing three-dimensional microstructure by fib-cvd and drawing system for three-dimensional microstruture
There are provided a fabrication method of a nanostructure by FIB-CVD which enables fabrication of a three-dimensional nanostructure, especially that without a support such as a terrace structure or a hollow structure, and a drawing system thereof. The three-dimensional nanostructure is fabricated by controlling a focused ion beam to determine ...

12/21/06 - 20060286690 - Mask cd correction based on global pattern density
The present disclosure provide a method of forming a photomask layout. In one example, the method comprises selecting a pattern feature on the photomask layout, defining a global area centered at the pattern feature on the photomask layout, calculating a pattern density inside the global area, and correcting the pattern ...

12/14/06 - 20060281200 - Method and system for using pattern matching to process an integrated circuit design
Disclosed is a method, system, and computer program product for processing design objects, such as vias, for an integrated circuit design. In one approach, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. A library of via combinations can be used to insert scattering bars into design. ...

12/14/06 - 20060281199 - Abnormality cause specifying method, abnormality cause specifying system, and semiconductor device fabrication method
A feature amount is generated by standardizing inspection data related to a fabrication unit for each type, a similar set including fabrication units corresponding to similar feature amounts is formed by comparing the feature amounts, and apparatus difference analysis is performed between a plurality of fabrication units forming the similar ...

12/14/06 - 20060281198 - Pattern drawing system, electrically charged beam drawing method, photomask manufacturing method, and semiconductor device manufacturing method
A pattern drawing system includes a beam irradiating mechanism which irradiates electrically charged beams on a film to be drawn, a coefficient calculating section which calculates a backward scattering coefficient relevant to a drawing pattern in the film to be drawn, based on an approximating function for approximating a relationship ...

12/14/06 - 20060281197 - Method and apparatus for completely covering a wafer with a passivating material
A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine ...

12/07/06 - 20060275934 - Management of computer processes
It is determined that an amount of total memory utilized by active processes exceeds a memory pressure threshold. There is deactivated at least one active process occupying space in the total memory during a first system cycle based on said determination. There is deactivated a number N of active processes ...

12/07/06 - 20060275933 - Thermally conductive ceramic tipped contact thermocouple
An apparatus for processing a substrate. The apparatus comprising a tubular member with a first end and a second end. The first end comprising an opening; and a temperature sensor disposed in the opening. The temperature sensor comprising a resilient member. The resilient member comprising a surface made of a ...

11/30/06 - 20060270072 - Mask forming method and semiconductor device manufacturing method
A mask forming method includes preparing design data of mask including pattern regions having identical repetition patterns respectively, generating mask pattern data of mask based on the design data, generating inspection control information for controlling inspection of defect on mask based on the mask pattern data, the information including positional ...

11/30/06 - 20060270071 - Method of reducing charging damage to integrated circuits during semiconductor manufacturing
A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device ...

11/23/06 - 20060263916 - Infrared thermopile detector system for semiconductor process monitoring and control
A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes. ...

11/23/06 - 20060263915 - Device for testing an exposure apparatus
A device and a method for testing an exposure apparatus is disclosed. A testing device includes a substrate, and a plurality of block patterns, each of which has a top area varying with an area of a shot region of the exposure apparatus, having at least two different heights located ...

11/23/06 - 20060263914 - Testing chip and micro integrated analysis system
A testing chip includes (1) a first chip having a micro flow path that stores reagent; upstream-side opening provided on upstream-side of the micro flow path; downstream-side opening provided on downstream-side of the micro flow path; and one or more sealing members in a small thickness stuck to at least ...

11/23/06 - 20060263913 - Systems and methods for maintaining performance at a reduced power
Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor that generates a signal indicative of at least one performance characteristic of at least a portion of a critical path associated with the integrated circuit. The ...

11/23/06 - 20060263912 - Systems and arrangements to assess thermal performance
Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some ...

11/16/06 - 20060258025 - Fabrication method of ic inlet, id tag, id tag reader and method of reading date thereof
A method accurately inspects whether an IC inlet to be inspected is non-defective or defective in a state in which a large number of IC inlets are formed over an insulating film. The inspection of IC inlets formed over an insulating film is performed by transmitting microwaves to the IC ...

11/16/06 - 20060258024 - Method of inspecting integrated circuits during fabrication
A method and system for inspecting integrated circuit chips during fabrication. The method including: selecting an integrated circuit chip at a selected level of fabrication; determining coordinates of potential failures of the integrated circuit chip based on one or more risk of failure analyses performed ancillary to fabrication of the ...

11/16/06 - 20060258023 - Method and system for improving integrated circuit manufacturing yield
A lithographic scanner collects surface height information concurrently with conducting a lithographic scan process. A defect identification module identifies wafers having a surface height metric greater than a determined threshold. The identified wafers may be separated for rework to correct the surface defects such as hotspots and improve manufacturing yield ...

11/09/06 - 20060252162 - Method and apparatus for electronically aligning capacitively coupled mini-bars
One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects ...

11/02/06 - 20060246611 - Method of and apparatus for controlling probe tip sanding in semiconductor device testing equipment
In a method of and apparatus for controlling probe tip sanding in semiconductor device testing equipment, resistance values of pads of a probed chip are measured and stored. If a maximum resistance value among the stored resistance values is greater than a contact resistance reference value, a consecutive fail counting ...

11/02/06 - 20060246610 - Allocating manufactured devices according to customer specifications
A method and system sorts manufactured integrated circuit devices by evaluating performance characteristics of the manufactured integrated circuit devices. All of the integrated circuit devices are manufactured using an identical design, and differences in the performance characteristics among the integrated circuit devices occurs because of variations including manufacturing line variations. ...

11/02/06 - 20060246609 - Dynamic metal fill for correcting non-planar region
Methods and a system are disclosed for correcting a non-planar region during fabrication of a semiconductor product on a wafer. The invention separates an exposure of at least a portion of a fill pattern on a resist from a product exposure so that the fill pattern can be adjusted to ...

10/26/06 - 20060240582 - Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface ...

10/26/06 - 20060240581 - Method for assembling testing equipment for semiconductor substrate
Upon an assembly of a probe head unit, the relative positions of the probe pins 28ai to those of the electrode group 24E in the pitch-changing substrate 24 are determined by making the positions of the through-holes 26A, 26B, 26C and 26D in the contact block 26 to coincide with ...

10/26/06 - 20060240580 - Method for evaluating reproduced images of wafers
Method for evaluating recorded images of wafers is disclosed. The recording of an image of at least one reference wafer is followed by the determination and representation, on a user interface, of the radial distribution of the measured values of the reference wafer as a radial homogeneity function. A radially ...

10/19/06 - 20060234404 - Method for predicting and optimizing chip performance in cured thermoset coatings
Disclosed is a method for evaluating chip performance of a cured coating system. In one embodiment, the method includes providing a coated substrate comprising a substrate and a cured film of a first coating composition thereon, measuring elastic work energy (We/Wtot) of the cured film, and calculating a % C.P. ...

10/19/06 - 20060234403 - Wat process to avoid wiring defects
A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer. ...

10/19/06 - 20060234402 - Method of recipe control operation
An operation method of a recipe control process in which multiple processing targets are processed continuously in a processing apparatus using recipes that specify a set of control parameters specifying the processing conditions of processing targets. The method comprises the steps of: (I) specifying correction coefficients to correct at least ...

10/19/06 - 20060234401 - Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line
A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the ...

10/19/06 - 20060234400 - Method of judging quality of semiconductor epitaxial crystal wafer and wafer manufacturing method using the same
In a method of determining the quality of a semiconductor epitaxial crystal wafer having a buffer structure portion comprised of epitaxial layers the semiconductor epitaxial crystal wafer (S) is irradiated with pulsed exciting light (5A) to modulate an internal electric field of the buffer structure portion, the electric transport properties ...

10/05/06 - 20060223204 - System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, ...

10/05/06 - 20060223203 - Advanced process control model incorporating a target offset term
An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an ...

10/05/06 - 20060223202 - Offline screening of outgas emissions in semiconductor processing
The present description relates to measuring outgas emissions in fabrication chambers used for semiconductors, micromachines and the like. In one embodiment, the invention includes inserting a gas adsorption material into a processing chamber exhaust vent, running a process in the chamber, venting gasses in the chamber through the gas adsorption ...

09/28/06 - 20060216839 - Method for monitoring chamber cleanliness
A method for evaluating a cleanliness of a tool, the method includes: receiving a wafer; cleaning the wafer; placing the wafer into the tool for a predefined period; removing the wafer from the tool, performing a contact angle measurement and determining the cleanliness of the wafer. ...

09/28/06 - 20060216838 - Substrate, micro structure, method of making reference scale, and method of measuring length of micro structure
There is provided a substrate possessing a substrate main body in whose surface there is formed a measurement object article, and a reference scale having been provided, on the surface of the substrate main body, in the vicinity of a region where the measurement object article is formed so as ...

09/14/06 - 20060205098 - Method of determining n-well scattering effects on fets
A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary ...

09/07/06 - 20060199286 - System for reviewing defects, a computer implemented method for reviewing defects, and a method for fabricating electronic devices
A system for reviewing defects includes an analysis module configured to analyze defect information of a plurality of intermediate products, the defect information including information of an amount of defects classified by sizes of the defects existing in each of the intermediate products; a failure magnitude calculation module configured to ...

09/07/06 - 20060199285 - Highly activated carbon selective epitaxial process for cmos
In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess in ...

08/31/06 - 20060194353 - Method and circuit for the detection of solder-joint failures in a digital electronic package
The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a ...

08/31/06 - 20060194352 - Semiconductor device test system
An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device ...

08/24/06 - 20060189011 - Semiconductor device and control method
In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first ...

08/24/06 - 20060189010 - Method of testing fpc bonding yield and fpc having testing pads thereon
A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed corresponding to each of the bonding pads, and the testing pads are electrically isolated from the bonding ...

08/24/06 - 20060189009 - Apparatus for controlling semiconductor manufacturing process
An apparatus for controlling a semiconductor manufacturing process includes, a filter which receives from semiconductor processing devices first process parameters for processing a wafer and measured data obtained by measuring the wafer, and removes noise from the first process parameters and the measured data, a model generating unit which receives ...

08/24/06 - 20060189008 - Method for monitoring implantation depth of impurity
The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer, ...

08/24/06 - 20060189007 - Wirebond crack sensor for low-k die
A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures. ...

08/17/06 - 20060183256 - Method of piping defect detection
A method of piping defect detection is provided. A semiconductor substrate having an active region and an isolation region is provided, a plurality of semiconductor elements are formed on the semiconductor substrate, a dielectric layer is deposited on the semiconductor substrate and the semiconductor elements, and first and second contact ...

08/10/06 - 20060177949 - Method for monitoring oxide film deposition
A method for monitoring oxide film deposition is disclosed. The method utilizes silicon wafers having silicon nitride films thereon instead of bare silicon wafers to monitor the growth of silicon oxide/dioxide films in a furnace. The method for monitoring oxide film deposition comprises the following steps. First of all, a ...

08/03/06 - 20060172444 - Efficient method of forming and assembling a microelectronic chip including solder bumps
The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a correspondingly designed carrier substrate. In the process flow, a plasma-based process for patterning the underbump metallization layer is ...

08/03/06 - 20060172443 - Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an integrated circuit
The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image ...

08/03/06 - 20060172442 - Semiconductor production system and semiconductor production process
A semiconductor manufacturing apparatus according to the present invention comprises: a treating unit that treats a substrate to manufacture thereon a semiconductor device; a fluid supplying channel for supplying a fluid required for a treatment of the substrate to the treating unit; a set voltage outputting unit that outputs a ...

07/27/06 - 20060166382 - Method and apparatus for detecting backside particles during wafer processing
A method and apparatus for detecting backside particles during wafer processing is provided. The method includes holding a wafer with vacuum pressure, detecting the presence of particles on a backside of the wafer while holding the wafer with vacuum pressure, transferring the wafer into a process chamber and performing a ...

07/27/06 - 20060166381 - Mold cavity identification markings for ic packages
The invention provides small-feature identifying markings for tracing completed IC packages to individual mold cavities. Preferred embodiments of the invention include IC packages and associated methods for forming indicia in a surface of an integrated circuit package in an arrangement indicative of a particular mold cavity. The indicia may be ...

07/27/06 - 20060166380 - Method of integration testing for packaged electronic components
A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a testing carrier board so that conductive pins are oriented to test spaces ...

07/20/06 - 20060160256 - Method of inspecting substrate processing apparatus, and storage medium storing inspection program for executing the method
A method of inspecting a substrate processing apparatus that enables a reduction in operator labor time to be achieved. A host computer instructs a substrate processing apparatus to prohibit transfer of a product wafer into the substrate processing apparatus during a period of cleaning the substrate processing apparatus. The substrate ...

07/20/06 - 20060160255 - Driving circuit for amoled display and driving method thereof
A driving circuit and method for an active matrix organic light emitting diode (AMOLED) display are provided. The driving circuit comprises a power circuit, a linear thermistor, and a pixel circuit. The power circuit provides an equivalent current. The linear thermistor coupled to the power circuit adjusts the equivalent current ...

07/20/06 - 20060160254 - System and method for detection of spatial signature yield loss
A method and system are provided for identifying systematic yield losses. The method comprising testing produced products using a test sequence, the testing sequence producing yield data, the yield data related to a wafer. For each zone of each wafer size calculating and storing a first data series R1, wherein ...

07/13/06 - 20060154385 - Fabrication pathway integrated metrology device
An in-line, non-freestanding substrate measurement system is integrated into the substrate fabrication pathway. One embodiment includes a metrology device integrated into a guided vehicle. Another embodiment provides a system for simultaneously measuring both sides of a substrate. A metrology device may be integrated into the front handling chamber of a ...

07/06/06 - 20060148111 - Method for automatic measurement of failure in subthreshold region of metal-oxide-semiconductor transistor
A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained ...

06/22/06 - 20060134812 - Inspection methods for a semiconductor device
An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the ...

06/15/06 - 20060128039 - Yield analysis method
A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free ...

06/08/06 - 20060121632 - Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies
Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined ...

06/08/06 - 20060121631 - Method of producing semiconductor elements using a test structure
Testing the production of semiconductor elements on a substrate, the semiconductor elements having a plurality of cell types, by providing at least one test structure on the substrate with a number of test cells having cell types similar to one or more of the plurality of cell types, each of ...

05/25/06 - 20060110838 - Multilayered circuit substrate, semiconductor device and method of producing same
A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can ...

05/25/06 - 20060110837 - Method and system for topography-aware reticle enhancement
The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution ...

05/18/06 - 20060105476 - Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof
A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of ...

05/18/06 - 20060105475 - Fast localization of electrical failures on an integrated circuit system and method
Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize ...

05/11/06 - 20060099727 - Method of making a circuitized substrate having a plurality of solder connection sites thereon
A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different ...

05/04/06 - 20060094135 - Method of making semiconductor devices
A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed ...

05/04/06 - 20060094134 - Method of manufacturing inspection unit
A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a first ...

05/04/06 - 20060094133 - Method and apparatus for measuring surface carrier recombination velocity and surface fermi level
A pump beam irradiates the surface of a semiconductor sample through modulator while irradiating the surface with a probe beam so that a detector measures a light-modulated spectrum of the probe beam reflected from the surface of the semiconductor sample. Then, surface electric field strength is calculated from the period ...

05/04/06 - 20060094132 - Method for analyzing the structure of deep trench capacitors and a preparation method thereof
A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspection area, of the die are removed. A chemical etchant ...

05/04/06 - 20060094131 - System and method for critical dimension control in semiconductor manufacturing
Provided are a system and method for modifying a fabrication process based on inline measurement information during manufacture of a semiconductor device. In one example, the method includes exposing a photoresist layer on the device, performing post-exposure baking on the photoresist layer, and obtaining at least one critical dimension (CD) ...

04/27/06 - 20060088949 - Early detection of metal wiring reliability using a noise spectrum
The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. ...

04/27/06 - 20060088948 - Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel
A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module ...

04/20/06 - 20060084189 - Characterizing the integrity of interconnects
The present invention provides for a system and method of characterizing the integrity of a barrier structure. The barrier structure is an interconnect comprising a porous dielectric layer sandwiched between at least one barrier layer and at least one conducting layer. The method of characterizing the integrity of such an ...

04/20/06 - 20060084188 - Method for temperature control in a rapid thermal processing system
A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing baseline characteristic data and zone characteristic data, and then using the baseline and zone ...

04/13/06 - 20060079011 - Methods for marking a bare semiconductor die
A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including back grinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having ...

04/13/06 - 20060079010 - Transfer base substrate and method of semiconductor device
A transfer base substrate comprises: a substrate; a plurality of transfer thin film circuits formed on the substrate via removing layer; a test circuit formed on the substrate for checking circuit operation; and a wiring coupling each of transfer thin film circuits with a test circuit. ...

04/13/06 - 20060079009 - Fine-pitch electronic socket for temporary or permanent attachments
An electronic socket is described for providing either or both temporary and permanent attachments of electronic components to a substrate having interconnection circuits. The socket includes wells filled with a conductive fluid or paste for temporary attachment to the mesas of an electronic circuit. The wells are connected to selected ...

03/30/06 - 20060068513 - Film forming condition determination method, film forming method, and film structure manufacturing method
Among a plurality of parameters concerning a film forming condition, different parameter values are set for one parameter and the same predetermined values are set for other parameters to manufacture two pieces of film structures including a high-dielectric constant film or ferroelectric film formed on a substrate. The film characteristics ...

03/30/06 - 20060068512 - Method and apparatus for detecting defects
An inspection apparatus projects a laser beam on the surface of a SOI wafer and detects foreign matter on and defects in the surface of the SOI wafer by receiving scattered light reflected from the surface of the SOI wafer. The wavelength of the laser beam used by the inspection ...

03/30/06 - 20060068511 - Cmp process metrology test structures
A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with ...

03/23/06 - 20060063283 - Stacked die module and techniques for forming a stacked die module
Embodiments of the present technique relate to forming die stacks. Specifically, embodiments of the present technique include a method of forming and testing semiconductor die comprising forming a die stack of at least two semiconductor die without attaching either of the at least two semiconductor die to a substrate. Further, ...

03/23/06 - 20060063282 - Test structure and method for yield improvement of double poly bipolar device
A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector ...

03/23/06 - 20060063281 - Method and apparatus for uniformity and brightness correction in an oled display
A method for manufacturing and grading OLED devices is described, comprising the steps of: a) manufacturing OLED devices having a plurality of pixels; b) measuring pixel brightness and uniformity variation of each of the OLED devices prior to burning-in the OLED devices; c) correcting the pixel brightness and uniformity variation ...

03/16/06 - 20060057746 - Semiconductor device fabrication method and apparatus
According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a film made of an insulating material on a surface of a semiconductor substrate; measuring a film thickness and/or composition of the film; setting nitriding conditions or oxidation conditions on the basis of the measurement ...

03/09/06 - 20060051884 - Systems and methods for thin film thermal diagnostics with scanning thermal microstructures
Systems and methods are described for identifying characteristics and defects in material such as semiconductors. Methods include scanning a thermal probe in the vicinity of a semiconductor sample, applying stimuli to the thermal probe, and monitoring the interaction of the thermal probe and the semiconductor. The stimulus can be applied ...

03/02/06 - 20060046323 - In-situ critical dimension measrument
A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical ...

03/02/06 - 20060046322 - Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a ...

03/02/06 - 20060046321 - Underfill injection mold
An underfill injection mold includes an inner surface defining a cavity to receive injected underfill substantially between a first substrate and a second substrate. The cavity includes convex, curvilinear sidewalls to define a concave, curvilinear underfill fillet of the injected underfill. In an example, dimensions of the inner surface that ...

02/23/06 - 20060040418 - Method of correcting amplitude defect in multilayer film of euvl mask
By entering a low acceleration Si ion beam of 500 V or lower or a low acceleration Si ion beam of 500 V-2000 V having been slanted such that an injection depth becomes shallow, which has been mass-separated from a liquid alloy ion source containing Si by a mass separator ...

02/23/06 - 20060040417 - Method to build a wirebond probe card in a many at a time fashion
Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with ...

02/23/06 - 20060040416 - Method for manufacturing a light emitting device
A method for manufacturing an LED device includes the steps of mounting an LED on a substrate, sealing the LED with a transparent resin including phosphor particles to form an LED device before being dyed, measuring chromaticity of light from the LED device before being dyed; and dyeing the sealing ...

02/16/06 - 20060035395 - Process endpoint detection method using broadband reflectometry
A method of determining a parameter of interest during processing of a patterned substrate includes obtaining a measured net reflectance spectrum resulting from illuminating at least a portion of the patterned substrate with a light beam having a broadband spectrum, calculating a modeled net reflectance spectrum as a weighted incoherent ...

02/16/06 - 20060035394 - Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis
The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a drive current for semiconductor devices on a wafer-by-wafer basis. The method for manufacturing semiconductor devices, among other elements, includes patterning gate structures on a substrate (220), each ...

02/16/06 - 20060035393 - Methods for the determination of film continuity and growth modes in thin dielectric films
The invention provides methods for determining film continuity and growth modes in thin dielectric films. The continuity determining method comprises: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage ...

02/09/06 - 20060030061 - Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate
A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one ...

02/09/06 - 20060030060 - Apparatus and method for testing defects
An apparatus for detecting defects on a specimen including am illumination optical unit which obliquely projects a laser onto a region which is longer in one direction than in a direction transverse to said one direction on a surface of a specimen, a table unit which mounts said specimen and ...

02/02/06 - 20060024850 - Test structures and methods for monitoring or controlling a semiconductor fabrication process
Various test structures and methods for monitoring or controlling a semiconductor fabrication process are provided. One test structure formed on a wafer as a monitor for a lithography process includes a bright field target that includes first grating structures. The test structure also includes a dark field target that includes ...

01/26/06 - 20060019417 - Substrate processing method and substrate processing apparatus
A substrate processing method is used to polish a substrate. The substrate processing method includes rotating a substrate 13 by a motor 12, polishing a first surface of a peripheral portion of the substrate 13 by pressing a polishing surface of a polishing mechanism 20 against the first surface, determining ...

01/26/06 - 20060019416 - Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions
With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from ...

01/26/06 - 20060019415 - Rapid thermal anneal equipment and method using sichrome film
A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a ...

01/26/06 - 20060019414 - Wiring structure to minimize stress induced void formation
A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at ...

12/22/05 - 20050282300 - Back-end-of-line metallization inspection and metrology microscopy system and method using x-ray fluorescence
Systems and methods for performing inspection and metrology operations on metallization processes such as on back-end-of-line (BEOL) metallization thickness and step coverage are disclosed. Specific examples include measurements of thickness and uniformity of barrier layers, including tantalum for example, and seed layers, including copper for example, in Damascene, including dual-Damascene, ...

12/22/05 - 20050282299 - Wafer inspection system and method thereof
A wafer inspection system includes an electrical testing part to control a probe to be in contact with a pad of a wafer to perform a predetermined electrical test, a defect detecting part to detect a defect in the wafer passing through the electrical test, a defect sorting part to ...

12/22/05 - 20050282298 - Transport speed monitoring apparatus and semiconductor processing system utilizing the same
A semiconductor processing system utilizing transport speed monitoring of a wafer boat. The semiconductor processing comprises a process chamber, loading device, and transport speed monitoring device. The loading device transports a boat of wafers into and out of the process chamber where the wafers experience particular treatment. The transport speed ...

12/15/05 - 20050277210 - Sequential unique marking
The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling ...

11/24/05 - 20050260776 - Structure and method for extraction of parasitic junction capacitance in deep submicron technology
The present disclosure provides a structure and method for determining a parasitic junction voltage that cannot be directly measured because of lack of space for a probe. For example, the method may be used with a test structure having at least two transistors pairs. The first transistor pair may include ...

11/17/05 - 20050255611 - Defect identification system and method for repairing killer defects in semiconductor devices
A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action ...

11/17/05 - 20050255610 - Semiconductor wafer shape evaluating method and shape evaluating device
The present invention is a method of evaluating a shape of a semiconductor wafer comprising the steps of: measuring shape data of a semiconductor wafer by scanning a front surface and/or a back surface of the semiconductor wafer; calculating a differential profile through a differential process of the measured shape ...

11/10/05 - 20050250226 - Method for generating work-in-process schedules
A method and program is disclosed for generating work in progress (WIP) schedules in semiconductor manufacturing facility. After determining starting and ending dates of predetermined schedule periods for generating WIP schedules, remaining days are determined for completing at least one wafer lot associated with predetermined product from the starting date. ...

10/27/05 - 20050239223 - Method and device for monitoring the etching operation for a regular depth structure in a semiconductor substrate
In order to monitor the etching operation for a regular depth structure in a semiconductor substrate, a radiation source is used to irradiate, in large-area fashion, the semiconductor substrate in the region of the depth structure during the etching operation at a predetermined angle of incidence with respect to the ...

10/27/05 - 20050239222 - Run-to-run control of backside pressure for cmp radial uniformity optimization based on center-to-edge model
During planarization of wafers, the thickness of a layer of a wafer is measured at a number of locations, after the wafer has been planarized by chemical mechanical polishing. The thickness measurements are used to automatically determine, from a center to edge profile model to which the measurements are fit, ...

10/27/05 - 20050239221 - Method for conductive film quality evaluation
A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper ...

10/20/05 - 20050233481 - Novel development hastened stability of titanium nitride for apm etching rate monitor
A method of fabricating a stabilized TiN control wafer comprising the following steps. A silicon substrate is provided having a silicon oxide layer formed thereover. An initial TiN layer is formed over the silicon oxide layer. The silicon substrate is placed in an atmosphere having ambient oxygen for from about ...

10/20/05 - 20050233480 - Clearance inspection apparatus and clearance inspection method
A clearance inspection apparatus for inspecting clearance of a wiring line passing between vias on a substrate comprises: first determining means for determining vias adjacent on both sides of a reference via as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, ...

10/20/05 - 20050233479 - Cda controller and method for stabilizing dome temperature
A doomed plasma reactor chamber uses an antenna driven by RF energy which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls ...

10/13/05 - 20050227383 - Manufacturing method of semiconductor integrated circuit device and probe card
Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This ...

10/13/05 - 20050227382 - In-situ surface treatment for memory cell formation
A system and methodology are disclosed for forming a passive layer on a conductive layer, such as can be done during fabrication of an organic memory cell, which generally mitigates drawbacks inherent in conventional inorganic memory devices. The passive layer includes a conductivity facilitating compound, such as copper sulfide (Cu2S), ...

10/13/05 - 20050227381 - Using cell voltage as a monitor for deposition coverage
A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage. ...

10/13/05 - 20050227380 - Control of liner thickness for improving thermal cycle reliability
A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on ...

10/06/05 - 20050221514 - Adaptive sampling method for improved control in semiconductor manufacturing
A method is provided, the method comprising sampling at least one parameter characteristic of processing performed on a workpiece in at least one processing step, and modeling the at least one characteristic parameter sampled using an adaptive sampling processing model, treating sampling as an integrated part of a dynamic control ...

10/06/05 - 20050221513 - Method of controlling trimming of a gate electrode structure
A method and processing tool are provided for controlling trimming of a gate electrode structure containing a gate electrode layer with a first dimension by determining the first dimension of the gate electrode structure, choosing a target trimmed dimension, feeding forward the first dimension and the target trimmed dimension to ...

09/29/05 - 20050214958 - Electron beam apparatus, a device manufacturing method using the same apparatus, a pattern evaluation method, a device manufacturing method using the same method, and a resist pattern or processed wafer evaluation method
Provided is an electron beam apparatus comprising: an electron beam emitter (32) having an electron gun (30), said electron gun (30) disposed along an optical axis (23) and operable to emit a plurality of off-axis electron beams along a direction defined by a certain angle with respect to the optical ...

09/29/05 - 20050214957 - Method for manufacturing a transmitting optical sub-assembly with a thermo-electric cooler therein
The present invention relates to an optical transceiver that installs an optical transmitting assembly and an optical receiving assembly both are compact, inexpensive, and capable of operating at a high speed. The optical transmitting assembly of the present invention provides the metal bottom that installs the thermoelectric cooler thereon and ...

09/29/05 - 20050214956 - High throughput measurement of via defects in interconnects
Heat is applied to a conductive structure that includes one or more vias, and the temperature at or near the point of heat application is measured. The measured temperature indicates the integrity or the defectiveness of various features (e.g. vias and/or traces) in the conductive structure, near the point of ...

09/22/05 - 20050208685 - Periodic patterns and technique to control misalignment
A method and system to measure misalignment error between two overlying or interlaced periodic structures are proposed. The overlying, or interlaced periodic structures are illuminated by incident radiation, and the diffracted radiation of the incident radiation by the overlying or interlaced periodic structures are detected to provide an output signal. ...

09/22/05 - 20050208684 - Manufacturing method of semiconductor device
In a trial production process from a design process to an actual manufacturing process of semiconductor devices, a pre-process of a pad matrix wafer with simpler configuration than a prototype wafer is completed before a pre-process of the prototype wafer is completed, and data of conditions and evaluations to be ...

09/22/05 - 20050208683 - [method of correcting lithographic process and method of forming overlay mark]
A method of correcting a lithographic process is provided. A physical vapor deposition process (PVD) is performed to deposit a film on a wafer. The asymmetrical deposition of the film on the sidewalls of an opening is related to the change of target consumption in the PVD process. Therefore, the ...

09/08/05 - 20050196881 - Method for analyzing metal element on surface of wafer
Various kinds of metal elements existing on the surface of a wafer are analyzed with higher sensitivity. A high concentration HF solution is dropped onto a surface of a wafer. By providing the droplets of high concentration HF solution, the native oxide film on the surface of the wafer is ...

09/08/05 - 20050196880 - High resolution cross-sectioning of polysilicon features with a dual beam tool
A method for high resolution cross sectioning of polysilicon features with a dual electron (E) beam and focused ion beam. The method comprises consecutive steps of encapsulating the polysilicon features of interest with a metal coating, followed by ion beam cross sectioning of the metal encapsulated polysilicon features, followed by ...

09/01/05 - 20050191772 - Manufacturing method of semiconductor device
In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern ...

09/01/05 - 20050191771 - Ultrafast laser direct writing method for modifying existing microstructures on a submicron scale
A method for pre-calibration of a laser micro-machining system to achieve alignment tolerances greater than the diffraction limit of an illumination wavelength. A blank is mounted in the system, such that the beam spot is incident on its top surface. Two marks are ablated in the blank. The centers of ...

09/01/05 - 20050191770 - Flip chip semiconductor die internal signal access system and method
A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive ...

08/25/05 - 20050186691 - Method of determining a flatness of an electronic device substrate, method of producing the substrate, method of producing a mask blank, method of producing a transfer mask, polishing method, electronic device substrate, mask blank, transfer mask, and pol
A flatness of a substrate is determined to achieve a desired flatness of a mask blank by predicting the variation in flatness resulting from a film stress of a thin film formed on the substrate. The flatness is adjusted by measuring the flatness of the substrate as a measured flatness, ...

08/25/05 - 20050186690 - Method for improving semiconductor wafer test accuracy
A method for improving the accuracy of electrical test results of semiconductor wafers is described. The method introduces a non-contacting physical cleaning process prior to testing. The cleaning process removes micro-contamination on circuit contact pads that has been introduced during semiconductor wafer processing. This results in more accurate electrical probing ...

08/25/05 - 20050186689 - Method and structure for determining thermal cycle reliability
A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure ...

08/18/05 - 20050181525 - Method of fabricating board having periodically poled region
A polarization inverting region is formed by using a board comprising a single crystal of lithium tatalate of a stoichiometric composition or near to the stoichiometric composition and applying a direct current electric field having an electric field intensity equal to or lower than 5 [kV/mm] for 1 [second] or ...

08/18/05 - 20050181524 - Matching dose and energy of multiple ion implanters
A method that is sensitive to lattice damage (also called “primary method”) is combined with an additional method that independently measures one of two parameters to which the primary method is sensitive namely dose and energy. In some embodiments, the additional method is sensitive to dose, and in two such ...

08/11/05 - 20050176159 - Method for inspecting a wafer and apparatus for inspecting a wafer
Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing ...

08/04/05 - 20050170535 - Calibration standards for dopants/impurities in silicon and preparation method
A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each dopant or impurity to be quantified. On each calibration ...

07/28/05 - 20050164415 - Method and device for testing semiconductor laser
In testing a distributed feedback semiconductor laser with a grating having a phase shift part, a spectrum of the distributed feedback semiconductor laser is measured. A difference between an intensity of a side mode at a high-frequency-wave side of a main mode and an intensity of a side mode at ...

07/21/05 - 20050158887 - Yield based, in-line defect sampling method
A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The ...

07/14/05 - 20050153466 - Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof
A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of ...

07/14/05 - 20050153465 - Fabrication method of semiconductor integrated circuit device
A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test ...

07/07/05 - 20050148104 - Process controls for improved wafer uniformity using integrated or standalone metrology
A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map ...

06/30/05 - 20050142672 -