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Synchronizing The Sampling Time Of Digital Data

Synchronizing The Sampling Time Of Digital Data patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Pulse Or Digital Communications


Synchronizers > Synchronizing The Sampling Time Of Digital Data



Receivers and semiconductor systems including the same
12/18/14 - 20140369453 - The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the...

Digital receivers
12/18/14 - 20140369454 - A method for processing a received digital signal includes generating a clock signal used for sampling the received signal by comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal to maximize the vertical eye opening of the signal at...

Using multiple oscillators across a sub-network for improved holdover
11/27/14 - 20140348278 - A method and system are provided for improving maintenance of timing information when a node enters holdover due to a lost connection between a sub-network and a reference clock. Each node within the sub-network sends information concerning the drift of its local oscillator to a single node, and the single...

Digital signal up-converting apparatus and related digital signal up-converting method
11/27/14 - 20140348279 - A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to...

Methods and systems for clocking a physical layer interface
10/23/14 - 20140314190 - A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized...

Apparatus and method for detection of time tracking failure
09/18/14 - 20140270024 - According to an example embodiment of this application, a method may include calculating a timing offset estimate based on a received reference signal; accumulating consecutive timing offset estimates to generate a cumulative timing offset estimate; comparing the cumulative timing offset estimate against a threshold; and determining whether a time tracking...

Communication system with charge pump mechanism and method of operation thereof
09/18/14 - 20140270025 - A method of operation of a wireless communication system includes: synthesizing an incoming clock reference by differentiating an even cycle signal and an odd cycle signal; commutating a pair of resistors (R1, R2) based on the even cycle signal and the odd cycle signal; and controlling an amplifier output by...

Multi-wire single-ended push-pull link with data symbol transition based clocking
09/18/14 - 20140270026 - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is...

Protection control apparatus
09/18/14 - 20140270027 - A protection control apparatus includes a control-signal output circuit configured to generate a sampling signal in synchronization with a 1PPS signal and output, as a control signal, data numbers cyclically counted up every time the sampling signal is generated and the sampling signal and a data output unit configured to...

Dithering circuit for serial data transmission
09/11/14 - 20140254731 - A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system...

Receiver and methods for calibration thereof
07/31/14 - 20140211896 - There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely...

Signal processing circuit and signal processing method
07/10/14 - 20140192938 - A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with...

Alignment of non-synchronous data streams
07/10/14 - 20140192939 - An apparatus for aligning non-synchronous input data streams received in the apparatus, the apparatus comprising an analogue to digital converter arrangement for digitising the data streams into a plurality of sequences of samples; and a synchronisation processing arrangement for generating alignment pulses for each sequence of the plurality of sequences...

Communication channel calibration for drift conditions
07/10/14 - 20140192940 - A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link...

Communication system including multiple receiving antennas and time tracking method thereof
06/19/14 - 20140169513 - A tracking method and apparatus of a communication system to prevent a timing difference and bit error rate performance degradation caused by unstable characteristics of a plurality of circuit devices are provided. The tracking method and apparatus include sampling signals received at receiving antennas, tracking sample values resulting from the...

Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability
05/15/14 - 20140133614 - The technique uses the free-running or ‘slave’ mode of these serial receivers in which the receiver does not lock to the incoming data. To date, this mode has been used for oversampling but not for sampling at the actual data rate with a recovered clock in order obtain eye pattern...

Estimation of sample clock frequency offset based on error vector magnitude
05/08/14 - 20140126676 - A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/TS′ of a receiver and an intended sample clock rate 1/TS. The receiver captures samples of a received baseband signal at the rate 1/TS′, operates on the captured...

Method and apparatus for sampling a serial data stream using a clock signal, based on a counter pattern
03/06/14 - 20140064421 - In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency...

Apparatus & methods for symbol timing error detection, tracking and correction
02/20/14 - 20140050288 - Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant...

Techniques for varying a periodic signal based on changes in a data rate
02/06/14 - 20140037033 - A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on...

Method and device for establishing router neighbor
12/19/13 - 20130336434 - Embodiments of the present invention relate to a method and a device for establishing a router neighbor. The method includes: obtaining a first discovery protocol Hello message sent by a neighbor router, where the first Hello message carries identification information and priority information of the neighbor router; and determining whether...

Data recovery circuit and operation method thereof
10/03/13 - 20130259177 - In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality...

Apparatus, system, and method for timing recovery
09/19/13 - 20130243138 - Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to...

System and method for determining a time for safely sampling a signal of a clock domain
08/22/13 - 20130216013 - A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging...

Phase control block for managing multiple clock domains in systems with frequency offsets
08/01/13 - 20130195234 - A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock...

Method and apparatus for regulating the sampling phase
04/25/13 - 20130101075 - Embodiments of the invention relate to methods and circuits for controlling the sampling phase of a signal that is to be regenerated by sampling, particularly a serial communication signal, having method steps or means for oversampling the signal in order to ascertain samples of the signal during predetermined sampling phases,...

Sampling phase selection method for a stream of data bits
03/07/13 - 20130058445 - The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data...

Implied clock
01/10/13 - 20130010908 - Systems and methods providing clocking between various components or sub-components are shown. Embodiments implement an implied clock technique which reduces the number of signal lines, signaling overhead required for an encoded clock signal, and/or and power consumption for a high speed communication link. In accordance with embodiments efficient communication is...

Sampling clock selection module of serial data stream
10/25/12 - 20120269308 - A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal....

System and method to overcome wander accumulation to achieve precision clock distribution over large networks
10/18/12 - 20120263264 - A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the...

System for adaptive sampled medical signal interpolative reconstruction for use in patient monitoring
10/11/12 - 20120257698 - A patient medical signal processing system adaptively reconstructs a medical signal sampled using a varying sampling rate. The system includes an input processor and a signal processor. The input processor receives first data and second data. The first data represents a first portion of a medical signal derived by sampling...

Data recovery apparatus and method by using over-sampling
07/05/12 - 20120170697 - A data recovery apparatus and method by using over-sampling are provided. The data recovery apparatus by using over-sampling includes an over-sampling module, a data regeneration unit, a phase alignment unit, a phase decision module, and an output data correction unit. The over-sampling module samples serial data according to a clock...

Adaptive frequency synthesis for a serial data interface
06/21/12 - 20120155586 - Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to...

Systems and methods for improved timing recovery
06/21/12 - 20120155587 - Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a...

Oversampling circuit, serial communication apparatus and oversampling method
04/26/12 - 20120099688 - An oversampling circuit includes: a generation unit configured to generate multiphase serial data by delaying serial data by a predetermined time; and an oversampling unit configured to oversample the multiphase serial data by using multiphase clocks, wherein a phase difference of the multiphase serial data is set to be a...

Glitch-free oversampling clock and data recovery
04/19/12 - 20120093273 - A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector...

Clock data recovery circuit and clock data recovery method
02/16/12 - 20120039426 - A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and...

Multi-channel sample rate converter
02/09/12 - 20120033771 - A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding...

Slicing level and sampling phase adaptation circuitry for data recovery systems
01/26/12 - 20120020444 - The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating...

Wireless sensor synchronization methods
01/26/12 - 20120020445 - A method of sampling data includes providing a plurality of wireless nodes, wherein each of the wireless nodes includes a receiver, a real time clock and a counter. Ticks of the real time clock are counted by the counter. The method also includes broadcasting a common beacon for receipt by...

Phase detection method and circuit
01/12/12 - 20120008723 - Phase detection methods are provided. According to a first embodiment, a signal is sampled in order to obtain an amplitude sample. Then an absolute value of the difference of the amplitude sample minus an average of amplitude samples is calculated. According to a second embodiment, the signal is sampled at...

Apparatus and method for clock and data recovery
08/11/11 - 20110194659 - Apparatus and methods for clock and data recovery are disclosed. In one embodiment, a clock and data recovery system includes a sampler, a deserializer, a phase detector and a frequency detector. The sampler may be configured to sample a serial data stream to produce data samples and transition samples. The...

Apparatus and method for rotational frequency detection
08/11/11 - 20110194660 - Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of...

Digital audio processing system and method
08/11/11 - 20110194661 - A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase...

Method for clock and data recovery
07/14/11 - 20110170644 - An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one...

Method and apparatus for estimating symbol timing
06/23/11 - 20110150157 - Provided is a symbol timing estimating apparatus and method that may generate at least one sampled preamble signal by sampling a preamble signal with changing a phase of the preamble signal based on a symbol speed, calculate a power value of each of the at least one sampled preamble signal,...

Radio communication apparatus and method
06/23/11 - 20110150158 - A radio communication apparatus includes a clock reproducer unit which repetitively detects a symbol timing from a Nyquist point in detection-result data. A symbol generator unit controllably generates or non-generates a to-be-transmitted symbol or symbols at every symbol timing detected by the clock reproducer unit, converts the to-be-transmitted symbol or...

Apparatus and methods for estimating and compensating sampling clock offset
05/26/11 - 20110122979 - An apparatus for sampling clock recovery (SCO) and methods for estimating and compensating SCO are provided. The apparatus comprises a symbol timing adjustment module for shifting forward or backward symbol timing of the transmitted OFDM symbols; a discrete Fourier transform (DFT) processor for performing DFT to an output from the...

Method and apparatus for deskewing data transmissions
04/28/11 - 20110096882 - The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilising a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip...

Method and apparatus for bandpass digital to analog converter
03/31/11 - 20110075780 - Systems and methods for providing a mechanism by which digital signals can be converted to analog signals with an efficient structure that reduces the number of filters required by providing a mechanism for cancelling images that would otherwise be generated. By adjusting three parameters in the system, a selection can...

Clock recovery circuit and data recovery circuit
03/17/11 - 20110064176 - A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial...

Method for carrying out bidirectional communications
11/25/10 - 20100296614 - In a method for carrying out bidirectional communications between a first electronic unit and a second electronic unit, a clock signal and an input signal synchronized with the clock signal are transmitted from the first electronic unit to the second electronic unit, and the second electronic unit transmits a response...

Method and system for bit detection and synchronization
10/21/10 - 20100266079 - A bit synchronization method is proposed. The method includes buffering a plurality of samples from a signal stream, scanning the buffered samples for transitions and updating a zero-crossing histogram buffer upon detection of the transitions. The method further includes detecting at least two peaks simultaneously from the updated zero-crossing histogram...

Edge-based sampler offset correction
09/02/10 - 20100220828 - Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point...

High availability clock synchronization and distribution for mobile backhaul networks
07/08/10 - 20100172453 - Fully redundant clock systems are provided on network nodes coupled by redundant multisegment psuedowires (MSPWs) within an internet-protocol (IP)-based mobile backhaul network. The primary clock system includes a primary master clock on a first node and a primary slave clock on a second node coupled via a primary MSPW, while...

Multirate resampling and filtering system and method
06/24/10 - 20100158178 - A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient...

Symbol timing acquisition using early-late interpolation
06/24/10 - 20100158179 - Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be interpolated to generate an early...

Methods of processing a wireless communication signal, wireless communication synchronization methods, and a radio frequency ideentification device communication method
06/10/10 - 20100142665 - Wireless communications devices, methods of processing a wireless communication signal, wireless communication synchronization methods and a radio frequency identification device communication method are described. In one aspect, a wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and...

Reception apparatus
05/13/10 - 20100119023 - In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and...

Apparatus and method for digital up converting in a mobile communication system
04/29/10 - 20100104055 - An apparatus and method for digital up converting in a mobile communication system are provided. The apparatus includes a Selectable Input Logic (SIL), a Scalable Clock Distribution Logic (SCDL), a filter logic, and a mixer logic. The SIL performs decimation at a decimation rate. The SCDL controls a clock frequency....

Sample rate converter
04/15/10 - 20100091922 - A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency. The sample rate converter comprises: a buffer, for storing data samples received from said first signal; a first loop circuit,...

Circuit for a radio system, use and method for operation
04/15/10 - 20100091923 - A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock...

System and method for multilaterating a position of a target using mobile remote receiving units
04/15/10 - 20100091924 - A method of multilaterating the position of a target, including the steps of deploying a plurality of time synchronized receiving units in a network that allows the receiving units to communicate with a central processor; receiving a target signal from the target at each receiving unit; determining a time of...

Recovering data from an oversampled bit stream with a plesiochronous receiver
03/04/10 - 20100054382 - Data is recovered in a plesiochronous receiver from an oversampled bit stream. In one example, a bit stream is received and oversampled in blocks to produce successive sets of samples, each set of samples representing a same number of bits. Transitions are found in the samples. Positions of the found...

Adaptive clock and equalization control systems and methods for data receivers in communications systems
02/25/10 - 20100046683 - Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods...

Bust-mode clock and data recovery circuit using phase selecting technology
02/18/10 - 20100040182 - A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked...

Method and computer program for identifying a transition in a phase-shift keying or frequency-shift keying signal
01/14/10 - 20100008457 - A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal...

Tracker circuit and method for automated test equipment systems
01/07/10 - 20100002819 - A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines...

Method and apparatus for generating clock signals for quadrature sampling
11/12/09 - 20090279650 - The present invention provides a quadrature-sampling clock signals generation method and apparatus for use in a receiver The apparatus firstly obtains an initial clock signal whose frequency is lower than twice of the carrier frequency of an input signal, then divides the frequency of the initial clock signal by two...

Clock and/or data recovery
10/08/09 - 20090252265 - Embodiments for clock and/or data recovery may comprise two samplers to sample a relatively small number of distinct data sample phase locations of a data pulse relative to an estimate of the location of a center of the data pulse....

Mechanism for constructing an oversampled waveform for a set of signals received by a receiver
09/24/09 - 20090238318 - A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of...