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Pulse Or Digital Communications > Synchronizers > Synchronizing The Sampling Time Of Digital Data Synchronizing The Sampling Time Of Digital DataSynchronizing The Sampling Time Of Digital Data patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/22/07 - 20070268990 - Isochronous synchronizer Circuitry for synchronizing communications between clock environments wherein a change of state is transmitted from a first clock environment to a second clock environment, the first clock environment being timed by a first clock signal and the second clock environment being timed by a second clock signal, the first and ... 11/08/07 - 20070258552 - Data receiver with clock recovery circuit A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for ... 10/25/07 - 20070248201 - Data recovery apparatus and method for reproducing recovery data A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N steps in a period T of ... 10/11/07 - 20070237274 - Synchronizing to symbols received via wireless communications channel Synchronization techniques for reducing the effects of time dispersive wireless communications channels are presented. A synchronization technique for communications over a time dispersive wireless channel includes receiving a signal having at least identical first and second symbols, and calculating a metric for each sampling time by correlating respective samples of ... 09/27/07 - 20070223634 - Method and apparatus for high resolution measurement of signal timing A phase measurement system for measuring a phase difference between an input signal and a reference signal, comprises: a phase comparator having a first input receiving a first sample of the input signal and a second sample of the input signal and having a second input receiving a clock derived ... 09/20/07 - 20070217560 - Apparatus and method for sample rate conversion in a software defined radio communication system A method for converting a sample rate in a Software Defined Radio (SDR) communication system is provided. The method includes setting a sampling frequency range depending on a maximum sampling frequency and a minimum sampling frequency so as to enable support of a plurality of sample rates; if a required ... 09/20/07 - 20070217559 - Signaling system with adaptive timing calibration An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sampling circuit samples a data signal in response to the ... 09/20/07 - 20070217558 - Method and apparatus for improving linearity in clock and data recovery systems Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal. ... 08/02/07 - 20070177699 - Interpolation processing for enhanced signal acquisition The present invention relates to methods and systems for enhanced signal acquisition through cross-ambiguity function (CAF) interpolation. In one aspect, the present invention provides methods and systems for CAF interpolation. In an embodiment, a first CAF generated using a low input sampling rate (e.g., 1 sample/chip) is interpolated to generate ... 07/26/07 - 20070172006 - Method and circuit for sampling data A method for sampling data is disclosed. The method includes providing a first data and a second data, detecting a phase of the first data by a first clock, and sampling the second data by an inverted signal of the first clock. ... 07/05/07 - 20070153947 - Method and computer program for identifying a transition in a phase-shift keying or frequency-shift keying signal The present invention is a method and computer program for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals. The method of the present invention is implemented via the computer program. With respect to phase-shift keying signals, the method broadly comprises the steps of: selecting ... 06/28/07 - 20070147567 - Star receiver burst processing Architecture for processing a record of burst information in a transmission link. A waveform sampler samples a received waveform containing a record of symbols imposed on a carrier signal. Symbol phase of the record symbols is determined utilizing one or more metrics. Any residual carrier error is corrected, and the ... 06/28/07 - 20070147566 - Clock and data recovery with extended integration cycles Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, ... 06/28/07 - 20070147564 - Phase interpolator A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes ... 06/21/07 - 20070140395 - Method of symbol timing synchronization in communication systems Symbol timing synchronization in OFDM communication systems where multiple wireless terminals communicate with a single base station is described. Base station transmitter and receiver symbol timing is fixed. Each wireless terminal operates to independently adjust its transmitter timing. Transmitter timing synchronization at the wireless terminal is slaved to the terminal's ... 06/21/07 - 20070140394 - Generating a clock crossing signal based on clock ratios A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal with a first frequency and the second clock domain includes a second clock signal ... 06/07/07 - 20070127612 - Apparatus and method for retiming data using phase-interpolated clock signal A data recovering apparatus and method using an interpolated clock signal are provided. The data recovering apparatus comprises a first phase alignment unit extracting from multi-phase clock signals a first clock having an edge most closely corresponding to the center of each bit of input data, a second phase alignment ... 06/07/07 - 20070127611 - Non-coherent synchronous direct-conversion receiving apparatus for compensating frequency offset A non-coherent synchronous direct-conversion receiving apparatus is provided. The apparatus includes a RF receiving unit, an I/Q ADC unit, and a digital signal processing unit for analyzing the digital signal received from the I/Q ADC unit to adjust a bandwidth of a variable receiving filtering unit according to the analyzing ... 05/24/07 - 20070116167 - Apparatus and method for adjusting filter frequency in relation to sampling frequency A self-tuning filter is disclosed. The self-tuning filter includes a digital clocking signal and an input coupled to the digital clocking signal, whereby the input reads a value incident on the input when the digital clocking signal changes to a predetermined state. A clock-tunable filter is, furthermore, coupled to the ... 05/17/07 - 20070110204 - Sampling circuit apparatus and method A system, method and apparatus for sampling an electromagnetic signal is provided. In one embodiment of the present invention, data is obtained from an electromagnetic signal by sampling the received signal and demodulating the signal without mixing the signal with a second electromagnetic signal. One feature of the present invention ... 05/17/07 - 20070110203 - Sampling frequency conversion apparatus and signal switching apparatus A sampling frequency conversion apparatus having sampling frequency conversion circuits for a plurality of channels includes a detector detecting phase information of digital signals inputted to the conversion circuit for each channel, and an input section inputting setting information for the conversion circuits for two or more channels to be ... 05/03/07 - 20070098126 - Determination of a jitter property of a signal Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with ... 05/03/07 - 20070098125 - Methods and apparatus for determining timing in a wireless communication system Methods and apparatus for setting timing of sampling of one or more symbols. The disclosed methods account for at least three types of effective interference (EI) and are used to set the timing of a sampling window for sampling received symbols. The methods includes setting timing based on determining an ... 04/26/07 - 20070092047 - Closed loop power normalized timing recovery for 8 vsb modulated signals A receiver timing error recovery loop expands the bandwidth of a received signal and determines the timing error based on the bandwidth expanded received signal. ... 03/29/07 - 20070071153 - Adaptive reception techniques for over-sampled receivers An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount ... 03/29/07 - 20070071152 - Method and circuit for timing recovery A circuit and method for timing recovery. The circuit for timing recovery comprises an converter, a timing recovery controller, and a initial phase generator. The converter converts an input signal to sample data with a sampling signal. The timing recovery controller is coupled to the converter, and determines the sampling ... 03/22/07 - 20070064850 - Data reproduction circuit This is a data reproduction circuit for receiving data and reproducing the data and its clock which comprises an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a ... 03/22/07 - 20070064849 - Pilot tracking module operable to adjust interpolator sample timing within a handheld audio system The present invention provides a method to adjustably sample pilot tracking module within a handheld audio system that includes both an error sensing module and a feedback module that track timing errors in sampling a first digitized signal having a first data rate to produce a second digitized signal having ... 03/22/07 - 20070064848 - Clock recovery A method and apparatus of recovering a clock signal from an input data signal consistent with certain embodiments, where the clock signal has a clock cycle equal to one data bit period, involves identifying an earliest transition time position in a sequence of data signal transitions; identifying a latest transition ... 03/22/07 - 20070064847 - Dsp-based data recovery A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge ... 03/15/07 - 20070058765 - Dynamic input setup/hold time improvement architecture A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through ... 03/15/07 - 20070058764 - Phase detection device and method thereof A phase detection device comprising an analog-digital converter, an interpolator, and a determining unit. The analog-digital converter receives an analog signal and converts the analog signal to a digital signal according to a plurality of digital sampling points. The interpolator generates a plurality of interpolation points according to a predetermined ... 03/15/07 - 20070058763 - Device with adaptive equalizer A device (200) with an adaptive equalizer (210) includes an adaption scheme performed in the synchronous domain. The equalizer coefficient update scheme is based on a correlation of an error sequence (delta k) derived from the equalized sequence transposed to the synchronous domain (Ek) and a synchronous and delayed version ... 03/08/07 - 20070053473 - Faster fine timing operation in multi-carrier system There is provided a method, system and receiver for receiving data over a communication link. An energy of said signal in respect of an estimated guard interval position of said signal is defined. Based on said energy, a position for a time domain to a FFT window is selected. Trial ... 03/01/07 - 20070047683 - Clock and data recovery circuit having wide phase margin A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of ... 02/01/07 - 20070025485 - Metric sampling method and system An arbitrary metric stream is processed initially at an interim sampling rate to derive a plurality of samples. The samples are analyzed preferably to determine an estimate of the effective bandwidth of the metric stream. As a result of the analysis, an improved sampling rate is determined and adopted for ... 02/01/07 - 20070025484 - Apparatus and method for compensating the drift of a local clock used as sampling frequency The invention relates to an apparatus and a method for data acquisition, the apparatus being characterized in that it comprises an analog/digital converter (510) sampling at an imperfect frequency FE provided by a local clock (100) data acquired by a sensor (500) thus providing a series of sampled and dated ... 02/01/07 - 20070025483 - Methods and apparatus for clock synchronization and data recovery in a receiver Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval ... 02/01/07 - 20070025482 - Flexible sampling-rate encoder A method for implementing a flexible sampling-rate encoder, comprising the steps of (A) sampling an input signal at a regular time-interval to produce sampled data, (B) generating a pseudo-random bit sequence having a plurality of bits, wherein each bit corresponds to a different sampling time, (C) encoding a first set ... 01/25/07 - 20070019768 - Sampling device and sampling method A sampling device for repetitive sampling a measured signal includes a measured signal sampling circuit for sampling the measured signal, a reference signal generating circuit for generating a reference signal having a predetermined frequency, a sampling circuit for sampling the reference signal generated by the reference signal generating circuit, and ... 01/25/07 - 20070019767 - Method and system for synchronizing a base station of a wireless communication system and a subscriber communication equipment The method for synchronising a base station of a wireless communication system and a subscriber communication equipment located in the coverage area of the base station comprises the steps of compensating a sampling frequency offset in the subscriber equipment by interpolating input and/or output signals of a radio frequency part ... 01/18/07 - 20070014389 - Wireless receiving device having low power consumption and excellent reception performance The A/D converter changes sampling timing of a received signal in a synchronization acquisition mode and a synchronization tracking mode. The A/D converter generates an internal clock of a sampling frequency eight times a symbol rate under the control of the clock control unit in the synchronization acquisition mode. On ... 01/11/07 - 20070009073 - Data sampling circuit and semiconductor integrated circuit A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a ... 01/04/07 - 20070002990 - Data recovery using data eye tracking A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital ... 01/04/07 - 20070002989 - Method and system for link jitter compensation including a fast data recovery circuit A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal ... 12/28/06 - 20060291602 - Communications link clock recovery Apparatus and systems, as well as methods and articles, may operate to receive a data signal from a transmitter at a selected channel included in a plurality of receiver channels, derive clock frequency deviation information from the data signal, receive an operational mode indication, and communicate the clock frequency deviation ... 12/21/06 - 20060285616 - Method and apparatus for correcting symbol timing The present invention provides a method and apparatus for correcting symbol timing of a receiver. The receiver receives a signal transmitted by a transmitter based on a symbol period. The method includes: sampling the signal with a sampling period to generate N sampled data in series, wherein the sampling period ... 12/14/06 - 20060280272 - Data-level clock recovery A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a ... 12/14/06 - 20060280271 - Sampling rate conversion apparatus, encoding apparatus decoding apparatus and methods thereof A coding apparatus capable of reducing a circuit scale and also reducing the amount of coding processing calculation is disclosed. In this apparatus, frequency domain conversion section (103) performs a frequency analysis of the signal sampled at a sampling rate Fx with an analysis length of 2·Na and calculates first ... 12/07/06 - 20060274872 - Waveform shaping method, waveform shaping device, electronic device, waveform shaping program and recording medium A sampling section (102) is provided for generating a sampling signal (103) by sampling an input signal (101) using a sampling clock (106) which is faster than a data speed of the input signal (101). A waveform shaping section (104) is provided for I) processing (e.g. inverting a pulse) the ... 11/23/06 - 20060262890 - Asynchronous data reception without precision timing reference A method of asynchronous data reception, the method comprising: receiving a plurality of calibration bits having a bit rate; sampling the received calibration bits at a sampling rate, the sampling rate being in excess of the bit rate; determining, responsive to the sampling, respective indexes for valuing each of the ... 11/23/06 - 20060262889 - Synchronous undersampling for high-frequency voltage and current measurements A power source may generate signals (RF or microwave), when driven by a drive signal from a controller. A sensor may measure the voltage and current of the signals generated by the power source, and may generate sensor signals representative of the measured voltage and current. A sampler may be ... 11/23/06 - 20060262888 - Methods and apparatus with logic to determine a relative change relationship between modem and frame clocks Methods and apparatus to determine a relative change relationship between modem and frame clocks are generally described herein. Other embodiments may be described and claimed. ... 11/02/06 - 20060245528 - Method for selecting optimum sampling parameters for a plurality of data receivers having at least one sampling parameter in common Eye diagrams are made for signals on each channel in a group thereof. Outlying signals that do not exhibit overlap for a sampling parameter that is to be common for all channels may be ignored and a warning given. Selected, normalized eye openings are used to discover optimum sampling parameters ... 10/19/06 - 20060233291 - Partial response receiver with clock data recovery In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second ... 10/12/06 - 20060227917 - High-speed serial data transceiver and related methods A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system ... 10/12/06 - 20060227916 - Data recovery method, data recovery circuit, data transmitting/receiving apparatus and information processing apparatus Serially transferred data is over sampled with a multiphase clock signal generated as a result of shifting a predetermined frequency clock signal by a predetermined phase each, to obtain over sampling data; generating clock patterns, having mutually different phase states according to a data phase state of the over sampling ... 10/12/06 - 20060227915 - Eye center determination system and method A system and method for bit eye center determination is provided. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively offsets the selected samples based on state criteria and the number of transitions in each set of samples, accumulates the ... 10/12/06 - 20060227914 - Clock data recovery circuit with circuit loop disablement A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the ... 10/05/06 - 20060222131 - Method for sampling reverse data and a reverse data sampling circuit for performing the same A method for sampling reverse data and a reverse data sampling circuit for performing the same are provided. The reverse data sampling method of a host interface device includes generating a multi-phase clock; sampling clocks corresponding to respective phases of the multi-phase clock at a transition of a reverse data ... 10/05/06 - 20060222130 - Methods of controlling tracker bandwidth in wireless communication systems In a method of tracking on-time errors in a wireless communication system, first and second metrics may be produced from accumulated signal samples of a received data frame, and a sum of, and a difference between, the first and second metrics may be calculated. The calculated difference and sum values ... 10/05/06 - 20060222129 - High-speed serial transceiver with sub-nominal rate operating mode A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured ... 10/05/06 - 20060222128 - Analog signals sampler providing digital representation thereof A method and a corresponding system for sampling at least one analog signal (54) and providing digital representation thereof (59). Disclosed an analog circuit (51) featuring high bandwidth, high gain, and low current consumption, wherein that analog circuit is implemented by low accuracy components. The analog circuit is integrated with ... 09/07/06 - 20060198481 - Apparatus and method for tracking a sampling clock of multi-carrier communication system An apparatus and a method for tracking a sampling clock of a multi-carrier communication system are disclosed, the apparatus including a data removal module, a phase estimation module, and a sampling clock offset computation module. The data removal module is for generating a plurality of first and second data removal ... 09/07/06 - 20060198480 - Method, article, and apparatus for a dynamic phase delay compensator An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a ... 08/31/06 - 20060193414 - Synchronization and data recovery device A synchronization and data recovery device (SuD) for clock-synchronized recovery of data bits in a data stream is provided, which is particularly suitable for improved backward identification of data in serial receiver interfaces of high-speed semiconductor memory modules and/or memory controller modules with a low data density. The SuD includes ... 08/31/06 - 20060193413 - Method of capturing data transferred in synchronization with a data strobe signal and data capture circuit performing same A method of capturing data that are transferred in synchronization with a data strobe signal. The method includes sampling a data strobe signal at a clock frequency higher than a data rate to detect a transition point of the data strobe signal (e.g., by generating and comparing a plurality of ... 08/24/06 - 20060188047 - Method and circuitry for extracting clock in clock data recovery system A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after ... 08/24/06 - 20060188046 - Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel A network device for determining an optimal sampling phase for source synchronous data received on a data communications channel. The network device includes a transmitter clock domain for providing a data pattern along with a synchronous free-running clock. The network device also includes a plurality of phases of a core ... 08/17/06 - 20060182213 - Data sampler for digital frequency/phase determination The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is ... 08/10/06 - 20060176991 - System for adjusting sampling timing of dll circuit, method therefor and transmitter-receiver used therefor An object of the present invention is to provide a DLL circuit adjustment system that can adjust the sampling timing of a DLL circuit without causing any increase of the number of interface signals or amount of coding overhead and any reduction of the data transfer efficiency. On a transmitter ... 07/20/06 - 20060159211 - Digital frequency/phase recovery circuit A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a multiplexer. The comparator with hysteresis receives the input signal and generates a comparison signal. The counter receives the comparison signal, calculates the pulse ... 07/06/06 - 20060146968 - Data communication device A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization ... 07/06/06 - 20060146967 - Keep-out asynchronous clock alignment scheme In some embodiments an apparatus may comprise a data circuit, a clock circuit to synchronize the data circuit; and a sampling circuit to sample a clock signal from a separate clock domain, the sampling circuit may control the clock circuit in response to the sampled clock signal and to delay ... 06/29/06 - 20060140318 - Amplitude monitor for high-speed signals A serial communication system includes a receiver that incorporates an amplitude monitor, which may be used to set and maintain appropriate termination-resistance values and transmit pre-emphasis and receive equalization settings. The amplitude monitor can note the presence or absence of input signals, as is required by some communication standards, such ... 06/08/06 - 20060120497 - Method for resampling at transmission and reception of a digital signal with digital band translation The invention relates to a method for resampling at transmission and reception of a digital signal with digital band translation. According to the invention, a resampling (25) is performed upon reception of a bandpass signal, whereby the signal is translated (4) to baseband with a configurable frequency and the resulting ... 06/08/06 - 20060120496 - Receiving apparatus A receiver apparatus having a demodulator circuit that demodulates transmitted serial data into parallel data by sampling the transmitted serial data on the basis of a first and a second clock signals having different numbers of clocks to be output in synchronization with a cycle of a transmitted clock includes ... 06/01/06 - 20060115034 - Newton's method-based timing recovery circuit A Newton's method-based timing recovery circuit includes a sampling clock generator, a sampler, an interpolator, a timing error detector for generator a timing error signal, a third delayer, a second subtractor, a rightward-bit-shifter, a multiplexer, a leftward-bit-shifter for leftward shifting a differential timing error signal, a fourth delayer, a first ... 05/25/06 - 20060109942 - Improvements to data recovery circuits using oversampling for best data sample selection An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means ... 05/11/06 - 20060098769 - Apparatus and method for controlling display state In a display state control apparatus for automatically changing the frequency and the phase of a sampling clock signal according to changes in the phase and frequency of an input signal, and in a display state control method therefor, an optimal display state is maintained by automatically changing the frequency ... 04/20/06 - 20060083339 - Parallel sampled multi-stage decimated digital loop filter for clock/data recovery The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase ... 03/16/06 - 20060056558 - Method and apparatus for adjusting phase of sampling frequency of adc A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; ... 03/02/06 - 20060045225 - Analog front end circuit with automatic sampling time generation system and method An automatic clock generation system is used for automatically outputting a sampling signal and a holding signal to an analog front end circuit and for sampling the analog signal. The clock generation system comprises a clock generator generating a plurality of clock signals and a comparing module. According to the ... 03/02/06 - 20060045224 - Methods and arrangements for link power reduction Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to ... 02/23/06 - 20060039515 - Method and apparatus for estimating sfo in digital receiver A method and apparatus for estimating a sampling frequency offset (SFO) in a digital receiver is disclosed. The method for estimating the SFO in the digital receiver to perform sampling synchronization includes the steps of: a) extracting a current scattered pilot contained in a single OFDM (Orthogonal Frequency Division Multiplexing) ... 02/23/06 - 20060039514 - Universal sampling rate converter in electronic devices and methods A method and apparatus for converting the sampling rate of digital signals including a decimating comprising a low pass filter (122) and a downsampler (124), wherein the input signal is decimated a number of times based on a ratio of an input sampling rate to an output sampling rate. The ... 02/23/06 - 20060039513 - Clock and data recovery systems and methods Methods of clock and data recovery (CDR) are provided. An exemplary method comprises extending the eye of the data stream by examining transitions of adjacent samples, detecting whether an island sample exists in each symbol according to the separation of the transitions, and altering the value of the neighboring samples ... 02/16/06 - 20060034406 - Apparatus for timing recovery and method thereof The present invention provides an apparatus for timing recovery and method thereof. The present invention includes the steps of obtaining a symbol sample value by sampling a received baseband signal with a symbol sample rate and by performing a front-end processing on the sampled signal in a digital area, finding ... 02/16/06 - 20060034405 - Method and apparatus for high-speed input sampling A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock ... 02/02/06 - 20060023821 - Resampler for a bit pump and method of resampling a signal associated therewith A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a ... 01/05/06 - 20060002498 - Clock recovery There is provided a Clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further ... 01/05/06 - 20060002497 - Phase adjustment method and circuit for dll-based serial data link transceivers A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second ... 12/29/05 - 20050286668 - Method for reducing a computational complexity in non-linear filter arrangements as well as corresponding filter arrangements A method for creating a form of a non-linear filter suitable for reducing a computational complexity is proposed. The filter is resolved into polyphase components in such a way that the polyphase components can be interchanged with a conversion of the sampling rate of a signal to be sent to ... 12/15/05 - 20050276365 - Multipath compensation for signal receivers This invention provides a signal synchronizer that is capable of minimizing the effects of multi-path reception. The signal synchronizer provides signal samples from a first signal source and a second signal source for generating an output signal. The signal synchronizer includes a memory for storing signal samples obtained from a ... 12/08/05 - 20050271175 - Minimum variance unbiased and moment estimators of carrier frequency offset in multi-carrier systems A class of non data-aided cyclic based robust estimators for frequency offset estimation of multi-carrier systems is disclosed. The use of sufficient statistics provides a minimum variance unbiased (MVU) estimate of the frequency offset under complete knowledge of timing offset error. The Neyman-Fisher factorization theorem and Rao-Blackwell-Lehmann-Scheffe theorem are used ... 11/24/05 - 20050259775 - Dynamic phase alignment methods and apparatus Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate ... 11/24/05 - 20050259774 - Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique sample voltage, unique sample timing, or a unique combination ... 11/17/05 - 20050254611 - Symbol timing search algorithm A system is described for establishing timing synchronism between a local receiver symbol clock and a transmitter symbol clock. A prescribed number of offset values are calculated for desired symbol timing range, the offset values being grouped substantially symmetrically about a central offset value. Each of the preselected offset values ... 11/10/05 - 20050249322 - Methods for terminal assisted coordinated radio serving and interference avoidance in ofdm mobile communication system Methods for coordinated radio serving and coordinated interference avoidance in a radio communication system employing multi-carrier techniques such as OFDM for the air interface communication between a network and a plurality of user terminals, the network comprising at least two base stations controlled by a radio network controller, the base ... 11/03/05 - 20050243956 - Apparatus and method for automated determination of sampling phase of an analog video signal A method and an apparatus provide extraction of data from an analog signal. The method includes deriving a data-location signal having amplitude transitions that identify a phase of amplitude transitions of the analog signal, and, in response to the data-location signal, selecting a sampling clock signal having a phase different ... 10/27/05 - 20050238126 - Multi rate clock data recovery based on multi sampling technique A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the ... 10/06/05 - 20050220237 - Method and arrangement for sampling In the proposed method of sampling data that are related to a clock signal, a three test samples are taken from the same data at positions in time spaced from each other by fixed delays by shifting the clock signal in time with respect to the data until the test ... 10/06/05 - 20050220236 - Data receiver with servo controlled delayed clock A Time Ruler is used to periodically discover the Unit Interval (UI) for a data signal, which does not change abruptly, but drifts with time and various parameters. The same Time Ruler can also be used at other times to determine where in the Measured UI the data is being ... 09/22/05 - 20050207521 - Recovery from errors in a data processing apparatus A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic ... 09/22/05 - 20050207520 - High-speed serial link clock and data recovery A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate ... 09/15/05 - 20050201503 - Clock control of transmission signal processing devices in mobile radiotelephone terminals To support a plurality of different mobile radio standards in mobile radio terminal devices using a single system oscillator, a sampling rate converter converts the sampling rates from an input rate to an output rate and additionally outputs control information which is suitable for operating signal processing components. The components ... 09/08/05 - 20050195929 - Sampling frequency conversion apparatus A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, and comprises storage means 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading ... 09/01/05 - 20050190874 - Variable phase bit sampling with minimized synchronization loss Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response ... 08/18/05 - 20050180537 - System and method for clock rate determination Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second ... 08/11/05 - 20050175133 - Method and circuit arrangement for synchronizing a function unit with a predetermined clock frequency A receiver is synchronized with a first clock frequency or signal of a transmitter for the proper reception of transmitted and received signals, such as data carrying signals (DS). The first clock frequency is for example a carrier frequency. A local oscillator generates a second clock frequency or signal in ... 08/04/05 - 20050169415 - Timing error recovery system A timing error recovery system includes a phase locked loop that receives a continuous time input signal, samples the input signal at a sampling rate and generates a voltage control signal. A statistical estimator, such as a maximum a posteriori estimator, compares the voltage control signal with an expected error ... 07/21/05 - 20050157827 - Method and circuit for writing double data rate (ddr) sampled data in a memory device A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and ... 06/30/05 - 20050141660 - Symbol timing recovery and broadcast receiver using the same A timing recovery for recovering a symbol clock using received data is provided. The timing recovery estimates a timing offset in such a way that dispersion constants of received symbols are minimized. Since the dispersion constants do not totally depend on a specific portion of a received signal spectrum, deterioration ... 06/23/05 - 20050135527 - Data recovery method and data recovery circuit (b) extracting f1/f2 bits on average from the oversampled data; and (c) recovering the extracted bits to restore the received data. ... ### FreshPatents.com Support - Terms & Conditions |