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Pulse Or Digital Communications > Synchronizers SynchronizersSynchronizers patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070258551 - System and method for performing on-chip synchronization of system signals utilizing off-chip harmonic signal Aspects of the invention provide a method and system for reducing signal distortion within an on-chip transceiver module. In response to receipt of a signal bearing at least one external clock frequency, at least one harmonic signal of the signal bearing the at least one external clock frequency may be ... 10/18/07 - 20070242786 - Method of supporting operation of sleep mode in a wideband radio access system A method of supporting operation of sleep mode in a wideband radio access system is disclosed. More specifically, a mobile subscriber station (MSS) which determines a frame offset information for synchronizing listening windows of at least one MSS that is in sleep mode, and transmits the determined framed offset information ... 10/04/07 - 20070230645 - Metastability injector for a circuit description During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of ... 09/27/07 - 20070223633 - Non-overlapping multi-stage clock generator system A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also ... 09/27/07 - 20070223632 - System and method for signal alignment when communicating signals A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices. The alignment logic may operate to adjust one or more communicated signals, ... 09/20/07 - 20070217557 - Secured identities collaboration system and method An identities collaboration system that comprises a Personal Service Provider (PSP) system for supplying specific user related personal service(s); means for assigning two different data files to each user opting-in to the PSP system, wherein one data file contains data representing user identity at the PSP system and it assigned ... 09/13/07 - 20070211838 - Timing signal recovery and distribution apparatus and methods Timing signal recovery and distribution apparatus and methods are disclosed. A timing synchronization source signal is selected from timing signals recovered by multiple communication devices. The timing signals may have any of multiple different frequencies. A timing distribution signal is generated by applying to the selected synchronization source signal one ... 08/16/07 - 20070189428 - Method and system for automatically calibrating a clock oscillator in a base station Method and system for automatically calibrating a clock oscillator (202) in a base station (102) are provided. The method (300) includes receiving (304) a span of at least one transmission link and linking (306) the base station to at least one reference clock over the at least one transmission link. ... 08/02/07 - 20070177698 - Signal transfer across circuits operating in different clock domains Signal transfer across circuits operating in different clock domains. According to an aspect of the present invention, a freeze signal is generated when it is determined that data is to be transferred from a first clocked element to a second clocked element. The freeze signal thus generated causes the first ... 07/19/07 - 20070165759 - Plural circuit selection using role reversing control inputs Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and ... 07/12/07 - 20070160172 - Communications device and communications method A communications device 100, which performs data communication, includes an AC cycle sensor 30 which is connected to a power line 106 supplied with an a.c. voltage and generates a synchronous signal SS at timing of an a.c. voltage waveform AC of the power line 106; a data communicator 10 ... 06/28/07 - 20070147563 - Synchronization of a digital circuit A method of synchronization of a digital circuit includes selecting a first site and a second site from a plurality of different sites of the digital circuit where a signal to be synchronized occurs; passing a first signal, which is the signal to be synchronized of the first site, via ... 06/28/07 - 20070147562 - Corrrecting time synchronization inaccuracy caused by asymmetric delay on a communication link Techniques for correcting time synchronization inaccuracy caused by asymmetric delays on a communication link. Time synchronization according to the present techniques includes determining an asymmetry in a propagation delay on a communication link used by a first device and a second device to exchange timing information and incorporating the asymmetry ... 06/28/07 - 20070147561 - Method and system for communicating sub-synchronization signals using a phase rotator A system and method of communicating sub-synchronization information into a transmitted digital audio stream and extracting sub-synchronization information from a received digital audio stream is provided. The method includes the steps of having a transmitter introduce sub-synchronization information into a data stream at a period less than that of existing ... 06/21/07 - 20070140393 - Compensation of reference frequency drift in system requiring critical upstream timing Systems and methods are disclosed for to compensating reference frequency drift in a communications system having a plurality of modems and a headend, where the system requires critical upstream timing. One embodiment of the method includes learning or determining the relative delay of each modem and reporting each modem's unique ... 06/21/07 - 20070140392 - Multi-input multi-frequency synthesizing apparatus and method for multi-band rf receiver A multi-input multi-frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver. The frequency synthesizing apparatus may generate an output from a greater number of high frequency signals by using one multi-input single side band (SSB) mixer. The multi-input SSB mixer may generate a signal whose frequency is ... 06/14/07 - 20070133725 - Apparatus and method for correcting frequency offset in satellite digital video broadcasting system Provided are an apparatus and method for correcting a frequency offset in a satellite digital video broadcasting system. The apparatus includes: a frequency response transformer for receiving a satellite digital video broadcasting signal and acquiring a plurality of frequency responses divided into a positive frequency part and a negative frequency ... 06/14/07 - 20070133724 - Method and apparatus for time synchronization of devices within electrical power systems A method for distributing a timing signal to a device. The method includes receiving a timing signal from a timing source, receiving a power signal, superimposing the timing signal on the power signal to facilitate creating a different power signal to be distributed to the device, decoding the timing signal ... 06/07/07 - 20070127610 - Programmable and pausable clock generation unit A clock generation circuit comprising two programmable ring oscillators (10, 20) arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern (14) is provided as an input to the oscillating circuit, the programming pattern (14) providing data representative ... 05/31/07 - 20070121770 - Frequency detecting and converting apparatus A frequency detecting and converting apparatus comprises a plurality of frequency-dividers, a multiplexer, a pulse width detector, a comparing unit and an encoder. The invention automatically detects the operating frequency of an input clock signal, divides the frequency of the input clock signal by a pre-defined integer according to the ... 05/31/07 - 20070121769 - Implied clock Systems and methods providing clocking between various components or sub-components are shown. Embodiments implement an implied clock technique which reduces the number of signal lines, signaling overhead required for an encoded clock signal, and/or and power consumption for a high speed communication link. In accordance with embodiments efficient communication is ... 05/24/07 - 20070116166 - Pilot scrambling enabling direct pilot sequence detection in initial acquisition in evolved utra A communications network and method thereof include a base station controller configured to provide a repetition period of a primary synchronization channel to be equal to a predetermined integer value times a scrambling code length of the scrambling code of a common pilot channel. A user equipment in the network ... 05/24/07 - 20070116165 - Asynchronous transmission device, asynchronous transmission method The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal ... 05/24/07 - 20070116164 - Clock alignment detection from single reference A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first ... 05/17/07 - 20070110202 - Using statistics to locate signals in noise Computation of variance or variance of the autocorrelation over a moving window of various sizes of a signal containing noise and possibly a small digital signal provides a sensitive, frequency independent indication of the likelihood of the presence of a small pulse, chirp or even spread spectrum digital signal possibly ... 05/10/07 - 20070104302 - Method and apparatus for reducing synchronizer shadow In one embodiment, a method for reducing synchronizer shadow involves: 1) receiving and deserializing a serialized data flit of known length, under control of a first clock domain; 2) before receiving all of the serialized data flit, beginning to resolve a valid signal for the deserialized data flit in a ... 04/19/07 - 20070086553 - Frequency-characteristic-acquisition device, frequency-characteristic-acquisition method, and sound-signal-processing device A frequency-characteristic-acquisition device that inputs a time-stretched-pulse signal to a system to be measured and that acquires information about a frequency characteristic of the system on the basis of a signal output from the system is provided. The frequency-characteristic-acquisition device includes a control unit which performs control so that the ... 04/19/07 - 20070086552 - Digital phase locked loop for regenerating the clock of an embedded signal The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. ... 04/19/07 - 20070086551 - Apparatus and method for switching clocks while preventing glitches and data loss A apparatus (700) and method (600) are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion (110) of an Ultra Wideband (UWB) receiver. a first and a second recovered clock (111, 112) and an external clock (109) can be input to a switch (116). Logical ... 04/05/07 - 20070076830 - Digital data transfer between different clock domains One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher ... 03/29/07 - 20070071151 - Method and an apparatus to reduce electromagnetic interference A method and an apparatus to reduce electromagnetic interference (EMI) have been presented. In one embodiment, the method includes using a first clock signal to create a second clock signal having a fundamental frequency lower than a frequency of the first clock signal, wherein the first clock signal is used ... 03/22/07 - 20070064846 - Interface apparatus and method for synchronization of data An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied ... 03/15/07 - 20070058762 - High quality, controlled latency multi-channel wireless digital audio distribution system and methods A multichannel wireless digital audio distribution system provides for the synchronization of the output of audio data by different receiving units set to output audio data for receiver unit assigned channels. The transmitter includes parallel data respectively representing a plurality of audio data channels in each data packet. The data ... 02/22/07 - 20070041482 - Communication network and method of controlling the communication network The invention relates to a communication network with at least two network nodes, with transmission channels for transmitting data packets between the network nodes, and with at least one active coupler. The invention provides for coupler information to be attached to the data packets as they pass through the active ... 02/15/07 - 20070036254 - Timing generator and methods thereof A timing generator and methods thereof are provided. In a first example method, a timing control signal may be produced by generating a base clock signal and a higher delay resolution clock signal, a clock cycle of the higher delay resolution signal being less than a clock cycle of the ... 02/15/07 - 20070036253 - Apparatus for updating gain of loop filter For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior gain value, and a prior timing signal estimation value. A timing error estimator generates a current timing ... 02/08/07 - 20070030935 - Method of synchronization for universal asynchronous receiver-transmitter A method for a synchronization between two mainframe apparatuses is disclosed, which uses a synchronous module with fast response time, reduced deviation, less electric current consumed and low cost. ... 02/08/07 - 20070030934 - Data serializer A method of serializing a data stream includes passing a series of data words from a source in a first clock domain to a serializer in a second clock domain and passing valid signals from the source to the serializer indicating when each of the data words is available from ... 02/08/07 - 20070030933 - Auto-synchronization of format definitions in a commutation/de-commutation system A system and a method for dynamically synchronizing a client (110) to a data source (105). The method can include the step of dynamically selecting a first length of format data to correspond to an amount of bandwidth of a commutated bitstream (115) allocated for synchronization. At least a first ... 02/01/07 - 20070025481 - Time synchronizing method and apparatus based on time stamp Provided are a time synchronizing method and apparatus based on a time stamp. The time synchronizing method includes: transmitting a local time stamp based on a free-running local clock to a master node; receiving a response time stamp from the master node; calculating a delta time value based on the ... 01/25/07 - 20070019766 - Clock circuitry for programmable logic devices Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) ... 01/25/07 - 20070019765 - Method of measuring inter-symbol interference and apparatus therefor Inter-Symbol Interference is measured in fibre-optic communications systems by using the statistically balanced nature of the data being communicated and correlating a received data signal with a time-delayed version of the data signal to obtain an error signal. The error signal drives an adaptive equaliser to achieve channel equalisation. ... 01/18/07 - 20070014388 - Method for generating transmitter clock and transmit clock generator A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a ... 01/11/07 - 20070009072 - Apparatus and method for calibrating the frequency of a clock and data recovery circuit Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates ... 01/11/07 - 20070009071 - Methods and apparatus to synchronize a clock in a voice over packet network Methods and apparatus are disclosed for synchronizing a local clock in a Voice over Packet Network. In an example method, a data packet is transmitted from a transmitting device with an associated transmission frame rate determined by a remote clock signal, and is received at a receiving device. The receiving ... 01/04/07 - 20070002988 - Semiconductor memory device A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value ... 01/04/07 - 20070002987 - Synchronizing clocks across a communication link Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal ... 12/21/06 - 20060285615 - Sinusoidal carrier synthesis apparatus and method A substantially pure sinusoidal carrier is produced by a digital-to-analog converter that repeatedly converts a sequence of N digital values provided by a digital sequencer to a stream of quantized analog samples. In certain embodiments, the N digital values comprise a time-domain function selected to substantially eliminate all odd harmonics ... 12/14/06 - 20060280270 - Method and system for fm communication Aspects of a method and system for FM communication are provided. An FM transceiver may generate FM radio frequency signals for transmission by modulating a single PLL within the FM transceiver via at least one modulation point with a frequency modulated multiplexed audio signal. The single PLL may also generate ... 12/07/06 - 20060274871 - Clock pulse control device of a microwave pulse radar The invention relates to a clock pulse control circuit for generating a transmit clock pulse (ts) and a sampling clock pulse (ta; tb; tc), wherein the clock pulse control circuit comprises a first oscillator (20) for generating a first clock pulse (ts) of a first frequency, and a second oscillator ... 12/07/06 - 20060274870 - Method for data signal transfer across different clock-domains In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of said data signal is started before the synchronization of said data signal is completed in said current clock-domain. ... 11/30/06 - 20060269028 - Procedure for the synchronization of nodes of a network and associated network The invention relates to a method for the synchronization of at least two network nodes (A, B) which connect with one another in a network designed for the wireless transmission of data, in particular a sensor network designed for the wireless transmission and processing of usage measurement data. The synchronization ... 11/30/06 - 20060269027 - Receiver including synch pulse detection and associated method A receiver includes a matched filter matched to a synch pulse and generates a matched filter output signal having peaks and valleys with one of the peaks corresponding to the synch pulse. An orthogonal filter is inversely matched to the synch pulse and generates an orthogonal filter output signal having ... 11/30/06 - 20060269026 - Synchronization methodology for systems employing data pull flow control In one embodiment, a system comprises a signal source for generating a digital signal in response to a data pull signal; a digital-to-analog converter (DAC); a first plurality of shift registers for registering digital words of the digital signal before receipt by the DAC; a synchronizing logic element for generating ... 11/16/06 - 20060256907 - Real time clock A timer circuit is provided. The timer circuit can provide register(s) (105) having information for each of two or more groups, wherein the information for each group indicates a tick count of a first clock signal (109) to count before providing a second clock signal (107). Also, the timer circuit ... 11/02/06 - 20060245527 - Method and apparatus for effecting synchronous pulse generation for use in serial communications A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signal; providing a counter, defining a sample count value of the ... 10/26/06 - 20060239391 - Evaluating base station timing in an asynchronous network The present invention provides a method of wireless communication with at least one mobile unit and at least two base stations. The method includes determining a phase difference between at least two timing signals associated with said at least two base stations based upon timing information provided by said at ... 10/12/06 - 20060227913 - Methods and apparatuses to provide synchronization symbol on demand for dsl systems A method and apparatus for providing synchronization data on demand are described. The method includes sending one or more synchronization parameters from a receiver to a transmitter in a data communication system, and adjusting transmission of synchronization data from a transmitter to a receiver using the one or more parameters ... 10/05/06 - 20060222127 - Method for performing high resolution phase alignment of multiple clocks using low resolution converters The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset signal is integrated into an average offset signal value, wherein the period of integration is the predetermined phase measurement ... 10/05/06 - 20060222126 - Systems and methods for maintaining synchronicity during signal transmission Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the claimed invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the claimed invention also provide systems and methods for maintaining determinism ... 10/05/06 - 20060222125 - Systems and methods for maintaining synchronicity during signal transmission Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the present invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the present invention also provide systems and methods for maintaining determinism ... 09/21/06 - 20060210004 - Method and controller for syncronizing a wireless communication device and network A communication controller and a method is provided for synchronizing a wireless communication device and a wireless communication network having two or more transmit antennas, which support transmit diversity. The communication controller and method generally provide for receiving a reference signal from the wireless communication network via each one of ... 09/07/06 - 20060198479 - Data synchronizer system A data synchronizer system includes at least two synchronizers for receiving a source pulse signal, a corresponding source clock, and a destination clock. At least two first memory units each have a destination clock input. A first switch has an input coupled to the source pulse signal and an output ... 08/31/06 - 20060193412 - Communication timing changing method and device The invention aims at providing communication timing changing method and device which are capable of changing timing of communication for setting control parameters used to determine operations of analog devices in the analog devices, respectively, over to another one not impeding any of the operation of the analog devices. An ... 08/17/06 - 20060182212 - Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems ... 08/17/06 - 20060182211 - Synchronization system using redundant clock signals for equipment of a synchronous transport network A synchronization system (D) for equipment of a synchronous transport network comprises, firstly, a first synchronization module (MA) comprising i) a first submodule (SM1A) delivering a first intermediate clock signal derived from a first external reference clock signal or an internal reference clock signal, ii) a second submodule (SM2A) delivering ... 07/27/06 - 20060165201 - Method and apparatus for recording time information for digital data streams A recording medium, an apparatus and a method for recording time information of digital data streams are provided. The apparatus in one embodiment includes a time information creating unit creating a first time field and a second time field, wherein the first time field includes a 90 KHz unit value ... 07/27/06 - 20060165200 - Synchronization device and device for generating a synchronization signal A synchronization device for determining a position of a synchronization signal in a receive signal, the synchronization signal being based on a coarse synchronization signal and a fine synchronization signal, includes a signal processing means configured to determine, based on the coarse synchronization signal, a section of the receive signal ... 07/20/06 - 20060159210 - Synchronized signal detector and synchronized signal detecting method A SYNC detection window creating section creates a SYNC window signal on the basis of the output of a counter counting a synchronized phase detection signal at a WDU cycle and the output of a counter counting WDU at a Segment cycle. On the other hand, a synchronized signal is ... 07/20/06 - 20060159209 - Multi-pipe synchronizer system A multi-pipe synchronizer system includes at least two synchronizers for receiving a source signal and corresponding source clock, and a destination clock. A switch is coupled to an input of each synchronizer for coupling the source signal to a selected synchronizer. A generator is coupled to an output of each ... 07/13/06 - 20060153324 - Modulation of a pilot carrier, and means to perform this modulation For synchronisation purposes, a transmitter (TX) multiplexes a pilot carrier with carriers whereon data elements (DATA) are modulated, and transmits the pilot carrier together with the modulated carriers to a receiver (RX). The immunity of the pilot carrier for interferers, such as radio amateur signals, is improved by modulating the ... 07/13/06 - 20060153323 - Clock generation device and clock generation method Upon reception of digital broadcast, system clocks which follow PCR data of an MPEG2-TS are provided. Upon disc playback, system clocks as fixed clocks are provided. To this end, upon processing the MPEG2-TS, first clocks CK1 synchronized with the PCR data are generated. If the user designates playback using high-precision ... 07/13/06 - 20060153322 - Method and system for synchronization between transmitter and receiver in a communication system A method and system for synchronization between a transmitter and a receiver in a communication system is provided. The receiver receives a plurality of signals from the transmitter. According to this method, a frequency burst is detected in the received signal at the receiver. The detected frequency burst is then ... 06/29/06 - 20060140317 - Clock synchronization circuit A clock synchronization circuit for synchronizing a first clock signal (Φ1) and a second clock signal (Φ2) for data transfer from a first function block (2), which is clocked by the first clock signal (ΦD) at a relatively high clock frequency (fΦ1), to a second function block (3), which is ... 06/22/06 - 20060133555 - Clock generation circuit and method thereof The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls ... 06/22/06 - 20060133554 - Methods and apparatus for efficiently synchronizing a transmitter and a receiver in a communication system The disclosed embodiments provide methods and systems for synchronizing a transmitter and a receiver. In one embodiment, a method for synchronizing a transmitter and a receiver includes the transmitter performing a reset operation, and the receiver responding by performing a reset operation. In another embodiment, a method for synchronizing a ... 06/22/06 - 20060133553 - Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps: generation of a secondary clock (16) at a predetermined clock frequency; application of the system clock (15) and of the ... 06/08/06 - 20060120495 - Timing system and method for a wireless transceiver system A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, ... 06/01/06 - 20060115033 - Data transmission circuit with serial interface and method for transmitting serial data A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the first clock; a serial interface circuit that supplies an output signal in synchronization with the first clock; and a latch ... 06/01/06 - 20060115032 - System and method for using programmable frequency offsets in a data network A method is provided for offsetting a reference frequency of a quadrature reference clock signal. A quadrature reference clock (110) generates the quadrature reference clock signal at the reference frequency, while a quadrature variable offset clock (130) generates a quadrature clock signal at a base offset frequency based on a ... 05/04/06 - 20060093081 - Method and system for packet synchronization A method and system for packet synchronization may comprise receiving a plurality of bits from an incoming sample of data. The received plurality of bits may be sliced at a first sampling rate. A logic level of at least one of the received plurality of bits may be determined based ... 04/13/06 - 20060078076 - System and method of digital system performance enhancement The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are ... 04/06/06 - 20060072695 - System and method for synchronizing audio-visual devices on a power line communications (plc) network A method and apparatus for synchronizing streaming media devices within a PLC network. Output synchronization errors exceeding ˜30 ms become noticeable when multiple streaming media devices are outputting an audio stream. The present invention provides a system and method for isochronously sending periodic reference clocks from a master device to ... 04/06/06 - 20060072694 - Synchronizing clocks in wireless personal area networks A method synchronizes a transmit clock of a transmitter with a receive clock of a receiver in a wireless communications network. Times t1, t2, t3, and t4 of the transmit clock corresponding times t1′, t2′, t3′, and t4′ of the receive clock. A synchronization message is generated in a media ... 03/30/06 - 20060067449 - Data processing device including clock recovery from various sources A data processing device is described having a first receive data input unit for inputting a first receive data stream into the data processing device, at least one second receive data input unit for inputting at least one second receive data stream and a clock recovery unit for recovering a ... 03/16/06 - 20060056557 - Method of detecting the relative positioning of two signals and corresponding device A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic ... 03/16/06 - 20060056556 - Method for guaranteeing an identical message sequence in serveral data sinks The invention relates to a method for guaranteeing an identical message sequence in several data sinks, according to which several data sources transmit data messages in parallel and independently of one another to said data sinks. To guarantee an identical message sequence, according to the invention a clock-pulse generator delivers ... 03/16/06 - 20060056555 - Syncronization signal detection apparatus and synchronization signal detection method A synchronization signal detection apparatus and a synchronization signal detection method for improving the reading performance of an input signal after the dissolution of a defect state or the like. Under a predetermined condition after no synchronization signals from an input signal have been detected in predetermined detection periods and ... 03/09/06 - 20060050824 - Standard wave receiver and time code decoding method A standard wave receiver and a time code decoding method, which receive a standard wave including a time code signal, in which one frame including plural time codes is repeated, and decode the time codes, are provided. The time code signal is sampled over a period, in which a plurality ... 03/09/06 - 20060050823 - Method and system for a multi-channel signal synchronizer Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion of the received plurality of clock signals. A plurality ... 03/09/06 - 20060050822 - Training pattern for a biased clock recovery tracking loop Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data. ... 03/09/06 - 20060050821 - Clock and data recovery circuit A clock and data recovery (CDR) circuit for recovering a clock signal from a non-return to zero data signal and re-timing the data signal is disclosed. The CDR circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and ... 03/09/06 - 20060050820 - Data transmission device and data transmission method A signal receiver (11) receives an analog signal via a twisted pair cable (31). An A/D converter (12) converts the analog signal to a digital signal. A phase detection unit (14) detects the phase of the digital signal, and generates a reception timing signal. A transmission timing generation unit (15) ... 03/09/06 - 20060050819 - Frame synchronizing device and method Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel ... 03/02/06 - 20060045223 - Symbol clock regenerating apparatus, symbol clock regenerating program and symbol clock regenerating method A symbol clock regenerating apparatus comprises symbol value acquisition means 1, 2 for acquiring a symbol value at a sampling timing with a sampling clock having a frequency m times (m is an integer of 3 or greater) that of a symbol clock to be regenerated, based on a digital ... 03/02/06 - 20060045222 - Optical driver including a multiphase clock generator having a delay locked loop (dll), optimized for gigahertz frequencies An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock ... 02/16/06 - 20060034404 - High resolution digital clock multiplier A high resolution programmable clock synthesizer that is portable across processes and, thus, process independent is disclosed herein. The clock synthesizer provides a dynamic solution, in that the frequency of the desired clock signal is programmable. Initially, a control unit monitors the input clock signal and the output clock signal ... 02/16/06 - 20060034403 - Phase-locked loop having dynamically adjustable up/down pulse widths According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in ... 02/09/06 - 20060029172 - Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, ... 02/02/06 - 20060023820 - Controller for clock synchronizer A controller arrangement and method for effectuating data transfer between a first clock domain and a second clock domain. In one embodiment, inversion circuitry inverts a first clock signal associated with the first clock domain into an inverted first clock signal that is used in effectuating a SYNC pulse during ... 02/02/06 - 20060023819 - Clock synchronizer A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which ... 01/19/06 - 20060013347 - Synchronizing a radio network with end user radio terminals Synchronizing a Radio Network with End User Radio Terminals A Mobile Station that is able to receive GPS signals and compare the frequency of the GPS received time signal with a time signal from a network in order to determine the difference between the signals and communicate that difference back ... 12/29/05 - 20050286667 - Method and circuit for adjusting the timing of output data based on the current and future states of the output data A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that ... 12/15/05 - 20050276364 - Cdma pilot assisted channel estimation A pilot assisted channel estimation process. A receiver may be configured to estimate the impulse response of a channel from a signal having pilot tones and spread-spectrum pilot signals. The receiver estimates the response of the channel from the pilot tones, and adapts the length of delay the channel response ... 12/08/05 - 20050271174 - Method of synchronization for packet based, ofdm wireless systems with multiple receive chains A system for synchronizing a wireless receiver is provided. The system includes a first antenna (101a) and a second antenna (101b) to receive wireless signals containing data packets. The system includes one or more analyzer components (156) operable to determine correlation metrics based on at least a portion of the ... 12/01/05 - 20050265503 - Method and system for enabling device functions based on distance information A method, device and computer readable medium for enabling and blocking communications with a remote device based on a distance of the remote device. The method on which the device and computer readable medium are based includes transmitting a message from a local device to a remote device via an ... 12/01/05 - 20050265502 - Synchronous compensator adaptively defining an enable range for synchronous compensation In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal ... 12/01/05 - 20050265501 - Resynchronizing timing sync pulses in a synchronizing rf system A synchronizing method and system between a Radio Frequency (RF) transmitter and a battery powered receiver wherein the transmitter transmits short duration first periodic sync signals which are used by the receiver to maintain proper synchronization of the receiver with the transmitter during second periodic wake-up windows for transmission of ... 12/01/05 - 20050265500 - Clock drift compensation method for remote communications A system may include a buffer, a local clock, and a processor. The buffer may store and output received media information. The local clock may control a rate at which the buffer outputs stored media information. The processor may determine a number of mean time differences between the local clock ... 12/01/05 - 20050265499 - Hardware assisted adjacent channel leakage ratio measurement A tester module is used to perform an adjacent channel leakage ratio measurement. The tester module includes a translation block, a first filter, a re-sampler, a memory, a router, a second filter and a power detector. The translation block translates a received intermediate frequency signal to a baseband signal. The ... 11/24/05 - 20050259773 - Method and apparatus for synchronizing transmissions In order to properly synchronize a communication system (100), a synchronization pulse is combined with DC power distribution. This is accomplished by interrupting the DC power that is supplied to each access point radio (102). The interruption occurs on a rising edge of the precision timing reference and lasts for ... 11/17/05 - 20050254610 - Signal detection apparatus and method thereof The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated ... 11/10/05 - 20050249321 - Phase rotation estimation Apparatus, systems, and methods implementing techniques for estimating a relative rotation between a first complex signal and a second complex signal. The first complex signal is quantized to produce a quantized signal, and the quantized signal and an additional signal are combined, where the additional signal corresponds to the second ... 10/20/05 - 20050232384 - Method for the synchronization of subscribers of a network According to the invention, a time emitter of a subscriber (1) provided as a reference in a network regularly and/or randomly transmits reference time signals (TR1). A subscriber (2) approximately adjusts the local time measurement thereof in relation to the time measurement of the reference subscriber (1) only if the ... 10/06/05 - 20050220235 - System and method for aligning internal transmit and receive clocks A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a ... 10/06/05 - 20050220234 - Synchronization establishment circuit and synchronization establishment method A terminal is wirelessly connected to a base station. The terminal has a timer and a controller. The timer has a register for storing a beacon interval as a comparison value. The timer also includes a beacon counter for counting timer clocks. The timer also includes a comparator for generating ... 10/06/05 - 20050220233 - Frequency detector including a variable delay filter A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random ... 09/29/05 - 20050213695 - Synchronization signal detector, information recording/reproducing apparatus, and synchronization signal detecting method Disclosed is a synchronization signal detecting apparatus that includes a window generating circuit for generating a synchronization detecting window, a re-synchronization window generating circuit for generating a re-synchronization window, and a synchronization detecting circuit for generating a re-synchronization detecting window of a time interval that excludes a re-synchronization window mask ... 09/29/05 - 20050213694 - Method for synchronizing memory areas in a transmitter apparatus and a receiver apparatus, and receiver apparatus The invention relates to a method for synchronizing a transmitter memory area in a transmitter memory in a transmitter apparatus with a receiver memory area in a receiver memory in a receiver apparatus, and to a receiver apparatus. The transmitter memory area stores transmission data as transmission-data packets and the ... 09/29/05 - 20050213693 - Data communication A data communication system for communicating an input streamed data signal having an associated clock signal comprises: at least two data handling nodes each having a physical layer interface device and a balanced line interface device, a transmitting one of the data handling nodes being arranged to transmit the input ... 09/22/05 - 20050207519 - Digital radio receiver A digital radio receiver is disclosed herein. The receiver substitutes a phase offset compensator with a simple and cost-effective structure for the conventional carrier recovery unit which is relatively complex and expensive, so as to decrease the complexity of the receiver and to provide cost savings. The digital radio receiver ... 09/15/05 - 20050201502 - Method and apparatus for synchronization of a receiver to a transmitter In a method for synchronization of a receiver to a transmitter which periodically transmits a sequence which is known in the receiver, a subset of possible synchronization times is determined in a first selection process by repeated correlation of the received signal with the known sequence and comparison of the ... 09/08/05 - 20050195928 - Transmission apparatus During detection of an amount for deskew, a test signal generator generates a test signal that has an edge, and a transmitter transmits the test signal. A reflected wave detection circuit detects a reflected wave of the test signal. A time measurement circuit measures the time from the instant the ... 09/01/05 - 20050190873 - Digital-data receiver synchronization method and apparatus Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise ... 09/01/05 - 20050190872 - Transcoding system and method for maintaining timing parameters before and after performing transcoding process A transcoding system and method effectively synchronize segmentation metadata with A/V content when converting an MPEG stream to another format stream using a segment browser. The transcoding system includes a timing synchronizer, which adjusts the timing parameters so that the video data can be synchronized with segmentation metadata even after ... 08/25/05 - 20050185744 - Synchronization determination control device and synchronization determination control method An SIR measurement unit measures SIR based on a received signal. A velocity detection unit detects the moving velocity of a mobile station. A synchronization determination processing unit determines whether or not the detected moving velocity is larger than a velocity detection threshold value. If it is determined that the ... 08/18/05 - 20050180536 - Interpolator based clock and data recovery (cdr) circuit with digitally programmable bw and tracking capability The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate ... 08/04/05 - 20050169414 - Transmitting circuit and method thereof, receiving circuit and method thereof, and data communication apparatus A method of frame synchronization serial data transmission. A transmitting circuit in a data communication apparatus converts frame data into serial data and transmit the same, and following the serial data, the transmitting circuit transmits frame synchronization data varying several times in the interval from an edge of a clock ... 08/04/05 - 20050169413 - Method to synchronise data and a transmitter and a receiver realising said method A method to realise synchronisation in a receiver (RX), of data (DAT) sent from a transmitter (TX) to the receiver (RX), with a signal (SIG) available in the receiver (RX). The method includes the following steps: in the receiver (RX) generating trigger signals (T) from the signal (S); sending the ... 07/28/05 - 20050163273 - System and method for providing synchronization information to a receiver The invention provides a method and system for synchronizing a transmitter and a receiver wherein the transmitter generates phase difference information indicating a phase difference between an internal and an external clock, the phase difference information is transmitted to the receiver, and the receiver generates a clock signal dependent on ... 07/28/05 - 20050163272 - High speed early/late discrimination systems and methods for clock and data recovery receivers The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to process center and edge samples and identify an average ... 07/07/05 - 20050147195 - Synchronizing circuit for stably generating an output signal The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the ... 06/23/05 - 20050135526 - Dual-pll signaling for maintaining synchronization in a communications system A communications management system introduces a low bandwidth phase locked loop (LoBW-PLL) working in tandem with a high bandwidth phase locked loop (HiBW-PLL). The LoBW-PLL only needs to follow the average frequency of the transported clock and not all of the excursions made by the master clock. During periods of ... 06/23/05 - 20050135525 - Dds circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system ... 06/23/05 - 20050135524 - High resolution synthesizer with improved signal purity An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high ... 06/23/05 - 20050135523 - Methods and arrangements for link power reduction Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by ... 06/09/05 - 20050123085 - Seamless clock System (10) comprising at least two units (1, 2) with clock functionality, the units being coupled to a common system clock line (SCLK), a common internal clock line (ICLK), and a logic bus (L-BUS), whereby one sole unit (1, 2) is being dedicated as a mater unit at a time. ... 06/02/05 - 20050117679 - Method and apparatus for synchronization of a mobile radio receiver to a base station In a method for synchronization of a mobile radio receiver to a base station, the received signal is sampled using oversampling, by which means sample values are obtained from different sampling phases. The oversampled signal is correlated with a local code, with sample values that are associated with a first ... 06/02/05 - 20050117678 - Method for resynchronization of a mobile radio receiver in the event of a change over between two different modulation methods When data bursts are transmitted between a base station and a mobile receiver, a changeover is made between a plurality of modulation methods during an existing radio link for modulation of the data. For resynchronization of the receiver in the event of the changeover, synchronization information items are determined from ... ### FreshPatents.com Support |