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Decision Feedback Equalizer

Decision Feedback Equalizer patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Pulse Or Digital Communications


Equalizers > Automatic > Adaptive > Decision Feedback Equalizer



Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
12/11/14 - 20140362901 - Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model...

Decision feedback equalizer ('dfe') with a plurality of independently-controlled isolated power domains
12/04/14 - 20140355661 - A Decision Feedback Equalizer (DFE) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled...

Pipelined charge redistribution decision feedback equalizer (dfe) for a receiver
12/04/14 - 20140355662 - A pipelined decision feedback equalizer (DFE) includes a programmable digital-to-analog converter (DAC) configured to provide a programmable voltage to a plurality of decision feedback equalized (DFE) sections, a capacitive element associated with each DFE section, the capacitive element coupled to an input connection by a first switch and coupled to...

Sampler circuit for a decision feedback equalizer and method of use threof
11/20/14 - 20140341268 - A sampler circuit for a decision feedback equalizer and a method of use thereof. One embodiment of the sampler circuit includes: (1) a first sampler portion including a series-coupled first master regeneration latch and first slave latch, (2) a second sampler portion including a series-coupled second master regeneration latch and...

Unequalized clock data recovery for serial i/o receiver
10/16/14 - 20140307769 - A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the...

Efficient calculation of initial equaliser coefficients
10/02/14 - 20140294058 - Methods of efficient calculation of initial equaliser coefficients are described. In a first stage, a channel matched filter is generated based on an estimate of CIR and then used to filter the CIR estimate. In a second stage, initial FFE coefficients are calculated from a portion of the match filtered...

Efficient tracking of decision-feedback equaliser coefficients
10/02/14 - 20140294059 - Efficient methods and apparatus for tracking decision-feedback equaliser (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equaliser (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In...

Multiphase receiver with equalization circuitry
09/25/14 - 20140286389 - An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the...

Adaptive continuous time linear equalizer
09/18/14 - 20140269888 - An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol...

Power and area efficient receiver equalization architecture with relaxed dfe timing constraint
09/18/14 - 20140269889 - An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the...

Digital equalizer adaptation using on-die instrument
09/18/14 - 20140269890 - Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to...

Combined turbo decoding and turbo equalization techniques
09/18/14 - 20140269891 - Techniques are disclosed for turbo decoding orthogonal frequency division multiplexing OFDM symbols. Techniques for combined turbo decoding and equalization are disclosed. The disclosed techniques can be implemented in receivers that receive wired or wireless OFDM signals and produce data and control bits by decoding the received signals....

Adaptation of equalizer settings using error signals sampled at several different phases
09/11/14 - 20140254655 - An apparatus includes an error sample generating circuit and an adaptation circuit. The error sample generating circuit is generally configured to generate error samples at a plurality of phases. The adaptation circuit may be configured to adjust one or more equalizer settings based upon a data sample and the error...

Co-channel dual polarized microwave device and method for receiving receive signal
09/04/14 - 20140247863 - Embodiments of the present invention disclose a co-channel dual polarized microwave device and a method. Frame synchronization is performed on a first receive signal processed by cross polarization interference cancellation and phase noise immunization is performed on the first receive signal processed by frame synchronization. Frame synchronization is performed on...

Offset and decision feedback equalization calibration
08/14/14 - 20140226707 - A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit...

Method and apparatus for algorithm on flexible square-qam coherent detection
07/31/14 - 20140211838 - In Software defined elastic optical networks, modulation format and constellation size may be flexibly modified. As a result, digital signal processing (DSP) algorithm should be compatible with different modulation schemes or readily reconfigurable at the optical coherent receiver. Therefore we propose a novel cascaded adaptive blind equalizers based on decision-directed...

Receiver having limiter-enhanced data eye openings
07/31/14 - 20140211839 - A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the...

Single carrier communication in dynamic fading channels
07/24/14 - 20140204992 - Briefly, in accordance with one or more embodiments, in response to receiving a single carrier signal that is not phase locked, channel equalization may be applied to the signal via a channel equalizer. The equalized signal may be phase averaged to provide a signal that is at least partially phase...

Adaptive equalizer
07/10/14 - 20140192856 - An adaptive equalizer (100) has a signal converter (200) for performing a fast Fourier transform and/or an inverse fast Fourier transform. The signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable...

Decision feedback equalizer using current mode processing with cmos compatible output level
06/26/14 - 20140177697 - A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS...

Signal transmission device performing compensation by filtering characteristics and method thereof, and signal reception device offsetting compensation and method thereof
06/26/14 - 20140177698 - The present invention discloses a signal transmission device performing compensation by filtering characteristics for generating a transmission signal according to a pulse amplitude modulation signal. The signal transmission device comprises: a filtering characteristic compensation circuit for generating a compensation signal according to the pulse amplitude modulation signal and a filtering...

Equalizer and semiconductor device
06/26/14 - 20140177699 - An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit...

Apparatus and methods for equalizer adaptation
06/19/14 - 20140169439 - One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal...

Adaptive cancellation of voltage offset in a communication system
06/19/14 - 20140169440 - Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock...

Modulation and equalization in an orthonormal time-frequency shifting communications system
06/19/14 - 20140169441 - A method of receiving data including receiving, on one or more carrier waveforms, signals representing a plurality of data elements of an original data frame wherein each of the data elements are represented by cyclically time shifted and cyclically frequency shifted versions of a known set of waveforms. The method...

Clock data recovery method and clock data recovery circuit
06/19/14 - 20140169442 - A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to...

Receiver with parallel decision feedback equalizers
05/29/14 - 20140146867 - Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input...

Decision feedback equalizers and operating methods thereof
05/29/14 - 20140146868 - A decision feedback equalizer (DFE) includes a sampler for receiving a first input signal and comparing an amplitude of the first input signal with a first predetermined voltage level and a second predetermined voltage level. The DFE includes a DFE logic circuit for receiving at least one first sign signal...

Forward error correction with parity check encoding for use in low complexity highly-spectrally efficient communications
05/22/14 - 20140140388 - A transmitter inserts parity samples into a stream of information symbols in an inter-symbol correlated (ISC) signal. The inserted parity samples may be utilized to generate estimates of corresponding information symbols when they are received by a receiver. The information symbols may be pulse shaped by a first pulse shaping...

Receiver with duobinary mode of operation
05/22/14 - 20140140389 - An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a...

Compensation factor reduction in an unrolled decision feedback equalizer
05/15/14 - 20140133544 - An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where...

Systems, circuits and methods for adapting parameters of a linear equalizer in a receiver
05/08/14 - 20140126625 - A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is...

Slicer and method of operating the same
05/01/14 - 20140119426 - A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch...

Systems for high-speed backplane applications using pre-coding
04/24/14 - 20140112382 - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still...

Decision feedback equalizer utilizing symbol error rate biased adaptation function for highly spectrally efficient communications
04/17/14 - 20140105268 - One or more embodiments describe a decision feedback equalizer utilizing symbol error rate biased adaptation function for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include determining values of tap coefficients used by the DFE based. The tap coefficients may...

Equalization effort-balancing of transmit finite impulse response and receive linear equalizer or receive decision feedback equalizer structures in high-speed serial interconnects
04/03/14 - 20140092952 - Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of...

Interference channel equalizer
03/27/14 - 20140086300 - An interference channel equalizer for receiving and processing at least two distinct RF data signals transmitted over the same frequency to a single receiving station that has at least one receiver for each distinct transmitted RF data signal. Each receiver processes an RF data signal received by its antenna and...

Feed forward equalizer tap weight adaptation based on channel estimation
03/06/14 - 20140064352 - An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel....

Crossing isi cancellation
03/06/14 - 20140064353 - An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate...

Filter calculating device, transmitting device, receiving device, processor, and filter calculating method
03/06/14 - 20140064354 - A filter calculating device includes a first equalization filter calculating section that generates at least a first conversion matrix and a first triangular matrix based on a channel state of a first channel; a first quasi-orthogonalization section that calculates a first unimodular matrix based on the first triangular matrix; and...

Decision feedback equalizers with high-order continuous time feedback
02/27/14 - 20140056344 - Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response....

Decision feedback equalizers with high-order continuous time feedback
02/27/14 - 20140056345 - Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response....

High-speed parallel decision feedback equalizer
02/27/14 - 20140056346 - A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment...

Switched continuous time linear equalizer with integrated sampler
02/20/14 - 20140050260 - An apparatus includes an input, an output, an equalizer configured to receive an input signal at the input and to output an output signal for the output, and a reset block coupled to the equalizer and the output. The reset block is configured to pull the output signal at the...

Equalization of a distributed pilot ofdm signal
02/06/14 - 20140036984 - A technique for equalizing a distributed pilot OFDM signal with decision feedback involves correlating a received OFDM signal against a pilot reference to obtain a coarse channel estimate, where the received OFDM signal includes a distributed pilot signal and an OFDM data signal. The received OFDM signal is equalized based...

Decision feedback equalization with selectable tap
02/06/14 - 20140036985 - A system generates a set of candidate signals based on a received signal, whereby each candidate signal represents an adjustment of the signal for a different amount of potential noise. The system selects one of the candidate signals based on a selected subset of previous samples and the values of...

Coarse phase estimation for highly-spectrally-efficient communications
02/06/14 - 20140036986 - Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback...

Fast generalized decision feedback equalizer precoder implementation for multi-user multiple-input multiple-output wireless transmission systems
01/30/14 - 20140029662 - A technique is used to realize a generalized decision feedback equalizer (GDFE) Precoder for multi-user multiple-input multiple-output (MU-MIMO) systems, which significantly reduces the computational cost while resulting in no capacity loss. The technique is suitable for improving the performance of various MU-MIMO wireless systems including future 4G cellular networks. In...

Adaptation of baseline wander correction loop gain settings
01/23/14 - 20140023134 - An apparatus includes a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to...

Edge based partial response equalization
01/16/14 - 20140016692 - A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on...

Circuit and method for clock data recovery
01/09/14 - 20140010276 - A clock data recovery circuit includes an equalizer, a multi-phase clock generator, a sampling and check unit, a signal edge detection unit and an adjusting unit. The equalizer performs an equalization on an incoming data signal. The multi-phase clock generator generates multiple clock signals and at least one pair of...

On-the-fly compensation of sampling frequency and phase offset in receiver performing ultra-high-speed wireless communication
01/02/14 - 20140003485 - Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a...

Feed-forward equalizer architectures
12/19/13 - 20130336378 - Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein...

Receiving circuit, clock recovery circuit, and communication system
12/12/13 - 20130329776 - A received data acquisition circuit performs a decision-feedback equalization process on a received signal to obtain a shaped signal, and also performs sampling of the shaped signal with a sampling rate equal to or higher than a self-resonant frequency, according to a sampling clock, to obtain a data sample. A...

Receiver with four-slice decision feedback equalizer
12/05/13 - 20130322512 - A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator...

Decision feedback equalizer
11/21/13 - 20130308694 - A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than...

Blind equalization in a single carrier wideband channel
11/14/13 - 20130301697 - a DD LMS blind equalizer, wherein: the blind equalizer uses a finite impulse response filter with tap weights that are adaptively updated using a filter tap update algorithm, wherein blind equalization of one of an in-phase (I) channel and a quadrature (Q) channel is carried out by maximizing the Euclidean...

Efficient frequency domain (fd) mmse equalization weight updates in a multi-stage parallel interference cancellation receiver
11/07/13 - 20130294494 - A system and method to more efficiently compute updated Frequency Domain (FD) Minimum Mean Squared Error (MMSE) equalization weights in a multi-stage Parallel Interference Cancellation (PIC) receiver after initial interference cancellation. The updated equalization weights (which are to be used during re-equalization) can be obtained using the old equalization weights...

Receiver having limiter-enhanced data eye openings
10/31/13 - 20130287088 - A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the...

Circuits and methods for dfe with reduced area and power consumption
10/31/13 - 20130287089 - A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit...

Method and apparatus for soft symbol processing in a communication receiver
10/24/13 - 20130279559 - In one aspect, the present invention improves Turbo equalization and/or soft interference cancellation processing in communication receivers by providing an efficient and accurate technique to compute the second moment of a received symbol, e.g., an interfering symbol, as a function of the expected bit values of only those bits in...

Asymmetric multi-channel adaptive equalizer
10/24/13 - 20130279560 - An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes...

Systems and methods for adaptive blind mode equalization
10/03/13 - 20130259113 - Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with...

Tap adaptation with a fully unrolled decision feedback equalizer
09/19/13 - 20130243070 - Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal....

Predictive selection in a fully unrolled decision feedback equalizer
09/19/13 - 20130243071 - Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators, each comparator provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision...

Multi-protocol communications receiver with shared analog front-end
09/19/13 - 20130243072 - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits...

Extension of ethernet phy to channels with bridged tap wires
09/05/13 - 20130230091 - In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes;...

Sparse and reconfigurable floating tap feed forward equalization
09/05/13 - 20130230092 - In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques....

Shift register based downsampled floating tap decision feedback equalization
09/05/13 - 20130230093 - Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of...

Analog signal current integrators with tunable peaking function
08/22/13 - 20130215954 - Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current...

Apparatus and method for detecting communications from multiple sources
08/22/13 - 20130215955 - A method, apparatus, and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources is determined. The real-domain representation is...