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Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape



Sensor device packages and related fabrication methods
04/23/15 - 20150108653 - Sensor device packages and related fabrication methods are provided. An exemplary sensor device package includes a first structure having a sensing arrangement thereon, a second structure having circuitry thereon, and a conductive structure within the first structure and coupled to the circuitry to provide an electrical connection to the circuitry...

Reliable passivation layers for semiconductor devices
04/23/15 - 20150108654 - Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the...

Semiconductor device and method of manufacturing the same
04/23/15 - 20150108655 - Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of...

Stacked die package
04/23/15 - 20150108656 - Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted...

Electronic device
04/23/15 - 20150108657 - A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at...

Self-aligned nano-structures
04/23/15 - 20150108658 - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or...

3d-packages and methods for forming the same
04/23/15 - 20150108659 - A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die...

Stacked memory with interface providing offset interconnects
04/23/15 - 20150108660 - A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face...

Semiconductor package
04/16/15 - 20150102495 - A semiconductor package is provided. The semiconductor package includes a substrate, a first pad, a second, a first conductive element, a surface mount device, a first bonding wire and a molding compound layer. The first pad, the second pad, and the first conductive element are formed on the substrate. The...

Novel method to make high aspect ratio vias for high performance devices interconnection application
04/16/15 - 20150102496 - Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin....

Integrated circuit devices including a through-silicon via structure and methods of fabricating the same
04/16/15 - 20150102497 - Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and...

Carrier-bonding methods and articles for semiconductor and interposer processing
04/16/15 - 20150102498 - A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during...

Integrated circuit chip comprising electronic device and electronic system
04/16/15 - 20150102499 - An electronic device includes a substrate wafer made of many layers of an insulating material and including an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer further includes a metal plate that is integrated into the substrate wafer...

Electronic system comprising stacked electronic devices comprising integrated-circuit chips
04/16/15 - 20150102500 - An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second...

Semiconductor device for battery power voltage control
04/16/15 - 20150102501 - A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other,...

Integrated fan-out structure with openings in buffer layer
04/16/15 - 20150102502 - A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel...

Semiconductor device and manufacturing method thereof
04/16/15 - 20150102503 - A fan out package includes a molding compound, a conductive plug in the molding compound, a dielectric covering the molding compound and a portion of the conductive plug, and an interconnect disposed over the dielectric and contacted with the conductive plug, wherein a width of the interconnect contacting the conductive...

Multi-die stack structure
04/09/15 - 20150097296 - A multi-die stack structure including N dies stacked vertically is described. N is an integer larger than or equal to 2. Each die includes N die-specific input pads, wherein a specific pad among the N pads is for the input of the die. The specific pad of each die above...

Semiconductor article having a zig-zag guard ring
04/09/15 - 20150097297 - A semiconductor article which includes a semiconductor base portion including a semiconductor material; a back end of the line (BEOL) wiring portion on the semiconductor base portion and comprising a plurality of wiring layers having metallic wiring and insulating material, said BEOL wiring portion excluding a semiconductor material; and a...

Semiconductor substrate assembly
04/09/15 - 20150097298 - A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on...

3d device packaging using through-substrate pillars
04/02/15 - 20150091178 - A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second...

Semiconductor device with via bar
04/02/15 - 20150091179 - A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of...

Package on wide i/o silicon
04/02/15 - 20150091180 - An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a...

Self-aligned vias formed using sacrificial metal caps
04/02/15 - 20150091181 - A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric...

Die assembly on thin dielectric sheet
04/02/15 - 20150091182 - A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to...

Arrangement and method for manufacturing the same
04/02/15 - 20150091183 - An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing...

Semiconductor memory apparatus
04/02/15 - 20150091184 - A semiconductor memory apparatus includes: a power distribution line disposed over a circumferential portion of a device formation region; a guard ring formed to surround the device formation region outside of the power distribution line; and one or more power reinforcement parts configured to electrically couple an edge part of...

Semiconductor device and method for forming the same
04/02/15 - 20150091185 - A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing...

Interconnection structure, semiconductor device, and method of manufacturing the same
04/02/15 - 20150091186 - A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part...

3d device packaging using through-substrate posts
04/02/15 - 20150091187 - A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a...

Semiconductor device having dummy cell array
04/02/15 - 20150091188 - A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines,...

Apparatuses and methods enabling concurrent communication
04/02/15 - 20150091189 - Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die....

Super-self-aligned contacts and method for making the same
04/02/15 - 20150091190 - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each...

Chip package and method for forming the same
03/26/15 - 20150084205 - A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate...

Semiconductor device and method of forming dual fan-out semiconductor package
03/26/15 - 20150084206 - A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive...

Embedded semiconductor device package and method of manufacturing thereof
03/26/15 - 20150084207 - A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are...

Connection member, semiconductor device, and stacked structure
03/26/15 - 20150084208 - A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via,...

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
03/19/15 - 20150076704 - In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first...

Reduced capacitance interlayer structures and fabrication methods
03/19/15 - 20150076705 - Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and...

Through-silicon via unit cell and methods of use
03/19/15 - 20150076706 - Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to...

Integrated circuit via structure and method of fabrication
03/19/15 - 20150076707 - A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of...

Semiconductor device
03/19/15 - 20150076708 - A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less...

Semiconductor device and manufacturing method for the same
03/19/15 - 20150076709 - A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed...

Integrated semiconductor device and wafer level method of fabricating the same
03/19/15 - 20150076710 - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate,...

Conductive ink for filling vias
03/19/15 - 20150076711 - Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a...

Method for forming through wafer vias
03/12/15 - 20150069618 - A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and spaces, bonding a slab or wafer of glass to the template substrate, and melting the glass so that it flows into...

3dic interconnect apparatus and method
03/12/15 - 20150069619 - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric...

Semiconductor devices and methods of forming same
03/12/15 - 20150069620 - Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor device, the method including forming a first conductive feature over a substrate, forming a dielectric layer over the conductive feature, and forming an opening through...

Embedded electronic packaging and associated methods
03/12/15 - 20150069621 - An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings....

Via definition scheme
03/12/15 - 20150069622 - A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric...

Integrated fan-out structure with guiding trenches in buffer layer
03/12/15 - 20150069623 - A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein...

Recessed semiconductor die stack
03/12/15 - 20150069624 - Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second...

Ultra-thin metal wires formed through selective deposition
03/12/15 - 20150069625 - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process....

Chip package, chip package module based on the chip package, and method of manufacturing the chip package
03/12/15 - 20150069626 - A chip package is formed of a complex substrate and a chip. The complex substrate includes a core plate, a thermally-conductive insulated layer, and a through hole running through the core plate and the thermally-conductive insulated layer. The core plate is fixed to the core plate and buried into the...

Interposer wafer and method of manufacturing same
03/12/15 - 20150069627 - In one embodiment, a method of manufacturing an interposer wafer includes forming a first hole having a first depth on a first main surface of a semiconductor wafer. The method further includes forming a second hole having a second depth on the first main surface of the semiconductor wafer before...

Semiconductor package and method of fabricating the same
03/12/15 - 20150069628 - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces...

Hybrid package transmission line circuits
03/12/15 - 20150069629 - “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a...

Device with through-substrate via structure and method for forming the same
03/05/15 - 20150061147 - A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the...

3d ic with serial gate mos device, and method of making the 3d ic
03/05/15 - 20150061148 - A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second...

Packages, packaging methods, and packaged semiconductor devices
03/05/15 - 20150061149 - Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a...

Stacked semiconductor chip device with phase change material
03/05/15 - 20150061150 - Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket...

Package structure having silicon through vias connected to ground potential
03/05/15 - 20150061151 - A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality...

Package module with offset stack device
03/05/15 - 20150061152 - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections...

Semiconductor device and method for manufacturing the same
03/05/15 - 20150061153 - According to one embodiment, a semiconductor device includes a semiconductor layer including a first region and a second region, a first insulating layer provided above the semiconductor layer, an extending first contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a first element provided...

Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same
03/05/15 - 20150061154 - A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls...

Semiconductor devices and methods of fabricating the same
03/05/15 - 20150061155 - The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented....

Pad solutions for reliable bonds
03/05/15 - 20150061156 - A bonding pad and a method of manufacturing a bonding pad are presented. The method includes providing a substrate prepared with circuits component and an interlevel dielectric (ILD) layer with interconnects. A final passivation level is formed on the substrate surface and includes a pad opening. A wire bond in...

Semiconductor devices and methods of manufacture thereof
02/26/15 - 20150054170 - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface...

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054171 - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns....

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054172 - According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer. The conductive material is embedded into a via which penetrates the semiconductor layer in a thickness direction thereof and is electrically connected to...

Semiconductor package, method of manufacturing semiconductor package and stack type semiconductor package
02/26/15 - 20150054173 - Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base...

Interconnection structure with confinement layer
02/26/15 - 20150054174 - An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive...

Semiconductor device and method for making same
02/26/15 - 20150054175 - One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive...