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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape

Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/25/14 - 20140284813 - Interconnect level structures for confining stitch-induced via structures
A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer...

09/25/14 - 20140284814 - Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a first wiring, a second wiring disposed in the same layer as the first wiring, a first via connected to a bottom surface of the first wiring and formed of a carbon nanotube, and a second via connected to a bottom surface...

09/25/14 - 20140284815 - Interlevel dielectric stack for interconnect structures
A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances...

09/25/14 - 20140284816 - Through silicon via wafer, contacts and design structures
Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material....

09/18/14 - 20140264902 - Novel patterning approach for improved via landing profile
The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of...

09/18/14 - 20140264903 - Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a...

09/18/14 - 20140264904 - Unified pcb design for ssd applications, various density configurations, and direct nand access
Memory systems and methods for creating the same are disclosed. The memory systems can include pairs of IC packages mounted on either side of a system substrate. Contacts formed on the IC packages can be communicatively coupled with contacts of a paired IC package using vias that extend through the...

09/18/14 - 20140264905 - Semiconductor device and method of forming wlcsp with semiconductor die embedded within interconnect structure
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect...

09/18/14 - 20140264906 - Systems and methods for high-speed, low-profile memory packages and pinout designs
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from...

09/18/14 - 20140264907 - Stubby pads for channel cross-talk reduction
A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount...

09/18/14 - 20140264908 - Dual damascene gap filling process
A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions...

09/18/14 - 20140264909 - Microelectromechanical system devices having through substrate vias and methods for the fabrication thereof
Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via...

09/18/14 - 20140264910 - Interconnect structures with polymer core
Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a...

09/18/14 - 20140264911 - Through silicon vias
A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish...

09/18/14 - 20140264912 - Semiconductor device
A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of...

09/18/14 - 20140264913 - Semiconductor device
A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of...

09/18/14 - 20140264914 - Chip package-in-package and method thereof
An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through...

09/18/14 - 20140264915 - Stacked integrated circuit system
A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second...

09/18/14 - 20140264916 - An integrated structure with a silicon-through via
An integrated structure with a silicon-through via comprises a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure....

09/18/14 - 20140264917 - A semiconductor device with a through-silicon via and a method for making the same
A semiconductor device with a through-silicon via comprises a substrate with a front side and a backside and a through-silicon via penetrating the substrate with a circular shape on the front side and a corner-rounded rectangular shape on the back side....

09/18/14 - 20140264918 - Integrated circuit layout
An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV...

09/18/14 - 20140264919 - Chip arrangement, wafer arrangement and method of manufacturing the same
Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second...

09/18/14 - 20140264920 - Metal cap apparatus and method
Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap...

09/18/14 - 20140264921 - Through-silicon via with sidewall air gap
Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV...

09/18/14 - 20140264922 - Semiconductor structure
One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first...

09/18/14 - 20140264923 - Interconnect structure with kinked profile
Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first...

09/18/14 - 20140264924 - Apparatus and method for mitigating dynamic ir voltage drop and electromigration affects
An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a...

09/18/14 - 20140264925 - Interlayer conductor and method for forming
A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and...

09/18/14 - 20140264926 - Method and apparatus for back end of line semiconductor device processing
A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top...

09/18/14 - 20140264927 - Single mask package apparatus and method
Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may...

09/18/14 - 20140264928 - Semiconductor package and fabrication method thereof
A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming...

09/18/14 - 20140264929 - Interconnect structure for stacked device
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked...

09/18/14 - 20140264930 - Fan-out interconnect structure and method for forming same
A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound...

09/18/14 - 20140264931 - Stress tuning for reducing wafer warpage
An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress...

09/18/14 - 20140264932 - Patterning approach to reduce via to via minimum spacing
A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further...

09/18/14 - 20140264933 - Wafer level chip scale packaging intermediate structure apparatus and method
Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL...

09/18/14 - 20140264934 - Interlayer conductor structure and method
To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another...

09/18/14 - 20140264935 - Semiconductor device manufacturing method and semiconductor mounting substrate
A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of...

09/18/14 - 20140264936 - Semiconductor package
A semiconductor package including a first connection terminal group configured to receive a first signal group from the outside of the semiconductor package, a second connection terminal group configured to transmit a second signal group to the outside, a first chip connected to the first connection terminal group, and a...

09/18/14 - 20140264937 - Through-silicon vias and interposers formed by metal-catalyzed wet etching
Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at...

09/18/14 - 20140264938 - Flexible interconnect
The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive...

09/18/14 - 20140264939 - Semiconductor device
A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the...

09/18/14 - 20140264940 - Semiconductor package and package on package having the same
A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor...

09/18/14 - 20140264941 - Three-dimensional semiconductor architecture
A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior...

09/11/14 - 20140252644 - Mitigating electromigration effects using parallel pillars
Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of...

09/11/14 - 20140252645 - Thermal design and electrical routing for multiple stacked packages using through via insert (tvi)
Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI...

09/11/14 - 20140252646 - Interconnect structure for package-on-package devices
An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to...

09/11/14 - 20140252647 - Warpage reduction and adhesion improvement of semiconductor die package
Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing...

09/11/14 - 20140252648 - Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a portion of a first low-k (LK) dielectric layer between the first metal line and the second metal line; and a...

09/11/14 - 20140252649 - Semiconductor module
According to one embodiment, a semiconductor module includes a substrate, which has a first surface and a second surface opposite to the first surface, a controller device and a memory device formed on the first surface, and a metal plate bonded on the second surface. The metal plate is formed...

09/11/14 - 20140252650 - Semiconductor integrated circuit
In one embodiment, a semiconductor integrated circuit includes power supply strap wires extending in a first direction in a first layer, auxiliary power supply strap wires extending in the first direction in a second layer below the first layer, and intermediate power supply wires each electrically connecting one of the...

09/11/14 - 20140252651 - Anchor vias for improved backside metal adhesion to semiconductor substrate
Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor...

09/11/14 - 20140252652 - Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package
A bonding structure of a semiconductor package includes: a first conductive member configured to transmit an electrical signal; and a bonding pad configured to be electrically coupled to a surface of the first conductive member and comprising a plurality of sub bonding pads....

09/11/14 - 20140252653 - Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy...

09/11/14 - 20140252654 - Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive...