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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape

Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

11/20/14 - 20140339705 - Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias
An integrated circuit package includes an integrated circuit package comprising an interposer and an integrated circuit die. The interposer is formed from a silicon-on-insulator semiconductor substrate and includes a plurality of through-silicon vias, and the integrated circuit die is electrically coupled to a first through-silicon via included in the plurality...

11/20/14 - 20140339706 - Integrated circuit package with an interposer formed from a reusable carrier substrate
An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer. Vias in the interposer can be formed...

11/20/14 - 20140339707 - Thermal dissipation through seal rings in 3dic structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying...

11/13/14 - 20140332973 - Inline measurement of through-silicon via depth
A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and...

11/13/14 - 20140332974 - Providing a void-free filled interconnect structure in a layer of a package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for providing void-free filled interconnect structures in a dielectric layer of a package assembly. In one embodiment, the method for providing a void-free filled interconnect structure may include forming a through hole through a layer of a package substrate,...

11/13/14 - 20140332975 - Multichip integration with through silicon via (tsv) die embedded in package
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as...

11/13/14 - 20140332976 - Semiconductor package and fabrication method thereof
A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first...

11/13/14 - 20140332977 - Semiconductor device
A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a Polymide Isoindro Quirazorindione (PIQ) layer formed to cover the open region and to define a pad open region by exposing a center...

11/13/14 - 20140332978 - Optical wiring substrate, manufacturing method of optical wiring substrate and optical module
An optical wiring substrate includes a first conductor layer including a metal, a second conductor layer including a metal and arranged parallel to the first conductor layer, an insulation layer disposed to insulate the first conductor layer from the second conductor layer, and an electronic component including a photoelectric conversion...

11/13/14 - 20140332979 - Architecture of spare wiring structures for improved engineering change orders
An integrated circuit includes a substrate having a plurality of electronic devices, a plurality of interconnect layers disposed on one or both sides of the substrate, and a plurality of active electrically conductive interconnect layer structures. The plurality of interconnect layers include horizontal interconnect and vertical-interconnect-access (VIA) layers. The plurality...

11/13/14 - 20140332980 - Methods of forming 3-d circuits with integrated passive devices
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the...

11/13/14 - 20140332981 - Low-stress vias
A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define...

11/06/14 - - Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the...

11/06/14 - 20140327146 - Methods for improving double patterning route efficiency
A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to...

11/06/14 - 20140327147 - Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at...

11/06/14 - 20140327148 - Chip on film package including distributed via plugs
A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length,...

11/06/14 - 20140327149 - Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate....

11/06/14 - 20140327150 - Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of...

11/06/14 - 20140327151 - Through substrate via structures and methods of forming the same
A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure...

11/06/14 - 20140327152 - Chip package
A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from...

10/30/14 - 20140319693 - Semiconductor device and method of forming the same
A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate...

10/30/14 - 20140319694 - Anticipatory implant for tsv
A method including implanting a region of a substrate with a dopant, and forming a through-substrate via in the substrate adjacent to a device, the through-substrate via passing through the region....

10/30/14 - 20140319695 - Semiconductor device and method of forming stress-reduced conductive joint structures
A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer...

10/30/14 - 20140319696 - 3d packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of...

10/30/14 - 20140319697 - Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated...

10/30/14 - 20140319698 - Redistribution layer contacting first wafer through second wafer
A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor...

10/30/14 - 20140319699 - Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a...

10/23/14 - 20140312502 - Through-vias for wiring layers of semiconductor devices
Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is...

10/23/14 - 20140312503 - Semiconductor packages and methods of fabricating the same
A semiconductor package comprises a package substrate including a package pad, the package pad being conductive. A semiconductor chip is on the package substrate including a chip pad, the chip pad being conductive, the semiconductor chip extending in a horizontal direction of extension. A transparent substrate is on the semiconductor...

10/23/14 - 20140312504 - Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be...

10/23/14 - 20140312505 - Semiconductor devices and fabrication methods thereof
A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein...

10/23/14 - 20140312506 - Semiconductor device and method for manufacturing same
A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an I/O pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor...

10/23/14 - 20140312507 - Semiconductor device having a multilayer interconnection structure
A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor...

10/23/14 - 20140312508 - Semiconductor interconnect structures
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features...

10/16/14 - 20140306349 - Low cost interposer comprising an oxidation layer
Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is...

10/16/14 - 20140306350 - Method of manufacturing through-glass vias
A method of forming a through-glass via hole involves providing a glass substrate having first and second substantially planar parallel surfaces; masking the first and second substantially planar parallel surfaces to form a via-patterned portion thereon; and etching the via-patterned portion on the first and second substantially planar parallel surfaces...

10/16/14 - 20140306351 - Semiconductor device with air gap and method of fabricating the same
A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second...

10/16/14 - 20140306352 - Semiconductor device and fabrication method
Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate. A plurality of pillar structures having a matrix arrangement can be formed on the dielectric layer. A plurality of sidewall spacers can be formed on the dielectric layer....

10/09/14 - 20140299999 - Integrated circuit package assemblies including a glass solder mask layer
Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the...

10/09/14 - 20140300000 - Semiconductor device and method
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to...

10/09/14 - 20140300001 - Printed circuit board and manufacturing method thereof, and semiconductor package including the printed circuit board
A printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the...

10/09/14 - 20140300002 - Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer...

10/09/14 - 20140300003 - Semiconductor device and interconnect substrate
A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate,...

10/09/14 - 20140300004 - Semiconductor packages and methods of fabricating the same
Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter,...

10/09/14 - 20140300005 - Multilevel interconnect structures and methods of fabricating same
A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via....

10/09/14 - 20140300006 - Conductive structures, systems and devices including conductive structures and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor...

10/09/14 - 20140300007 - Semiconductor apparatus
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each...

10/02/14 - 20140291853 - Package structure of a chip and a substrate
A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed...

10/02/14 - 20140291854 - Semiconductor packages having tsv and adhesive layer
A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through...

10/02/14 - 20140291855 - Semiconductor device and semiconductor system including the same
A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon...

10/02/14 - 20140291856 - Tsv layout structure and tsv interconnect structure, and fabrication methods thereof
TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average...

10/02/14 - 20140291857 - Stacked structure and method of manufacturing the stacked structure
A stacked structure, includes: a wiring; an insulating layer; a substrate; and a protective layer, wherein the wiring, the insulating layer, and the substrate are stacked from a bottom side, and an end portion of the wiring is projected from a side face of the stacked structure, and the protective...

10/02/14 - 20140291858 - Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto
A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads....

10/02/14 - 20140291859 - Electronic component built-in substrate and method of manufacturing the same
An electronic component built-in substrate, includes, a substrate having an opening portion, a first wiring layer formed in the substrate, an electronic component arranged in the opening portion, a first insulating layer formed on one face of the substrate and sealing the electronic component, a second insulating layer formed on...

10/02/14 - 20140291860 - Semiconductor-on-insulator integrated circuit with interconnect below the insulator
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and...

10/02/14 - 20140291861 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

10/02/14 - 20140291862 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

10/02/14 - 20140291863 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

10/02/14 - 20140291864 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

10/02/14 - 20140291865 - Electronic apparatus and fabrication method of the same
A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the...