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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape

Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/17/14 - 20140103538 - Enhanced electrochemical deposition filling
One embodiment is a method for void-free metallic electrofilling inside openings, said method includes: providing a substrate with at least one opening, the substrate includes an electrically conductive surface, including inside the at least one opening; immersing the substrate in an electrolyte contained in an ECD cell, the ECD cell...

04/17/14 - 20140103539 - Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first...

04/17/14 - 20140103540 - Cooling channels in 3dic stacks
An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the...

04/17/14 - 20140103541 - Semiconductor device, circuit substrate, and electronic device
A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the...

04/10/14 - 20140097544 - Side stack interconnection for integrated circuits and the like
In an illustrative embodiment, a plurality of integrated circuits are stacked one on top of the other in a block. A plurality of leads on each integrated circuit is made accessible on a first side of the block. An insulating layer is formed on the first side of the block;...

04/10/14 - 20140097545 - Package structure and method for manufacturing package structure
Disclosed herein is a method for manufacturing a package structure. According to an exemplary embodiment of the present invention, the method for manufacturing a package structure includes: preparing a die having a metal pillar disposed on one surface thereof; bonding the die on the metal plate to allow the metal...

04/10/14 - 20140097546 - Multi-function and shielded 3d interconnects
A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least...

04/03/14 - 20140091473 - Novel three dimensional integrated circuits stacking approach
A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer...

04/03/14 - 20140091474 - Localized high density substrate routing
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can...

04/03/14 - 20140091475 - Method and apparatus to improve reliability of vias
A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second...

04/03/14 - 20140091476 - Directed self assembly of block copolymers to form vias aligned with interconnects
A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the...

04/03/14 - 20140091477 - System and method for chemical-mechanical planarization of a metal layer
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the...

04/03/14 - 20140091478 - Semiconductor device
To provide a semiconductor device having a high efficiency of arranging a TSV, there is provided a semiconductor device which is stacked with a semiconductor chip, and in which the semiconductor chips contiguous each other are electrically connected by plural TSVs, the semiconductor chip includes a core circuit and plural...

03/27/14 - 20140084476 - Thermal dissipation through seal rings in 3dic structure
A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via....

03/27/14 - 20140084477 - Noise attenuation wall
An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart...

03/27/14 - 20140084478 - Mold chase for integrated circuit package assembly and associated techniques and configurations
Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures,...

03/27/14 - 20140084479 - Integrated circuit formed using spacer-like copper deposition
A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing...

03/27/14 - 20140084480 - Semiconductor package substrates having layered circuit segments and related methods
The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the...

03/27/14 - 20140084481 - System and method of novel encapsulated multi metal branch foot structures for advanced back end of line
A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric...

03/27/14 - 20140084482 - Micro device stabilization post
A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom...

03/27/14 - 20140084483 - Package structure and manufacturing method thereof
A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein...

03/27/14 - 20140084484 - Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and...

03/27/14 - 20140084485 - Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a...

03/27/14 - 20140084486 - Reliable interconnect for semiconductor device
A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening...

03/20/14 - 20140077383 - Structure and method of making an offset-trench crackstop that forms an air gap adjacent to a passivated metal crackstop
A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in...

03/20/14 - 20140077384 - Bit cell with triple patterned metal layer structures
An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit...

03/20/14 - 20140077385 - Semiconductor package device having passive energy components
A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor...

03/20/14 - 20140077386 - 3d ic and 3d cis structure
An embodiment integrated circuit includes a first device supporting a first back end of line layer, the first back end of line layer including a first alignment marker, and a second device including a spin-on glass via and supporting a second back end of line layer, the second back end...

03/20/14 - 20140077387 - Semiconductor package and fabrication method thereof
A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers;...

03/20/14 - 20140077388 - Semiconductor device and method of manufacturing the same
A semiconductor device includes a device chip coupled to an electrode chip. The device chip includes a first device electrode on a first substrate, and the electrode chip includes a first pad electrode extending at least partially through a second substrate. The first pad electrode is electrically connected to the...

03/20/14 - 20140077389 - Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening...

03/20/14 - 20140077390 - Electronic apparatus
An electronic apparatus includes a multilayered structure in which a plurality of semiconductor chips provided with semiconductor devices are stacked, penetrating electrodes penetrating the semiconductor chips and electrically connecting the semiconductor devices of the plurality of semiconductor chips, an MEMS chip mounted on the multilayered structure and provided with an...

03/20/14 - 20140077391 - Semiconductor device
A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip...

03/20/14 - 20140077392 - Semiconductor device and method for fabricating the same
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

03/20/14 - 20140077393 - Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which...

03/13/14 - 20140070422 - Semiconductor device with discrete blocks
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device...

03/13/14 - 20140070423 - Tunable composite interposer
A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness....

03/13/14 - 20140070424 - Semiconductor package, method of fabricating the semiconductor package, and interposer structure of the semiconductor package
A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the...

03/13/14 - 20140070425 - Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to...

03/13/14 - 20140070426 - Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure
Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided....

03/13/14 - 20140070427 - Semiconductor device and method of forming conductive thv and rdl on opposite sides of semiconductor die for rdl-to-rdl bonding
A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias...

03/06/14 - 20140061935 - Method for manufacturing a layer arrangement, and a layer arrangement
A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first...

03/06/14 - 20140061936 - Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3d integrated circuits
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate,...

03/06/14 - 20140061937 - Fan-out package comprising bulk metal
A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size...

03/06/14 - 20140061938 - Semiconductor device
A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a...

03/06/14 - 20140061939 - Semiconductor devices having bit line contact plugs and methods of manufacturing the same
A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit...

03/06/14 - 20140061940 - Semiconductor device and method of manufacturing the same
Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger...

03/06/14 - 20140061941 - Semiconductor device and method of manufacturing the same
Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively...

03/06/14 - 20140061942 - Heterogeneous annealing method and device
A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating...

03/06/14 - 20140061943 - Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3d integrated circuits
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate,...

03/06/14 - 20140061944 - Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in fo-wlcsp
A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses...

03/06/14 - 20140061945 - Semiconductor package including a substrate and an interposer
The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality...

03/06/14 - 20140061946 - Semiconductor package including interposer with through-semiconductor vias
The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality...