FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents

Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape



Semiconductor devices and methods of manufacture thereof
02/26/15 - 20150054170 - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface...

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054171 - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns....

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054172 - According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer. The conductive material is embedded into a via which penetrates the semiconductor layer in a thickness direction thereof and is electrically connected to...

Semiconductor package, method of manufacturing semiconductor package and stack type semiconductor package
02/26/15 - 20150054173 - Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base...

Interconnection structure with confinement layer
02/26/15 - 20150054174 - An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive...

Semiconductor device and method for making same
02/26/15 - 20150054175 - One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive...

Stacked via structures and methods of fabrication
02/19/15 - 20150048514 - This disclosure provides systems, methods and apparatus for a stacked via having a top via structure and a bottom via structure. In one aspect, the bottom via structure includes a bottom dielectric layer and a bottom via extending through the bottom dielectric layer. The bottom via includes a bottom metal...

Fabrication of a substrate with an embedded die using projection patterning and associated package configurations
02/19/15 - 20150048515 - Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with...

Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
02/19/15 - 20150048516 - An integrated circuit that includes a substrate, a metal layer over the substrate and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer...

Crack stopping structure in wafer level packaging (wlp)
02/19/15 - 20150048517 - Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the...

Metal pad offset for multi-layer metal layout
02/19/15 - 20150048518 - A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads....

Semiconductor devices with through via electrodes, methods of fabricaring the same, memory cards including the same, and electronic systems including the same
02/19/15 - 20150048519 - A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the...

3d packages and methods for forming the same
02/12/15 - 20150041987 - Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device...

Ultra high performance interposer
02/12/15 - 20150041988 - An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced...

Semiconductor appratus and semiconductor system using the same
02/12/15 - 20150041989 - A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. The first path setting unit connects a first chip circuit to a first input/output terminal, and the second through...

Wiring substrate and manufacturing method therefor
02/12/15 - 20150041990 - A wiring substrate includes a semiconductor substrate, an insulator and a plurality of columnar conductors. The insulator is made of an insulating material filled in a groove or hole provided in the semiconductor substrate. The plurality of columnar conductors are filled in grooves or holes provided in the insulator. The...

Semiconductor device
02/12/15 - 20150041991 - The reliability of a semiconductor device is improved. A semiconductor device in accordance with one embodiment has a plurality of stacked semiconductor chips. Further, a plurality of inter-chip connection members (conductive members) arranged between the semiconductor chips, and establishing an electrical connection between the semiconductor chips include a first inter-chip...

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
02/12/15 - 20150041992 - A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the...

Semiconductor device and manufacturing method thereof
02/05/15 - 20150035161 - A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric...

Inductive device that includes conductive via and metal layer
02/05/15 - 20150035162 - An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer...

Semiconductor package and method of fabricating the same
02/05/15 - 20150035163 - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a...

Semiconductor package and method of fabricating the same
02/05/15 - 20150035164 - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and...

Interconnection structure of semiconductor device
02/05/15 - 20150035165 - An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second...

Method for manufacturing a semiconductor component and structure
02/05/15 - 20150035166 - A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. The mold compound is separated to form singulated semiconductor components. A portion of at least one leadframe lead is exposed and an electrically conductive material is...

Tft array substrate and manufacturing method thereof, and display device
02/05/15 - 20150035167 - The present invention provides a TFT array substrate, the TFT array substrate includes: a first metal layer including a first common electrode line, a second metal layer including a second common electrode line, and a third common electrode line, wherein the third common electrode line is electrically connected with at...

Semiconductor device having through-substrate vias
02/05/15 - 20150035168 - A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at...

Via structure for three-dimensional circuit integration
02/05/15 - 20150035169 - Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer....

Integrated circuits having device contacts and methods for fabricating the same
01/29/15 - 20150028490 - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of...

Improved sicoh hardmask with graded transition layers
01/29/15 - 20150028491 - A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded...

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages including same, modules including the same, and systems including the same
01/29/15 - 20150028492 - Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure...

Semiconductor device and manufacturing method thereof
01/29/15 - 20150028493 - A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less...

Integrated circuit device having through-silicon-via structure and method of manufacturing the integrated circuit device
01/29/15 - 20150028494 - Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via...

Soc design with critical technology pitch alignment
01/29/15 - 20150028495 - An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v...

Front-to-back bonding with through-substrate via (tsv)
01/22/15 - 20150021784 - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second...

Hybrid bonding with through substrate via (tsv)
01/22/15 - 20150021785 - Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material...

Bonded semiconductor structures
01/22/15 - 20150021786 - A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is...

Semiconductor package
01/22/15 - 20150021787 - Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed on the plurality of first semiconductor chips. The plurality of first semiconductor chips comprises a first semiconductor chip group and a second semiconductor chip group. The...

Multi-function and shielded 3d interconnects
01/22/15 - 20150021788 - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least...

Hybrid bonding with through substrate via (tsv)
01/22/15 - 20150021789 - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second...

Semiconductor die and package with source down and sensing configuration
01/15/15 - 20150014858 - A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source...

On-chip interconnects with reduced capacitance and method of fabrication thereof
01/15/15 - 20150014859 - An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric loss of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, which reduces the...

Semiconductor chip connecting semiconductor package
01/15/15 - 20150014860 - A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one...

Embedded structures for package-on-package architecture
01/15/15 - 20150014861 - Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first...

Multiple-patterned semiconductor device
01/08/15 - 20150008585 - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the...

Semiconductor device and manufacturing method thereof
01/08/15 - 20150008586 - A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover...

Semiconductor device and manufacturing method thereof
01/08/15 - 20150008587 - A fan-out package includes a molding compound, a conductive plug and a stress buffer. The conductive plug is in the molding compound. The stress buffer is between the conductive plug and the molding compound. The stress buffer has a coefficient of thermal expansion (CTE). The CTE of the stress buffer...

Semiconductor chip and stacked type semiconductor package having the same
01/08/15 - 20150008588 - The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first...

Method of forming stacked-layer wiring, stacked-layer wiring, and electronic element
01/08/15 - 20150008589 - A method of forming a stacked-layer wiring includes forming first wettability variable layer on a substrate using material that changes surface energy by energy application; forming first conductive layer in or on the first wettability variable layer; forming second wettability variable layer on the first wettability variable layer using material...

Semiconductor device
01/08/15 - 20150008590 - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space...

Semiconductor device and manufacturing method of the same
01/08/15 - 20150008591 - Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with...

Package assembly for embedded die and associated techniques and configurations
01/01/15 - 20150001731 - Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment, an apparatus includes a package assembly comprising a die attach layer, a die coupled with the die attach layer, the die having an active side including active devices...

Silicon space transformer for ic packaging
01/01/15 - 20150001732 - An apparatus includes at least a first integrated circuit (IC) and a wafer-fabricated space transformer (ST). The IC includes bonding pads of a first inter-pad pitch on a bottom surface. The ST includes a top surface having bonding pads of the first inter-pad pitch, and at least a portion of...

Reliable microstrip routing for electronics components
01/01/15 - 20150001733 - Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of...

Conductive line patterning
01/01/15 - 20150001734 - A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a...

Multipatterning via shrink method using ald spacer
01/01/15 - 20150001735 - A method of manufacturing a semiconductor device an include forming an first low temperature oxide (LTO) layer over an organic planarization layer (OPL) layer, forming a primary via pattern in the LTO layer to partially expose the OPL layer, forming a conformal second LTO layer over the primary via pattern...

Integration of optical components in integrated circuits
12/25/14 - 20140374915 - Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first...

Tsv interconnect structure and manufacturing method thereof
12/25/14 - 20140374916 - A method for forming a through-substrate-via structure includes forming a via hole in a substrate, depositing a conductive material in the via hole, forming an annular groove in the substrate surrounding the conductive material, and depositing a dielectric material in the annular groove with overhang portions of the deposited dielectric...

Component in the form of a wafer level package and method for manufacturing same
12/25/14 - 20140374917 - A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top...

Asic element including a via
12/25/14 - 20140374918 - In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear...

Method for producing contact areas on a semiconductor substrate
12/25/14 - 20140374919 - Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask....

Cd control
12/25/14 - 20140374920 - A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed...

Semiconductor packages including heat diffusion vias and interconnection vias
12/18/14 - 20140367860 - A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate...

Semiconductor device and semiconductor device fabrication method
12/18/14 - 20140367861 - A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via....

Semiconductor device with internal substrate contact and method of production
12/18/14 - 20140367862 - The semiconductor device comprises a substrate (1) of semiconductor material, a contact hole (2) reaching from a surface (10) into the substrate, and a contact metallization (12) arranged in the contact hole, so that the contact metallization forms an internal substrate contact (4) on the semiconductor material at least in...

Semiconductor device
12/18/14 - 20140367863 - A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor...

Seal ring structure and method of forming the same
12/11/14 - 20140361438 - A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric...

Packaging substrate and method for manufacturing same
12/11/14 - 20140361439 - A packaging substrate includes a first wiring layer, a first dielectric layer formed on the first wiring layer, a second wiring layer formed on the first dielectric layer, and a number of copper pillar bumps. Each copper pillar bump includes a base portion and a protruding portion. The base portion...

Process for producing at least one through-silicon via with improved heat dissipation, and corresponding three-dimensional integrated structure
12/11/14 - 20140361440 - A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on...

Manganese oxide hard mask for etching dielectric materials
12/04/14 - 20140353839 - A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese...

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
12/04/14 - 20140353840 - A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include...

Method for forming an electrical connection between metal layers
12/04/14 - 20140353841 - A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first...

Wide pin for improved circuit routing
12/04/14 - 20140353842 - Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater...

Circuit structures and methods of fabrication with enhanced contact via electrical connection
12/04/14 - 20140353843 - Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact...

Array substrate, display device and method for fabricating array substrate
12/04/14 - 20140353844 - An array substrate, a display device and a method for fabricating an array substrate are disclosed. The array substrate comprises at least two GOA elements and a STV signal line, a transmission channel between two of the adjacent GOA elements is formed by a via hole and a gate metal...

Semiconductor device and production method therefor
12/04/14 - 20140353845 - A production method for a semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided. In the production method, the step of forming each of the interconnection layers of the multi-level interconnection structure includes an interconnection forming...

Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
12/04/14 - 20140353846 - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant...