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Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape



Chip package and method for forming the same
03/26/15 - 20150084205 - A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate...

Semiconductor device and method of forming dual fan-out semiconductor package
03/26/15 - 20150084206 - A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive...

Embedded semiconductor device package and method of manufacturing thereof
03/26/15 - 20150084207 - A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are...

Connection member, semiconductor device, and stacked structure
03/26/15 - 20150084208 - A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via,...

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
03/19/15 - 20150076704 - In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first...

Reduced capacitance interlayer structures and fabrication methods
03/19/15 - 20150076705 - Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and...

Through-silicon via unit cell and methods of use
03/19/15 - 20150076706 - Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to...

Integrated circuit via structure and method of fabrication
03/19/15 - 20150076707 - A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of...

Semiconductor device
03/19/15 - 20150076708 - A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less...

Semiconductor device and manufacturing method for the same
03/19/15 - 20150076709 - A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed...

Integrated semiconductor device and wafer level method of fabricating the same
03/19/15 - 20150076710 - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate,...

Conductive ink for filling vias
03/19/15 - 20150076711 - Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a...

Method for forming through wafer vias
03/12/15 - 20150069618 - A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and spaces, bonding a slab or wafer of glass to the template substrate, and melting the glass so that it flows into...

3dic interconnect apparatus and method
03/12/15 - 20150069619 - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric...

Semiconductor devices and methods of forming same
03/12/15 - 20150069620 - Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor device, the method including forming a first conductive feature over a substrate, forming a dielectric layer over the conductive feature, and forming an opening through...

Embedded electronic packaging and associated methods
03/12/15 - 20150069621 - An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings....

Via definition scheme
03/12/15 - 20150069622 - A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric...

Integrated fan-out structure with guiding trenches in buffer layer
03/12/15 - 20150069623 - A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein...

Recessed semiconductor die stack
03/12/15 - 20150069624 - Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second...

Ultra-thin metal wires formed through selective deposition
03/12/15 - 20150069625 - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process....

Chip package, chip package module based on the chip package, and method of manufacturing the chip package
03/12/15 - 20150069626 - A chip package is formed of a complex substrate and a chip. The complex substrate includes a core plate, a thermally-conductive insulated layer, and a through hole running through the core plate and the thermally-conductive insulated layer. The core plate is fixed to the core plate and buried into the...

Interposer wafer and method of manufacturing same
03/12/15 - 20150069627 - In one embodiment, a method of manufacturing an interposer wafer includes forming a first hole having a first depth on a first main surface of a semiconductor wafer. The method further includes forming a second hole having a second depth on the first main surface of the semiconductor wafer before...

Semiconductor package and method of fabricating the same
03/12/15 - 20150069628 - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces...

Hybrid package transmission line circuits
03/12/15 - 20150069629 - “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a...

Device with through-substrate via structure and method for forming the same
03/05/15 - 20150061147 - A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the...

3d ic with serial gate mos device, and method of making the 3d ic
03/05/15 - 20150061148 - A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second...

Packages, packaging methods, and packaged semiconductor devices
03/05/15 - 20150061149 - Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a...

Stacked semiconductor chip device with phase change material
03/05/15 - 20150061150 - Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket...

Package structure having silicon through vias connected to ground potential
03/05/15 - 20150061151 - A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality...

Package module with offset stack device
03/05/15 - 20150061152 - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections...

Semiconductor device and method for manufacturing the same
03/05/15 - 20150061153 - According to one embodiment, a semiconductor device includes a semiconductor layer including a first region and a second region, a first insulating layer provided above the semiconductor layer, an extending first contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a first element provided...

Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same
03/05/15 - 20150061154 - A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls...

Semiconductor devices and methods of fabricating the same
03/05/15 - 20150061155 - The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented....

Pad solutions for reliable bonds
03/05/15 - 20150061156 - A bonding pad and a method of manufacturing a bonding pad are presented. The method includes providing a substrate prepared with circuits component and an interlevel dielectric (ILD) layer with interconnects. A final passivation level is formed on the substrate surface and includes a pad opening. A wire bond in...

Semiconductor devices and methods of manufacture thereof
02/26/15 - 20150054170 - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface...

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054171 - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns....

Semiconductor device and method of manufacturing the same
02/26/15 - 20150054172 - According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer. The conductive material is embedded into a via which penetrates the semiconductor layer in a thickness direction thereof and is electrically connected to...

Semiconductor package, method of manufacturing semiconductor package and stack type semiconductor package
02/26/15 - 20150054173 - Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base...

Interconnection structure with confinement layer
02/26/15 - 20150054174 - An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive...

Semiconductor device and method for making same
02/26/15 - 20150054175 - One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive...

Stacked via structures and methods of fabrication
02/19/15 - 20150048514 - This disclosure provides systems, methods and apparatus for a stacked via having a top via structure and a bottom via structure. In one aspect, the bottom via structure includes a bottom dielectric layer and a bottom via extending through the bottom dielectric layer. The bottom via includes a bottom metal...

Fabrication of a substrate with an embedded die using projection patterning and associated package configurations
02/19/15 - 20150048515 - Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with...

Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
02/19/15 - 20150048516 - An integrated circuit that includes a substrate, a metal layer over the substrate and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer...

Crack stopping structure in wafer level packaging (wlp)
02/19/15 - 20150048517 - Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the...

Metal pad offset for multi-layer metal layout
02/19/15 - 20150048518 - A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads....

Semiconductor devices with through via electrodes, methods of fabricaring the same, memory cards including the same, and electronic systems including the same
02/19/15 - 20150048519 - A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the...

3d packages and methods for forming the same
02/12/15 - 20150041987 - Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device...

Ultra high performance interposer
02/12/15 - 20150041988 - An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced...

Semiconductor appratus and semiconductor system using the same
02/12/15 - 20150041989 - A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. The first path setting unit connects a first chip circuit to a first input/output terminal, and the second through...

Wiring substrate and manufacturing method therefor
02/12/15 - 20150041990 - A wiring substrate includes a semiconductor substrate, an insulator and a plurality of columnar conductors. The insulator is made of an insulating material filled in a groove or hole provided in the semiconductor substrate. The plurality of columnar conductors are filled in grooves or holes provided in the insulator. The...

Semiconductor device
02/12/15 - 20150041991 - The reliability of a semiconductor device is improved. A semiconductor device in accordance with one embodiment has a plurality of stacked semiconductor chips. Further, a plurality of inter-chip connection members (conductive members) arranged between the semiconductor chips, and establishing an electrical connection between the semiconductor chips include a first inter-chip...

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
02/12/15 - 20150041992 - A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the...

Semiconductor device and manufacturing method thereof
02/05/15 - 20150035161 - A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric...

Inductive device that includes conductive via and metal layer
02/05/15 - 20150035162 - An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer...

Semiconductor package and method of fabricating the same
02/05/15 - 20150035163 - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a...

Semiconductor package and method of fabricating the same
02/05/15 - 20150035164 - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and...

Interconnection structure of semiconductor device
02/05/15 - 20150035165 - An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second...

Method for manufacturing a semiconductor component and structure
02/05/15 - 20150035166 - A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. The mold compound is separated to form singulated semiconductor components. A portion of at least one leadframe lead is exposed and an electrically conductive material is...

Tft array substrate and manufacturing method thereof, and display device
02/05/15 - 20150035167 - The present invention provides a TFT array substrate, the TFT array substrate includes: a first metal layer including a first common electrode line, a second metal layer including a second common electrode line, and a third common electrode line, wherein the third common electrode line is electrically connected with at...

Semiconductor device having through-substrate vias
02/05/15 - 20150035168 - A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at...

Via structure for three-dimensional circuit integration
02/05/15 - 20150035169 - Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer....

Integrated circuits having device contacts and methods for fabricating the same
01/29/15 - 20150028490 - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of...

Improved sicoh hardmask with graded transition layers
01/29/15 - 20150028491 - A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded...

Semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, packages including same, modules including the same, and systems including the same
01/29/15 - 20150028492 - Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure...

Semiconductor device and manufacturing method thereof
01/29/15 - 20150028493 - A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less...

Integrated circuit device having through-silicon-via structure and method of manufacturing the integrated circuit device
01/29/15 - 20150028494 - Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via...

Soc design with critical technology pitch alignment
01/29/15 - 20150028495 - An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v...

Front-to-back bonding with through-substrate via (tsv)
01/22/15 - 20150021784 - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second...

Hybrid bonding with through substrate via (tsv)
01/22/15 - 20150021785 - Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material...

Bonded semiconductor structures
01/22/15 - 20150021786 - A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is...

Semiconductor package
01/22/15 - 20150021787 - Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed on the plurality of first semiconductor chips. The plurality of first semiconductor chips comprises a first semiconductor chip group and a second semiconductor chip group. The...

Multi-function and shielded 3d interconnects
01/22/15 - 20150021788 - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least...

Hybrid bonding with through substrate via (tsv)
01/22/15 - 20150021789 - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second...