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Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape



Word line coupling prevention using 3d integrated circuit
05/28/15 - 20150145139 - A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to...

Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
05/28/15 - 20150145140 - Wafer to carrier adhesion without mechanical adhesion for formation of an IC. In such formation, an apparatus has a bottom surface of a substrate abutting a top surface of a support platform without adhesive therebetween. A material is disposed around the substrate and on the top surface of the support...

Multiple bond via arrays of different wire heights on a same substrate
05/28/15 - 20150145141 - An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed...

Mechanisms for forming package structure
05/28/15 - 20150145142 - In accordance with some embodiments, a package structure and a method for forming a package structure are provided. The package structure includes a semiconductor die and a molding compound partially or completely encapsulating the semiconductor die. The package structure also includes a through package via in the molding compound. The...

Placement of monolithic inter-tier vias (mivs) within monolithic three dimensional (3d) integrated circuits (ics) (3dics) using clustering to increase usable whitespace
05/28/15 - 20150145143 - Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included...

Use of a conformal coating elastic cushion to reduce through silicon vias (tsv) stress in 3-dimensional integration
05/28/15 - 20150145144 - Integrated circuit assemblies, as well as methods for creating the same, are provided. The integrated circuit assembly includes a first chip and a second chip, including respective face surfaces, wherein the first chip and the second chip are bonded in a face-against-face contact configuration. The integrated circuit assembly includes a...

Ic embedded substrate and method of manufacturing the same
05/28/15 - 20150145145 - Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The...

Methods of exposing conductive vias of semiconductor devices and related semiconductor devices
05/28/15 - 20150145146 - Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the...

Self-alignment for redistribution layer
05/21/15 - 20150137382 - An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate...

Thin substrate and mold compound handling using an electrostatic-chucking carrier
05/21/15 - 20150137383 - Thin substrates and mold compound handling is described using an electrostatic-chucking carrier. In one example, a first part of a plurality of silicon chip packages is formed on a front side of a silicon substrate wafer at a first processing station. An a carrier wafer of an electrostatic chuck is...

Semicondutor device with through-silicon via-less deep wells
05/21/15 - 20150137384 - Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers....

Integrated circuits with close electrical contacts and methods for fabricating the same
05/21/15 - 20150137385 - Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the...

Semiconductor device
05/21/15 - 20150137386 - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply...

Integrated circuit device including through-silicon via structure and method of manufacturing the same
05/21/15 - 20150137387 - An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer....

Semiconductor devices
05/21/15 - 20150137388 - A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced...

Semiconductor package and manufacturing method thereof
05/14/15 - 20150130070 - The present disclosure provides a semiconductor structure. The semiconductor structure includes a carrier, a first redistribution layer (RDL) over the carrier, a semiconductor die over the first RDL, an adhesive layer between the semiconductor die and the first RDL, and a molding compound encapsulating the first RDL, the semiconductor die,...

Semiconductor package comprising a transistor chip module and a driver chip module and a method for fabricating the same
05/14/15 - 20150130071 - A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a...

Stacking of multiple dies for forming three dimensional integrated circuit (3dic) structure
05/14/15 - 20150130072 - The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the...

Interconnect structure and methods of forming same
05/14/15 - 20150130073 - A method comprises depositing a first dielectric layer over a substrate, forming a first metal line and a second metal line in the first dielectric layer, wherein the first metal line and the second metal line are separated from each other by a width approximately equal to a width of...

Semiconductor device and method for forming the same
05/14/15 - 20150130074 - A semiconductor device may include: a wiring layer formed over an interlayer dielectric layer; and one or more wiring characteristic control parts extended from the wiring layer into the interlayer dielectric layer. The bottom of the one or more wiring characteristic control parts may be positioned at a higher level...

Semiconductor package having magnetic substance and related equipment
05/14/15 - 20150130075 - Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be...

Semiconductor module and method for manufacturing the same
05/14/15 - 20150130076 - A semiconductor module of the present invention includes: a semiconductor element having a first main surface and a second main surface facing the first main surface, the semiconductor element including a front surface electrode and a back surface electrode on the first main surface and the second main surface, respectively;...

Staged via formation from both sides of chip
05/14/15 - 20150130077 - A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad...

Semiconductor chip and semiconductor package having same
05/14/15 - 20150130078 - A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member...

Semiconductor element
05/14/15 - 20150130079 - A multilayer device has a resin layer, a semiconductor device positioned in the resin layer and including an electronic component and a passivation layer having an opening exposing an electrode of the electronic component, an intermediate layer including metal layers and formed in the opening of the passivation layer such...

Semiconductor device structures including damascene structures
05/14/15 - 20150130080 - A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer...

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
05/14/15 - 20150130081 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also...

Semiconductor package and method for manufacturing the same
05/07/15 - 20150123283 - A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each...

Semiconductor devices having through-electrodes and methods for fabricating the same
05/07/15 - 20150123284 - A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad...

Chip device packages and fabrication methods thereof
05/07/15 - 20150123285 - A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate...

Semiconductor device and method of fabricating the same
05/07/15 - 20150123286 - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a...

Semiconductor device and method for manufacturing a semiconductor device
04/30/15 - 20150115458 - A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip...

Integrated circuit structure with metal cap and methods of fabrication
04/30/15 - 20150115459 - The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end;...

Integrated circuit structure with through-semiconductor via
04/30/15 - 20150115460 - The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer;...

Semiconductor structure and method for forming the same
04/30/15 - 20150115461 - A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A...

Integrated circuit device
04/30/15 - 20150115462 - An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above...

Stacked semiconductor devices
04/30/15 - 20150115463 - A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that...

Chip on package structure and method
04/30/15 - 20150115464 - A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two...

Semiconductor device and method of balancing surfaces of an embedded pcb unit with a dummy copper pattern
04/30/15 - 20150115465 - A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over...

Semiconductor package devices including interposer openings for flowable heat transfer member
04/30/15 - 20150115466 - A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and...

Package-on-package device
04/30/15 - 20150115467 - The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The...

Semiconductor package having magnetic connection member
04/30/15 - 20150115468 - Provided is a semiconductor package including a wiring substrate having top and bottom surfaces facing each other. A first semiconductor chip is disposed on the wiring substrate in a flip-chip manner. The first semiconductor chip has a first surface facing the top surface of the wiring substrate and a second...

Semiconductor substrate and method for manufacturing the same
04/30/15 - 20150115469 - A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer...

Chip on package structure and method
04/30/15 - 20150115470 - A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two...

Process to achieve contact protrusion for single damascene via
04/30/15 - 20150115471 - The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend...

Sensor device packages and related fabrication methods
04/23/15 - 20150108653 - Sensor device packages and related fabrication methods are provided. An exemplary sensor device package includes a first structure having a sensing arrangement thereon, a second structure having circuitry thereon, and a conductive structure within the first structure and coupled to the circuitry to provide an electrical connection to the circuitry...

Reliable passivation layers for semiconductor devices
04/23/15 - 20150108654 - Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the...

Semiconductor device and method of manufacturing the same
04/23/15 - 20150108655 - Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of...

Stacked die package
04/23/15 - 20150108656 - Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted...

Electronic device
04/23/15 - 20150108657 - A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at...

Self-aligned nano-structures
04/23/15 - 20150108658 - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or...

3d-packages and methods for forming the same
04/23/15 - 20150108659 - A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die...

Stacked memory with interface providing offset interconnects
04/23/15 - 20150108660 - A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face...

Semiconductor package
04/16/15 - 20150102495 - A semiconductor package is provided. The semiconductor package includes a substrate, a first pad, a second, a first conductive element, a surface mount device, a first bonding wire and a molding compound layer. The first pad, the second pad, and the first conductive element are formed on the substrate. The...

Novel method to make high aspect ratio vias for high performance devices interconnection application
04/16/15 - 20150102496 - Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin....

Integrated circuit devices including a through-silicon via structure and methods of fabricating the same
04/16/15 - 20150102497 - Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and...

Carrier-bonding methods and articles for semiconductor and interposer processing
04/16/15 - 20150102498 - A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during...

Integrated circuit chip comprising electronic device and electronic system
04/16/15 - 20150102499 - An electronic device includes a substrate wafer made of many layers of an insulating material and including an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer further includes a metal plate that is integrated into the substrate wafer...

Electronic system comprising stacked electronic devices comprising integrated-circuit chips
04/16/15 - 20150102500 - An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second...

Semiconductor device for battery power voltage control
04/16/15 - 20150102501 - A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other,...

Integrated fan-out structure with openings in buffer layer
04/16/15 - 20150102502 - A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel...

Semiconductor device and manufacturing method thereof
04/16/15 - 20150102503 - A fan out package includes a molding compound, a conductive plug in the molding compound, a dielectric covering the molding compound and a portion of the conductive plug, and an interconnect disposed over the dielectric and contacted with the conductive plug, wherein a width of the interconnect contacting the conductive...

Multi-die stack structure
04/09/15 - 20150097296 - A multi-die stack structure including N dies stacked vertically is described. N is an integer larger than or equal to 2. Each die includes N die-specific input pads, wherein a specific pad among the N pads is for the input of the die. The specific pad of each die above...

Semiconductor article having a zig-zag guard ring
04/09/15 - 20150097297 - A semiconductor article which includes a semiconductor base portion including a semiconductor material; a back end of the line (BEOL) wiring portion on the semiconductor base portion and comprising a plurality of wiring layers having metallic wiring and insulating material, said BEOL wiring portion excluding a semiconductor material; and a...

Semiconductor substrate assembly
04/09/15 - 20150097298 - A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on...

3d device packaging using through-substrate pillars
04/02/15 - 20150091178 - A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second...

Semiconductor device with via bar
04/02/15 - 20150091179 - A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of...

Package on wide i/o silicon
04/02/15 - 20150091180 - An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a...

Self-aligned vias formed using sacrificial metal caps
04/02/15 - 20150091181 - A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric...

Die assembly on thin dielectric sheet
04/02/15 - 20150091182 - A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to...

Arrangement and method for manufacturing the same
04/02/15 - 20150091183 - An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing...

Semiconductor memory apparatus
04/02/15 - 20150091184 - A semiconductor memory apparatus includes: a power distribution line disposed over a circumferential portion of a device formation region; a guard ring formed to surround the device formation region outside of the power distribution line; and one or more power reinforcement parts configured to electrically couple an edge part of...

Semiconductor device and method for forming the same
04/02/15 - 20150091185 - A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing...

Interconnection structure, semiconductor device, and method of manufacturing the same
04/02/15 - 20150091186 - A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part...

3d device packaging using through-substrate posts
04/02/15 - 20150091187 - A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a...

Semiconductor device having dummy cell array
04/02/15 - 20150091188 - A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines,...

Apparatuses and methods enabling concurrent communication
04/02/15 - 20150091189 - Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die....

Super-self-aligned contacts and method for making the same
04/02/15 - 20150091190 - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each...

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