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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration > Via (interconnection Hole) Shape

Via (interconnection Hole) Shape

Via (interconnection Hole) Shape patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/31/14 - 20140210097 - Integrated circuit package with active interposer
An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements...

07/31/14 - 20140210098 - Techniques for enhancing fracture resistance of interconnects
Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of...

07/31/14 - 20140210099 - Packaged semiconductor devices and packaging methods
Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A...

07/31/14 - 20140210100 - Conductive line routing for multi-patterning technology
A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the...

07/31/14 - 20140210101 - Die package with openings surrounding end-portions of through package vias (tpvs) and package on package (pop) using the die package
Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs....

07/31/14 - 20140210102 - Systems and methods for producing flat surfaces in interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure...

07/31/14 - 20140210103 - Mram with sidewall protection and method of fabrication
BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited...

07/31/14 - 20140210104 - Non-lithographic formation of three-dimensional conductive elements
A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably...

07/24/14 - 20140203445 - Mitigating pattern collapse
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal...

07/24/14 - 20140203446 - Through silicon via device having low stress, thin film gaps and methods for forming the same
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack...

07/24/14 - 20140203447 - Metal lines having etch-bias independent height
A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern...

07/24/14 - 20140203448 - Random coded integrated circuit structures and methods of making random coded integrated circuit structures
Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material...

07/24/14 - 20140203449 - Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and...

07/24/14 - 20140203450 - Semiconductor package and method of fabricating the same
A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of...

07/24/14 - 20140203451 - Electronic device package and packaging substrate for the same
The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode...

07/24/14 - 20140203452 - Active chip on carrier or laminated chip having microelectronic element embedded therein
A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to...

07/24/14 - 20140203453 - Air-dielectric for subtractive etch line and via metallization
A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one...

07/24/14 - 20140203454 - Semiconductor device and semiconductor module
A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit. An analog ground layer is stacked on...

07/24/14 - 20140203455 - Feature patterning methods and structures thereof
Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and...

07/17/14 - 20140197544 - Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand,...

07/17/14 - 20140197545 - Non-cylindrical conducting shapes in multilayer laminated substrate cores
Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern...

07/17/14 - 20140197546 - Pad structures and wiring structures in a vertical type semiconductor device
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart...

07/10/14 - 20140191407 - Dielectric posts in metal layers
A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%....

07/10/14 - 20140191408 - Backside metal ground plane with improved metal adhesion and design structures
A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a...

07/10/14 - 20140191409 - Forming vias and trenches for self-aligned contacts in a semiconductor structure
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper...

07/10/14 - 20140191410 - Damage monitor structure for through-silicon via (tsv) arrays
Described herein are techniques related to techniques for monitoring damage to circuitry or structure neighboring one or more through-silicon vias (TSVs) caused by TSV-related processing. Additionally, techniques for confining diffusion of moisture or chemical from one or more TSVs during TSV-related processing are also described. This Abstract is submitted with...

07/10/14 - 20140191411 - Interconnection structures and fabrication method thereof
A method is provided for fabricating an interconnection structure. The method includes providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices, and a barrier layer on the metal layer. The method also includes forming a dielectric layer on the substrate; and forming an...

07/10/14 - 20140191412 - Interconnection structures and fabrication method thereof
A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive...

07/10/14 - 20140191413 - Method for producing a semiconductor device comprising a conductor layer in the semiconductor body and semiconductor body
A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally...

07/10/14 - 20140191414 - Semiconductor device and method for fabricating the same
A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and...

07/10/14 - 20140191415 - Methods for etching through-wafer vias in a wafer
Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma...

07/10/14 - 20140191416 - Semiconductor device
A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires...

07/03/14 - 20140183752 - Semiconductor assembly with built-in stopper, semiconductor device and build-up circuitry and method of making the same
The present invention relates to a semiconductor assembly with a built-in stopper and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper...

07/03/14 - 20140183753 - Fabricating polysilicon mos devices and passive esd devices
A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is...

07/03/14 - 20140183754 - Through-vias and methods of forming the same
An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring....

07/03/14 - 20140183755 - Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes a carrier having a mounting area and at least a grounding pad; a substrate body having opposite first and second surfaces and a plurality of conductive vias each having a first end exposed from the first surface and a second end opposite to...

07/03/14 - 20140183756 - Three-dimensional semiconductor device
A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second...

07/03/14 - 20140183757 - Semiconductor device including passivation layer encapsulant
A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a...

06/26/14 - 20140175663 - Semiconductor device having conductive via and manuacturing process
In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least...

06/26/14 - 20140175664 - Dielectric solder barrier for semiconductor devices
The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from...

06/26/14 - 20140175665 - Chip package using interposer substrate with through-silicon vias
A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon...

06/26/14 - 20140175666 - Integrated circuit device with stitched interposer
Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than...

06/26/14 - 20140175667 - Semiconductor integrated circuit and semiconductor system with the same
A semiconductor integrated circuit may include a plurality of semiconductor chips configured to be stacked in three dimensions, a first group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for density extension of the semiconductor integrated circuit, and a second group...

06/26/14 - 20140175668 - Semiconductor integrated circuit
A semiconductor integrated circuit includes: a first interface block configured to transmit and receive signals within the same chip; a second interface block configured to transmit and receive signals to and from different semiconductor chips; and a switching block configured to select a signal path in which the signal transmission...

06/26/14 - 20140175669 - Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith
Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a...

06/26/14 - 20140175670 - Stacked die package
The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a...

06/19/14 - 20140167280 - Semiconductor device
A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure....

06/19/14 - 20140167281 - Stack type semiconductor circuit with impedance calibration
A stack type semiconductor circuit includes a plurality of semiconductor chips stacked therein, wherein the plurality of semiconductor chips are configured to share impedance calibration information. The plurality of semiconductor chips include at least one resistance value of an external resistor and an impedance calibration signal as the impedance calibration...

06/19/14 - 20140167282 - Semiconductor device
A semiconductor device includes a multilayer substrate, a semiconductor element secured to an upper surface of the multilayer substrate, a first metal pattern located on a portion of a lower surface of the multilayer substrate, a dielectric having a higher permittivity than the multilayer substrate and located on the lower...

06/19/14 - 20140167283 - Interconnect structure and fabrication method
A carbon-containing dielectric layer can be formed on a substrate. A protective layer can be formed on the carbon-containing dielectric layer to prevent carbon loss from the carbon-containing dielectric layer by performing a surface treatment to the carbon-containing dielectric layer using a gas at least containing silicon and hydrogen. A...

06/19/14 - 20140167284 - Interconnect structure and forming method thereof
An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming an interlayer dielectric layer on the semiconductor substrate; forming a conductive layer on the interlayer dielectric layer; forming a groove in the conductive layer and the...

06/19/14 - 20140167285 - Interconnect structure and fabrication method
An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed in the substrate. At least two porous films can be formed over the substrate and can include a first porous film having a first pore size, and a second porous film having a second...

06/19/14 - 20140167286 - Semiconductor device
A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to...

06/19/14 - 20140167287 - Microelectronic package with terminals on dielectric mass
A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to...

06/19/14 - 20140167288 - Semiconductor device including contact plug and method of manufacturing the same
A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer,...

06/19/14 - 20140167289 - Semiconductor device having through electrode and method of fabricating the same
A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode...