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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/17/14 - 20140103532 - Chip-level humidity protection
An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish...

04/17/14 - 20140103533 - Extremely thin semiconductor-on-insulator with back gate contact
A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After...

04/17/14 - 20140103534 - Electrochemical deposition on a workpiece having high sheet resistance
A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature, depositing a first conductive layer in the feature, wherein the sheet resistance of the first conductive layer is greater than 10 ohm/square, depositing a second conductive layer in the feature...

04/17/14 - 20140103535 - Stub minimization for assemblies without wirebonds to package substrate
A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction...

04/17/14 - 20140103536 - Semiconductor device
A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section...

04/17/14 - 20140103537 - Nitride semiconductor device
A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film...

04/10/14 - 20140097543 - Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed
Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a...

04/03/14 - 20140091472 - Semiconductor device and manufacturing method of the same
A semiconductor element includes a plurality of electrodes on a main surface, a sealing resin covering at least a part of a side surface of the semiconductor element, and a first insulating layer formed on the main surface of the semiconductor element, a part of the side surface of the...

03/27/14 - 20140084475 - Semiconductor package substrates having pillars and related methods
The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces....

03/20/14 - 20140077380 - Bit cell with double patterned metal layer structures
An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure...

03/20/14 - 20140077381 - Semiconductor device and method of forming fo-wlcsp with multiple encapsulants
A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first...

03/20/14 - 20140077382 - Semiconductor packages having warpage compensation
A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from...

03/13/14 - 20140070420 - Chip to package interface
In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer....

03/13/14 - 20140070421 - Integrated circuit package
An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides...

03/06/14 - 20140061932 - Methods and apparatus for package on package structures
A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a...

03/06/14 - 20140061933 - Wire bond splash containment
A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and...

03/06/14 - 20140061934 - Semiconductor device
A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the...

02/27/14 - 20140054783 - Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending...

02/27/14 - 20140054784 - Integrated circuit connector access region and method for making
A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A...

02/27/14 - 20140054785 - Chip package structure and method for manufacturing same
A chip package structure includes a first wiring layer, a first solder mask layer, a chip and a plurality of third contact pads. The third contact pads are formed on the first wiring layer. The third contact pads and the first wiring layer are unitarily formed. The first solder mask...

02/27/14 - 20140054786 - Chip package and method for forming the same
An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess...

02/27/14 - 20140054787 - Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the...

02/27/14 - 20140054788 - Method for fabricating nanogap electrodes, nanogap electrodes array, and nanodevice with the same
A substrate 1 having metal layers 2A and 2B arranged to form a gap is dipped in an electroless plating solution mixed an electrolyte solution including metal ions with a reducing agent and a surfactant. Metal ions are reduced by the reducing agent to be precipitated on the metal layers...

02/20/14 - 20140048944 - Interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device...

02/20/14 - 20140048945 - Nonvolatile memory device and a method for fabricating the same
A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and...

02/13/14 - 20140042632 - Semiconductor device and method for manufacturing the same
The semiconductor device includes a semiconductor substrate including a first region straightly connected to a cell string region and a second region adjacent to the first region, a first conductive pattern having a first pitch in the first region, a second conductive pattern connected to the first conductive pattern in...

02/13/14 - 20140042633 - Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern
Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided....

02/13/14 - 20140042634 - Methods of making compliant semiconductor chip packages
A semiconductor chip package is fabricated including providing a compliant layer over a contact bearing face of a semiconductor chip, with a bottom surface of the compliant layer adjacent that chip face, a top surface facing away from the bottom surface, and at least one sloping surface extending between the...

02/13/14 - 20140042635 - Semiconductor device
One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer....

02/13/14 - 20140042636 - Dummy patterns and method for generating dummy patterns
A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a...

02/06/14 - 20140035151 - Integrated circuits and methods for fabricating integrated circuits using double patterning processes
Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second...

02/06/14 - 20140035152 - Methods for cell phasing and placement in dynamic array architecture and implementation of the same
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists...

01/30/14 - 20140027916 - Semiconductor device having vertical channel
A semiconductor device includes: bit lines each extending in a first direction; word lines each extending in a second direction, which crosses the first direction; pillars provided in a region between the bit lines and the word lines, wherein the pillars are each arranged along a third direction; and bit...

01/30/14 - 20140027917 - Non-lithographic line pattern formation
A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically...

01/30/14 - 20140027918 - Cross-coupling based design using diffusion contact structures
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact...

01/30/14 - 20140027919 - Semiconductor device and method of manufacturing the same
A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the...

01/30/14 - 20140027920 - Semiconductor device and method for manufacturing the same
A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed...

01/30/14 - 20140027921 - Connection carrier for semiconductor chips and semiconductor component
A connection carrier for at least one semiconductor chip is disclosed. The connection carrier has a carrier body having a main surface. A first connection area and a second connection area at a distance from the first connection area are formed on the main surface. The connection carrier has a...

01/23/14 - 20140021621 - Packaged semiconductor die with power rail pads
A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a...

01/23/14 - 20140021622 - Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections
A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the...

01/23/14 - 20140021623 - Method of forming electric contact interface regions of an electronic device
A method for forming electrical-contact interface regions on a wafer including a silicon-carbide substrate having a surface with at least one conductive region facing the surface. The method includes forming a first and a second resist layer; forming; removing portions of the second resist layer to form a through opening...

01/23/14 - 20140021624 - Mounting structure of semiconductor device and method of manufacturing the same
A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible...

01/23/14 - 20140021625 - Wiring substrate, method for manufacturing the wiring substrate, and semiconductor package
A wiring substrate includes an insulating layer including a reinforcement member and having a first surface and a second surface positioned on an opposite side of the first surface, an electrode pad exposed from the first surface, a layered body including first insulating layers and being formed on the second...

01/23/14 - 20140021626 - Liquid crystal display device and method of manufacturing a liquid crystal display device
A liquid crystal display device (10) includes: gate wiring (501) formed on a substrate (500) and along a first direction; drain wiring (702) formed on the substrate (500) and along a second direction that is different from the first direction; a common electrode (900) formed so as to cover the...

01/23/14 - 20140021627 - Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element...

01/16/14 - 20140015142 - Semiconductor device
In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the...

01/09/14 - 20140008806 - Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first...

01/09/14 - 20140008807 - Semiconductor constructions and methods of forming semiconductor constructions
Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect...

01/09/14 - 20140008808 - Method for fabricating a semiconductor device with formation of conductive lines
A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending...

01/09/14 - 20140008809 - Die up fully molded fan-out wafer level packaging
A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering...

01/02/14 - 20140001638 - Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality...

01/02/14 - 20140001639 - Semiconductor device having silicon interposer on which semiconductor chip is mounted
Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line...

01/02/14 - 20140001640 - Method for fabricating semiconductor device and semiconductor device
A method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and side surfaces; forming a mask pattern having an opening in which upper and side surfaces of the metal pattern therein being exposed; forming a barrier layer...