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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/24/14 - 20140203440 - Microelectronic package and method of manufacture thereof
A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a...

07/24/14 - 20140203441 - Semiconductor device and method of manufacturing the same
The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main...

07/24/14 - 20140203442 - Wiring structures for three-dimensional semiconductor devices
Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the...

07/24/14 - 20140203443 - Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to...

07/24/14 - 20140203444 - Semiconductor device and power source device
A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with...

07/17/14 - 20140197542 - Semiconductor devices and methods of fabricating semiconductor devices
Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some...

07/17/14 - 20140197543 - Enforcement of semiconductor structure regularity for localized transistors and interconnect
A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating...

07/10/14 - 20140191403 - Multi-die semiconductor package and method of manufacturing thereof
A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC)...

07/10/14 - 20140191404 - Local interconnect structure and fabrication method
Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned...

07/10/14 - 20140191405 - Method of forming patterns for semiconductor device
Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are...

07/10/14 - 20140191406 - Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a...

07/03/14 - 20140183747 - Multi-die, high current wafer level package
Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated...

07/03/14 - 20140183748 - Microbump and sacrificial pad pattern
Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit...

07/03/14 - 20140183749 - Semiconductor device and method of fabricating the same
In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified....

07/03/14 - 20140183750 - Ultrathin buried die module and method of manufacturing thereof
A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material...

07/03/14 - 20140183751 - Three-dimensional structure in which wiring is provided on its surface
One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter...

06/26/14 - 20140175657 - Methods to improve laser mark contrast on die backside film in embedded die packages
Apparatus including a die including a device side with contact points; and a build-up carrier disposed on the device side of the die; and a film disposed on the back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Method...

06/26/14 - 20140175658 - Anchoring a trace on a substrate to reduce peeling of the trace
Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is...

06/26/14 - 20140175659 - Semiconductor device including air gaps and method of fabricating the same
This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming...

06/26/14 - 20140175660 - Stack packages having token ring loops
Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first...

06/26/14 - 20140175661 - Semiconductor device and method of making bumpless flipchip interconnect structures
A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over...

06/26/14 - 20140175662 - Power layout for integrated circuits
An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically...

06/19/14 - 20140167272 - Semiconductor device having an identification mark
A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip....

06/19/14 - 20140167273 - Low parasitic package substrate having embedded passive substrate discrete components and method for making same
One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling...

06/19/14 - 20140167274 - Array substrate and display device
The embodiments of the present invention disclose an array substrate and a display device. The array substrate comprises a substrate and a first transparent conductive layer, an insulating layer and a second transparent conductive layer sequentially formed on the substrate, wherein the second transparent conductive layer has a plurality of...

06/19/14 - 20140167275 - Embedded package and method of manufacturing the same
When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized....

06/19/14 - 20140167276 - Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
A semiconductor package includes a package substrate, semiconductor chips adhered over the package substrate and configured to include bonding pads, one or more dummy patterns disposed at specific intervals in peripheries of the semiconductor chips, an insulating layer formed over the package substrate including the semiconductor chips and the dummy...

06/19/14 - 20140167277 - Semiconductor wiring patterns
A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes...

06/19/14 - 20140167278 - Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first...

06/19/14 - 20140167279 - Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a...

06/12/14 - 20140159244 - Process to achieve contact protrusion for single damascene via
The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend...

06/12/14 - 20140159245 - Semiconductor device and a method of manufacturing the same
A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in...

06/12/14 - 20140159246 - Methods of manufacturing nand flash memory devices
A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive...

06/05/14 - 20140151890 - Package with a fan-out structure and method of forming the same
An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a...

06/05/14 - 20140151891 - Semiconductor package
A semiconductor package includes: a first wiring substrate; a first spacer on the first wiring substrate, wherein the first spacer has a rectangular shape; a second spacer on the first wiring substrate to be separated from the first spacer, wherein the second spacer has a rectangular shape; a second wiring...

05/29/14 - 20140145342 - Metal density distribution for double pattern lithography
Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern...

05/29/14 - 20140145343 - Semiconductor device and method for manufacturing the same
A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor...

05/29/14 - 20140145344 - Semiconductor constructions and methods of forming semiconductor constructions
Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect...

05/22/14 - 20140138837 - Sandwiched diffusion barrier and metal liner for an interconnect structure
A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a...

05/22/14 - 20140138838 - Method of semiconducotr integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through...

05/22/14 - 20140138839 - Power semiconductor module
Disclosed herein is a power semiconductor module including a substrate having a first metal conductive track formed on one surface thereof, and a base plate made of a metal and solder-joined to the substrate in the first metal conductive track region, wherein a first uneven pattern is formed in the...

05/22/14 - 20140138840 - Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first...

05/15/14 - 20140131878 - Semiconductor devices with enhanced electromigration performance
Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least...

05/15/14 - 20140131879 - Design method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and...

05/15/14 - 20140131880 - Methods for fabrication of an air gap-containing interconnect structure
Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which...

05/08/14 - 20140124938 - Stress relief for plastic encapsulated devices
A semiconductor integrated circuit includes a semiconductor substrate, one or more devices in or on the semiconductor substrate, and a dielectric layer above the one or more devices, wherein the dielectric layer has openings over at least portions of the one or more devices. The semiconductor integrated circuit also includes...

05/08/14 - 20140124939 - Discrete device mounted on substrate
A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature...

05/08/14 - 20140124940 - Flexible routing for chip on board applications
Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each...

05/08/14 - 20140124941 - Semiconductor device
A semiconductor device includes a first base material having a first surface; a second base material having a coefficient of linear expansion different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface; and...

05/08/14 - 20140124942 - Reducing loadline impedance in a system
In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices...

05/01/14 - 20140117554 - Packaged integrated circuit having large solder pads and method for forming
A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only...

05/01/14 - 20140117555 - Integrated circuit underfill scheme
An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An...