FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration



Imprinted multi-level micro-wire circuit structure method
03/26/15 - 20150084200 - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate with a first stamp, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Second micro-channels are imprinted in a...

Imprinted micro-wire circuit multi-level stamp method
03/26/15 - 20150084201 - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Multi-level second micro-channels are imprinted in a curable second layer...

Die edge side connection
03/26/15 - 20150084202 - An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom...

Contact structure and forming method
03/26/15 - 20150084203 - A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack...

Semiconductor device and method of fabricating the same
03/26/15 - 20150084204 - Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common...

System-in-packages containing embedded surface mount devices and methods for the fabrication thereof
03/19/15 - 20150076700 - Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing one or more frontside redistribution layers over a molded panel having a backside and an opposing frontside through which a semiconductor die and a first Surface Mount...

Semiconductor device
03/19/15 - 20150076701 - Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection terminals, and a ground conductor. The semiconductor substrate includes a semiconductor element on its front surface. The side wall portion has conductivity and is provided on the front...

Semiconductor device and method of manufacturing the same
03/19/15 - 20150076702 - A semiconductor device including a semiconductor substrate having a hook-up region; wirings extending in a first direction above the semiconductor substrate and being aligned with a first spacing between one another, every two wirings forming pairs of wirings, each pair having a first portion being bent in a second direction...

Semiconductor memory device having pads
03/19/15 - 20150076703 - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of...

Semiconductor device
03/12/15 - 20150069615 - In one embodiment, a semiconductor device includes first and second semiconductor layers of a first conductivity type above a substrate via a first film, a first electrode above the second semiconductor layer, and a second electrode disposed on a side of the first electrode or an opposite side of the...

Semiconductor device and method of manufacturing the same
03/12/15 - 20150069616 - A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of...

Extremely stretchable electronics
03/12/15 - 20150069617 - In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components...

Microelectronic packages containing opposing devices and methods for the fabrication thereof
03/05/15 - 20150061139 - Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of...

Molded semiconductor package with pluggable lead
03/05/15 - 20150061140 - A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable lead dimensioned for insertion into an external receptacle. The pluggable lead protrudes from the molding compound and provides a separate electrical pathway for more than one terminal of...

Interconnect structures and methods of forming same
03/05/15 - 20150061141 - A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion...

Ultra fine pitch pop coreless package
03/05/15 - 20150061142 - A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement...

Ultra fine pitch and spacing interconnects for substrate
03/05/15 - 20150061143 - Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and...

Semiconductor arrangement, method for producing a semiconductor module, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement
03/05/15 - 20150061144 - A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies...

Semiconductor device
03/05/15 - 20150061145 - The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring...

Esd protection device
03/05/15 - 20150061146 - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The...

Semiconductor constructions
02/26/15 - 20150054164 - Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive...

Thin film transistor substrate and liquid crystal display including the same
02/26/15 - 20150054165 - A thin film transistor substrate includes: first and second driving chips; a plurality of signal lines respectively connected to the first and second driving chips; a plurality of first and second branch repair lines extended across the plurality of signal lines connected to the first driving chip; a plurality of...

Semiconductor arrangement, method for producing a number of chip assemblies and method for producing a semiconductor arrangement
02/26/15 - 20150054166 - A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina...

Semiconductor device and method of forming pad layout for flipchip semiconductor die
02/26/15 - 20150054167 - A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a...

Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures
02/26/15 - 20150054168 - Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over...

Stack packages having token ring loops
02/26/15 - 20150054169 - Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first...

Semiconductor devices including multiple interconnection structures and methods of manufacturing the same
02/19/15 - 20150048512 - A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first...

Method for obtaining three-dimensional actin structures and uses thereof
02/19/15 - 20150048513 - The present invention relates to a method for preparing three-dimensional actin structures having a well-defined shape and displaying improved mechanical rigidity. This method comprises the steps of (a) providing a polymerization solution comprising actin monomers, a branching agent and a capping agent, (b) providing at least one surface having thereon...

Electronic component and method
02/12/15 - 20150041984 - An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically...

Semiconductor device and method of making wafer level chip scale package
02/12/15 - 20150041985 - A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The...

Manufacturing method of a semiconductor device and method for creating a layout thereof
02/12/15 - 20150041986 - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a...

Pad configurations for an electronic package assembly
02/05/15 - 20150035160 - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side,...

Substrate structure and semiconductor package having the same
01/29/15 - 20150028485 - A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die...

Interconnect structures for embedded bridge
01/29/15 - 20150028486 - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals...

Chip package with passives
01/29/15 - 20150028487 - A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured...

Method for manufacturing a conducting contact on a conducting element
01/29/15 - 20150028488 - The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of...

Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
01/29/15 - 20150028489 - A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of...

Hard mask for back-end-of-line (beol) interconnect structure
01/22/15 - 20150021779 - A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over...

Thin power device and preparation method thereof
01/22/15 - 20150021780 - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the...

Semiconductor device and method of manufacturing semiconductor device
01/22/15 - 20150021781 - A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole...

Design method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
01/22/15 - 20150021782 - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and...

Semiconductor memory system
01/22/15 - 20150021783 - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side...

Microelectronic packages and methods for the fabrication thereof
01/15/15 - 20150014855 - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or...

Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
01/15/15 - 20150014856 - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned...

Low-resistance electrode design
01/15/15 - 20150014857 - A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of...

Semiconductor device and manufacturing method of semiconductor device
01/08/15 - 20150008584 - According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction...

Pre-treatment method for metal-oxide reduction and device formed
01/01/15 - 20150001728 - A method of forming a semiconductor device, the method includes performing, in a first module, a remote plasma treatment on a wafer to remove an oxide layer from the wafer by a reduction reaction. The method further includes transferring the pre-treated wafer from the first module to a second module...

Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
01/01/15 - 20150001729 - A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the...

Method to increase i/o density and reduce layer counts in bbul packages
01/01/15 - 20150001730 - An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one...

Circuit arrangement and method for manufacturing the same
12/25/14 - 20140374913 - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second...

Stress compensation patterning
12/25/14 - 20140374914 - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device....

Package substrates and methods of fabricating the same
12/11/14 - 20140361437 - Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of...

Methods of self-forming barrier integration with pore stuffed ulk material
12/04/14 - 20140353835 - A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing...

Chip arrangements and a method for manufacturing a chip arrangement
12/04/14 - 20140353836 - A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having...

Semiconductor device and manufacturing method thereof
12/04/14 - 20140353837 - A semiconductor device according to the present embodiment includes an insulating film provided above a semiconductor substrate. A plurality of upper-layer wirings are provided on the insulating film. A plurality of lower-layer wirings are provided in the insulating film. The lower-layer wirings are respectively located between the upper-layer wirings adjacent...

3d packages and methods for forming the same
12/04/14 - 20140353838 - Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and...

Semiconductor device
11/27/14 - 20140346676 - Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the...

Semiconductor package
11/20/14 - 20140339704 - A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two...

Epoxy-amine underfill materials for semiconductor packages
11/13/14 - 20140332966 - Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality...

Bit cell with double patterened metal layer structures
11/13/14 - 20140332967 - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure...

Chip package
11/13/14 - 20140332968 - A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal...

Chip package and method for forming the same
11/13/14 - 20140332969 - A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess...

Semiconductor device and method forming patterns with spaced pads in trim region
11/13/14 - 20140332970 - In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater...

Method and layout of an integrated circuit
11/13/14 - 20140332971 - An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the...

Composite reconstituted wafer structures
11/13/14 - 20140332972 - A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials...

Semiconductor device and method of fabricating the same
10/30/14 - 20140319690 - A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact....

Semiconductor device
10/30/14 - 20140319691 - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a...

Semiconductor device and method of forming high routing density interconnect sites on substrate
10/30/14 - 20140319692 - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater...

Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
10/23/14 - 20140312500 - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined...

Non-random array anisotropic conductive film (acf) and manufacturing processes
10/23/14 - 20140312501 - Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling...

Semiconductor device with an insulation layer having a varying thickness
10/16/14 - 20140306347 - A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a...

Chip on film and display device having the same
10/16/14 - 20140306348 - A flexible chip on film includes a base insulating layer, a metal layer disposed on an upper surface of the base insulating layer and including a circuit pattern, an integrated circuit chip disposed on an upper surface of the metal layer and electrically connected to the metal layer, a solder...