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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

11/20/14 - 20140339704 - Semiconductor package
A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two...

11/13/14 - 20140332966 - Epoxy-amine underfill materials for semiconductor packages
Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality...

11/13/14 - 20140332967 - Bit cell with double patterened metal layer structures
An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure...

11/13/14 - 20140332968 - Chip package
A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal...

11/13/14 - 20140332969 - Chip package and method for forming the same
A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess...

11/13/14 - 20140332970 - Semiconductor device and method forming patterns with spaced pads in trim region
In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater...

11/13/14 - 20140332971 - Method and layout of an integrated circuit
An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the...

11/13/14 - 20140332972 - Composite reconstituted wafer structures
A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials...

10/30/14 - 20140319690 - Semiconductor device and method of fabricating the same
A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact....

10/30/14 - 20140319691 - Semiconductor device
A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a...

10/30/14 - 20140319692 - Semiconductor device and method of forming high routing density interconnect sites on substrate
A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater...

10/23/14 - 20140312500 - Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined...

10/23/14 - 20140312501 - Non-random array anisotropic conductive film (acf) and manufacturing processes
Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling...

10/16/14 - 20140306347 - Semiconductor device with an insulation layer having a varying thickness
A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a...

10/16/14 - 20140306348 - Chip on film and display device having the same
A flexible chip on film includes a base insulating layer, a metal layer disposed on an upper surface of the base insulating layer and including a circuit pattern, an integrated circuit chip disposed on an upper surface of the metal layer and electrically connected to the metal layer, a solder...

10/09/14 - 20140299997 - Spacer process for on pitch contacts and related structures
Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a...

10/09/14 - 20140299998 - Method for making contact with a semiconductor and contact arrangement for a semiconductor
The invention relates to a method for making contact with a semiconductor (10), and to a contact arrangement (1) for a semiconductor (10), wherein the semiconductor (10) is a really connected to a first contact partner (20) at at least one first area by the formation of a first soldering...

10/02/14 - 20140291849 - Multi-level semiconductor package
A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second...

10/02/14 - 20140291850 - Method for manufacturing electronic devices
An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled...

10/02/14 - 20140291851 - Lead pin for package substrate
A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path...

10/02/14 - 20140291852 - Interconnect for an optoelectronic device
Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first...

09/25/14 - 20140284803 - Semiconductor package and fabrication method thereof
A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer...

09/25/14 - 20140284804 - Semiconductor device
A semiconductor device includes a first electrode formed on a substrate, the first electrode being a first electrical potential; and a second electrode formed on the first electrode, the second electrode including a signal wiring that transmits a signal and a planar electrode part with a prescribed area. A shape...

09/25/14 - 20140284805 - Multiple helix substrate and three-dimensional package with same
A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the...

09/25/14 - 20140284806 - Semiconductor device die attachment
A semiconductor device has first and semiconductor dies having active faces presenting electrical contact elements and back faces attached to first and second bonding areas side by side on an electrically conductive die support. A layer of electrically insulating material is applied to the first bonding area of the die...

09/25/14 - 20140284807 - Encapsulation process and associated device
The invention also relates to an electronic device obtained using such a process....

09/25/14 - 20140284808 - Stacked semiconductor device, and method and apparatus of manufacturing the same
Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film...

09/25/14 - 20140284809 - Power converter
A power converter includes a bus bar, a semiconductor device, a lead, and solder. The bus bar has a vertical wall. The semiconductor device includes an electrode. The lead has one end connected to the bus bar and another end connected to the semiconductor device to supply power from the...

09/25/14 - 20140284810 - Semiconductor device
In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the...

09/25/14 - 20140284811 - Methods for multi-wire routing and apparatus implementing same
A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual...

09/25/14 - 20140284812 - Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then...

09/18/14 - 20140264888 - Semiconductor package structure and method of manufacturing the same
A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor...

09/18/14 - 20140264889 - Semiconductor device channels
A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional...

09/18/14 - 20140264890 - Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the...

09/18/14 - 20140264891 - Forming fence conductors in an integrated circuit
A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the...

09/18/14 - 20140264892 - Semiconductor device with dummy lines
A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction....

09/18/14 - 20140264893 - Pitch-halving integrated circuit process and integrated circuit structure made thereby
A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the...

09/18/14 - 20140264894 - System and method for arbitrary metal spacing for self-aligned double patterning
An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first...

09/18/14 - 20140264895 - Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about...

09/18/14 - 20140264896 - Structure and method for a low-k dielectric with pillar-type air-gaps
A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a...

09/18/14 - 20140264897 - Damascene conductor for a 3d device
A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is...

09/18/14 - 20140264898 - 3-d ic device with enhanced contact area
A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At...

09/18/14 - 20140264899 - Pattern modification with a preferred position function
A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that...

09/18/14 - 20140264900 - Anisotropic conductor and method of fabrication thereof
An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the...

09/18/14 - 20140264901 - Semiconductor device and layout design system
In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of...

09/11/14 - - Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to...

09/11/14 - 20140252632 - Semiconductor devices
A semiconductor device includes: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip...

09/11/14 - 20140252633 - Method of fabricating an air gap using a damascene process and structure of same
The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an...

09/11/14 - 20140252634 - Packaging devices and methods for semiconductor devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of...

09/11/14 - 20140252635 - Bonding structures and methods of forming the same
A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A...

09/11/14 - 20140252636 - Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting...

09/11/14 - 20140252637 - Horizontal interconnects crosstalk optimization
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define...

09/11/14 - 20140252638 - Vertical interconnects crosstalk optimization
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of...

09/11/14 - 20140252639 - Integrated circuit device, method for producing mask layout, and program for producing mask layout
According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying...

09/11/14 - 20140252640 - Semiconductor package having a multi-channel and a related electronic system
A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive...

09/11/14 - 20140252641 - Semiconductor device and method of forming ultra high density embedded semiconductor die package
A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film...

09/11/14 - 20140252642 - Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer...

09/11/14 - 20140252643 - Semiconductor device manufacturing method and semiconductor device
To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane...