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Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Configuration



Substrate structure and semiconductor package having the same
01/29/15 - 20150028485 - A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die...

Interconnect structures for embedded bridge
01/29/15 - 20150028486 - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals...

Chip package with passives
01/29/15 - 20150028487 - A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured...

Method for manufacturing a conducting contact on a conducting element
01/29/15 - 20150028488 - The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of...

Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
01/29/15 - 20150028489 - A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of...

Hard mask for back-end-of-line (beol) interconnect structure
01/22/15 - 20150021779 - A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over...

Thin power device and preparation method thereof
01/22/15 - 20150021780 - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the...

Semiconductor device and method of manufacturing semiconductor device
01/22/15 - 20150021781 - A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole...

Design method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
01/22/15 - 20150021782 - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and...

Semiconductor memory system
01/22/15 - 20150021783 - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side...

Microelectronic packages and methods for the fabrication thereof
01/15/15 - 20150014855 - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or...

Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
01/15/15 - 20150014856 - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned...

Low-resistance electrode design
01/15/15 - 20150014857 - A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of...

Semiconductor device and manufacturing method of semiconductor device
01/08/15 - 20150008584 - According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction...

Pre-treatment method for metal-oxide reduction and device formed
01/01/15 - 20150001728 - A method of forming a semiconductor device, the method includes performing, in a first module, a remote plasma treatment on a wafer to remove an oxide layer from the wafer by a reduction reaction. The method further includes transferring the pre-treated wafer from the first module to a second module...

Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
01/01/15 - 20150001729 - A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the...

Method to increase i/o density and reduce layer counts in bbul packages
01/01/15 - 20150001730 - An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one...

Circuit arrangement and method for manufacturing the same
12/25/14 - 20140374913 - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second...

Stress compensation patterning
12/25/14 - 20140374914 - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device....

Package substrates and methods of fabricating the same
12/11/14 - 20140361437 - Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of...

Methods of self-forming barrier integration with pore stuffed ulk material
12/04/14 - 20140353835 - A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing...

Chip arrangements and a method for manufacturing a chip arrangement
12/04/14 - 20140353836 - A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having...

Semiconductor device and manufacturing method thereof
12/04/14 - 20140353837 - A semiconductor device according to the present embodiment includes an insulating film provided above a semiconductor substrate. A plurality of upper-layer wirings are provided on the insulating film. A plurality of lower-layer wirings are provided in the insulating film. The lower-layer wirings are respectively located between the upper-layer wirings adjacent...

3d packages and methods for forming the same
12/04/14 - 20140353838 - Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and...

Semiconductor device
11/27/14 - 20140346676 - Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the...

Semiconductor package
11/20/14 - 20140339704 - A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two...

Epoxy-amine underfill materials for semiconductor packages
11/13/14 - 20140332966 - Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality...

Bit cell with double patterened metal layer structures
11/13/14 - 20140332967 - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure...

Chip package
11/13/14 - 20140332968 - A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal...

Chip package and method for forming the same
11/13/14 - 20140332969 - A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess...

Semiconductor device and method forming patterns with spaced pads in trim region
11/13/14 - 20140332970 - In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater...

Method and layout of an integrated circuit
11/13/14 - 20140332971 - An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the...

Composite reconstituted wafer structures
11/13/14 - 20140332972 - A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials...

Semiconductor device and method of fabricating the same
10/30/14 - 20140319690 - A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact....

Semiconductor device
10/30/14 - 20140319691 - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a...

Semiconductor device and method of forming high routing density interconnect sites on substrate
10/30/14 - 20140319692 - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater...

Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
10/23/14 - 20140312500 - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined...

Non-random array anisotropic conductive film (acf) and manufacturing processes
10/23/14 - 20140312501 - Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling...

Semiconductor device with an insulation layer having a varying thickness
10/16/14 - 20140306347 - A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a...

Chip on film and display device having the same
10/16/14 - 20140306348 - A flexible chip on film includes a base insulating layer, a metal layer disposed on an upper surface of the base insulating layer and including a circuit pattern, an integrated circuit chip disposed on an upper surface of the metal layer and electrically connected to the metal layer, a solder...

Spacer process for on pitch contacts and related structures
10/09/14 - 20140299997 - Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a...

Method for making contact with a semiconductor and contact arrangement for a semiconductor
10/09/14 - 20140299998 - The invention relates to a method for making contact with a semiconductor (10), and to a contact arrangement (1) for a semiconductor (10), wherein the semiconductor (10) is a really connected to a first contact partner (20) at at least one first area by the formation of a first soldering...

Multi-level semiconductor package
10/02/14 - 20140291849 - A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second...

Method for manufacturing electronic devices
10/02/14 - 20140291850 - An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled...

Lead pin for package substrate
10/02/14 - 20140291851 - A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path...

Interconnect for an optoelectronic device
10/02/14 - 20140291852 - Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first...

Semiconductor package and fabrication method thereof
09/25/14 - 20140284803 - A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer...

Semiconductor device
09/25/14 - 20140284804 - A semiconductor device includes a first electrode formed on a substrate, the first electrode being a first electrical potential; and a second electrode formed on the first electrode, the second electrode including a signal wiring that transmits a signal and a planar electrode part with a prescribed area. A shape...

Multiple helix substrate and three-dimensional package with same
09/25/14 - 20140284805 - A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the...

Semiconductor device die attachment
09/25/14 - 20140284806 - A semiconductor device has first and semiconductor dies having active faces presenting electrical contact elements and back faces attached to first and second bonding areas side by side on an electrically conductive die support. A layer of electrically insulating material is applied to the first bonding area of the die...

Encapsulation process and associated device
09/25/14 - 20140284807 - The invention also relates to an electronic device obtained using such a process....

Stacked semiconductor device, and method and apparatus of manufacturing the same
09/25/14 - 20140284808 - Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film...

Power converter
09/25/14 - 20140284809 - A power converter includes a bus bar, a semiconductor device, a lead, and solder. The bus bar has a vertical wall. The semiconductor device includes an electrode. The lead has one end connected to the bus bar and another end connected to the semiconductor device to supply power from the...

Semiconductor device
09/25/14 - 20140284810 - In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the...

Methods for multi-wire routing and apparatus implementing same
09/25/14 - 20140284811 - A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual...

Forming array contacts in semiconductor memories
09/25/14 - 20140284812 - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then...

Semiconductor package structure and method of manufacturing the same
09/18/14 - 20140264888 - A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor...

Semiconductor device channels
09/18/14 - 20140264889 - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional...

Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
09/18/14 - 20140264890 - One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the...

Forming fence conductors in an integrated circuit
09/18/14 - 20140264891 - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the...

Semiconductor device with dummy lines
09/18/14 - 20140264892 - A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction....

Pitch-halving integrated circuit process and integrated circuit structure made thereby
09/18/14 - 20140264893 - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the...

System and method for arbitrary metal spacing for self-aligned double patterning
09/18/14 - 20140264894 - An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first...

Semiconductor devices and methods of manufacture thereof
09/18/14 - 20140264895 - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about...

Structure and method for a low-k dielectric with pillar-type air-gaps
09/18/14 - 20140264896 - A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a...

Damascene conductor for a 3d device
09/18/14 - 20140264897 - A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is...

3-d ic device with enhanced contact area
09/18/14 - 20140264898 - A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At...

Pattern modification with a preferred position function
09/18/14 - 20140264899 - A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that...

Anisotropic conductor and method of fabrication thereof
09/18/14 - 20140264900 - An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the...

Semiconductor device and layout design system
09/18/14 - 20140264901 - In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of...

Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
09/11/14 - - A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to...

Semiconductor devices
09/11/14 - 20140252632 - A semiconductor device includes: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip...

Method of fabricating an air gap using a damascene process and structure of same
09/11/14 - 20140252633 - The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an...

Packaging devices and methods for semiconductor devices
09/11/14 - 20140252634 - Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of...

Bonding structures and methods of forming the same
09/11/14 - 20140252635 - A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A...

Interconnect structure and method of forming the same
09/11/14 - 20140252636 - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting...

Horizontal interconnects crosstalk optimization
09/11/14 - 20140252637 - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define...

Vertical interconnects crosstalk optimization
09/11/14 - 20140252638 - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of...

Integrated circuit device, method for producing mask layout, and program for producing mask layout
09/11/14 - 20140252639 - According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying...

Semiconductor package having a multi-channel and a related electronic system
09/11/14 - 20140252640 - A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive...

Semiconductor device and method of forming ultra high density embedded semiconductor die package
09/11/14 - 20140252641 - A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film...

Chip package and method for forming the same
09/11/14 - 20140252642 - An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer...

Semiconductor device manufacturing method and semiconductor device
09/11/14 - 20140252643 - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane...