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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264888 - Semiconductor package structure and method of manufacturing the same
A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor...

09/18/14 - 20140264889 - Semiconductor device channels
A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional...

09/18/14 - 20140264890 - Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the...

09/18/14 - 20140264891 - Forming fence conductors in an integrated circuit
A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the...

09/18/14 - 20140264892 - Semiconductor device with dummy lines
A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction....

09/18/14 - 20140264893 - Pitch-halving integrated circuit process and integrated circuit structure made thereby
A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the...

09/18/14 - 20140264894 - System and method for arbitrary metal spacing for self-aligned double patterning
An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first...

09/18/14 - 20140264895 - Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about...

09/18/14 - 20140264896 - Structure and method for a low-k dielectric with pillar-type air-gaps
A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a...

09/18/14 - 20140264897 - Damascene conductor for a 3d device
A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is...

09/18/14 - 20140264898 - 3-d ic device with enhanced contact area
A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At...

09/18/14 - 20140264899 - Pattern modification with a preferred position function
A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that...

09/18/14 - 20140264900 - Anisotropic conductor and method of fabrication thereof
An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the...

09/18/14 - 20140264901 - Semiconductor device and layout design system
In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of...

09/11/14 - - Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to...

09/11/14 - 20140252632 - Semiconductor devices
A semiconductor device includes: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip...

09/11/14 - 20140252633 - Method of fabricating an air gap using a damascene process and structure of same
The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an...

09/11/14 - 20140252634 - Packaging devices and methods for semiconductor devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of...

09/11/14 - 20140252635 - Bonding structures and methods of forming the same
A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A...

09/11/14 - 20140252636 - Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting...

09/11/14 - 20140252637 - Horizontal interconnects crosstalk optimization
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define...

09/11/14 - 20140252638 - Vertical interconnects crosstalk optimization
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of...

09/11/14 - 20140252639 - Integrated circuit device, method for producing mask layout, and program for producing mask layout
According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying...

09/11/14 - 20140252640 - Semiconductor package having a multi-channel and a related electronic system
A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive...

09/11/14 - 20140252641 - Semiconductor device and method of forming ultra high density embedded semiconductor die package
A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film...

09/11/14 - 20140252642 - Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer...

09/11/14 - 20140252643 - Semiconductor device manufacturing method and semiconductor device
To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane...

09/04/14 - 20140246777 - Controlled metal extrusion opening in semiconductor structure and method of forming
Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer...

09/04/14 - 20140246778 - Semiconductor device, wireless device, and storage device
According to one embodiment, a semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a discrete element part. The first semiconductor chip is arranged on the substrate and includes a first electrode group. The second semiconductor chip is arranged on the substrate and includes a...

09/04/14 - 20140246779 - Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is...

09/04/14 - 20140246780 - Semiconductor device including dummy pattern
A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance...

08/28/14 - 20140239503 - Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is...

08/28/14 - 20140239504 - Multi-layer micro-wire structure
A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is...

08/28/14 - 20140239505 - Bump-on-trace methods and structures in packaging
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer....

08/28/14 - 20140239506 - Semiconductor device and manufacturing method thereof
To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above...

08/21/14 - 20140232006 - Device and method for manufacturing a device
A device includes a semiconductor chip including a frontside, a backside, and a side surface extending from the backside to the frontside. The side surface includes a first region and a second region, wherein a level of the first region is different from a level of the second region. The...

08/21/14 - 20140232007 - Semiconductor device and electronic apparatus
A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a...

08/21/14 - 20140232008 - Semiconductor constructions and methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a...

08/21/14 - 20140232009 - Memory circuits and routing of conductive layers thereof
A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and...

08/14/14 - 20140225270 - Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of...

08/14/14 - 20140225271 - Panelized packaging with transferred dielectric
Panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die unit in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less pattering technique....

08/07/14 - 20140217596 - Power transistor arrangement and method for manufacturing the same
Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second...

08/07/14 - 20140217597 - Semiconductor device and method of forming stress relieving vias for improved fan-out wlcsp package
A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and...

08/07/14 - 20140217598 - Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of the nth layer, each of the plurality of stacked films of the nth layer including a memory element, an...

08/07/14 - 20140217599 - Bbul material integration in-plane with embedded die for warpage control
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled...

08/07/14 - 20140217600 - Semiconductor device and method of manufacturing the same
The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which...

08/07/14 - 20140217601 - Semiconductor device
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the...

08/07/14 - 20140217602 - Semiconductor device
Provided is a semiconductor package with improved mounting property. A concave portion is provided in an insulating resin between an island for mounting a semiconductor chip thereon and an opposing lead, to thereby prevent contact between solder printed on a circuit board and the insulating resin. Self-alignment property in melting...

07/31/14 - 20140210093 - Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an internal resin sealing body having an edge and an opposite edge. The edge side of the internal resin sealing body covers a first end of an internal...

07/31/14 - 20140210094 - Wiring structure, droplet discharge head, and droplet discharge apparatus
A droplet discharge head includes: a vibrating plate on which first and second terminals are formed; a reservoir forming substrate bonded to the vibrating plate and including a first inclined surface as a side surface on which a first wiring electrically connected to the first terminal is formed and that...

07/31/14 - 20140210095 - Methods of manufacturing nand flash memory devices
A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive...

07/31/14 - 20140210096 - Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program
A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and...