FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents


Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Configuration

Of Specified Configuration

Of Specified Configuration patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

08/28/14 - 20140239503 - Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is...

08/28/14 - 20140239504 - Multi-layer micro-wire structure
A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is...

08/28/14 - 20140239505 - Bump-on-trace methods and structures in packaging
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer....

08/28/14 - 20140239506 - Semiconductor device and manufacturing method thereof
To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above...

08/21/14 - 20140232006 - Device and method for manufacturing a device
A device includes a semiconductor chip including a frontside, a backside, and a side surface extending from the backside to the frontside. The side surface includes a first region and a second region, wherein a level of the first region is different from a level of the second region. The...

08/21/14 - 20140232007 - Semiconductor device and electronic apparatus
A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a...

08/21/14 - 20140232008 - Semiconductor constructions and methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a...

08/21/14 - 20140232009 - Memory circuits and routing of conductive layers thereof
A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and...

08/14/14 - 20140225270 - Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of...

08/14/14 - 20140225271 - Panelized packaging with transferred dielectric
Panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die unit in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less pattering technique....

08/07/14 - 20140217596 - Power transistor arrangement and method for manufacturing the same
Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second...

08/07/14 - 20140217597 - Semiconductor device and method of forming stress relieving vias for improved fan-out wlcsp package
A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and...

08/07/14 - 20140217598 - Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of the nth layer, each of the plurality of stacked films of the nth layer including a memory element, an...

08/07/14 - 20140217599 - Bbul material integration in-plane with embedded die for warpage control
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled...

08/07/14 - 20140217600 - Semiconductor device and method of manufacturing the same
The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which...

08/07/14 - 20140217601 - Semiconductor device
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the...

08/07/14 - 20140217602 - Semiconductor device
Provided is a semiconductor package with improved mounting property. A concave portion is provided in an insulating resin between an island for mounting a semiconductor chip thereon and an opposing lead, to thereby prevent contact between solder printed on a circuit board and the insulating resin. Self-alignment property in melting...

07/31/14 - 20140210093 - Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an internal resin sealing body having an edge and an opposite edge. The edge side of the internal resin sealing body covers a first end of an internal...

07/31/14 - 20140210094 - Wiring structure, droplet discharge head, and droplet discharge apparatus
A droplet discharge head includes: a vibrating plate on which first and second terminals are formed; a reservoir forming substrate bonded to the vibrating plate and including a first inclined surface as a side surface on which a first wiring electrically connected to the first terminal is formed and that...

07/31/14 - 20140210095 - Methods of manufacturing nand flash memory devices
A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive...

07/31/14 - 20140210096 - Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program
A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and...

07/24/14 - 20140203440 - Microelectronic package and method of manufacture thereof
A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a...

07/24/14 - 20140203441 - Semiconductor device and method of manufacturing the same
The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main...

07/24/14 - 20140203442 - Wiring structures for three-dimensional semiconductor devices
Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the...

07/24/14 - 20140203443 - Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to...

07/24/14 - 20140203444 - Semiconductor device and power source device
A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with...

07/17/14 - 20140197542 - Semiconductor devices and methods of fabricating semiconductor devices
Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some...

07/17/14 - 20140197543 - Enforcement of semiconductor structure regularity for localized transistors and interconnect
A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating...

07/10/14 - 20140191403 - Multi-die semiconductor package and method of manufacturing thereof
A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC)...

07/10/14 - 20140191404 - Local interconnect structure and fabrication method
Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned...

07/10/14 - 20140191405 - Method of forming patterns for semiconductor device
Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are...

07/10/14 - 20140191406 - Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a...

07/03/14 - 20140183747 - Multi-die, high current wafer level package
Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated...

07/03/14 - 20140183748 - Microbump and sacrificial pad pattern
Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit...

07/03/14 - 20140183749 - Semiconductor device and method of fabricating the same
In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified....

07/03/14 - 20140183750 - Ultrathin buried die module and method of manufacturing thereof
A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material...

07/03/14 - 20140183751 - Three-dimensional structure in which wiring is provided on its surface
One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter...

06/26/14 - 20140175657 - Methods to improve laser mark contrast on die backside film in embedded die packages
Apparatus including a die including a device side with contact points; and a build-up carrier disposed on the device side of the die; and a film disposed on the back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Method...

06/26/14 - 20140175658 - Anchoring a trace on a substrate to reduce peeling of the trace
Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is...

06/26/14 - 20140175659 - Semiconductor device including air gaps and method of fabricating the same
This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming...

06/26/14 - 20140175660 - Stack packages having token ring loops
Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first...

06/26/14 - 20140175661 - Semiconductor device and method of making bumpless flipchip interconnect structures
A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over...

06/26/14 - 20140175662 - Power layout for integrated circuits
An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically...

06/19/14 - 20140167272 - Semiconductor device having an identification mark
A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip....

06/19/14 - 20140167273 - Low parasitic package substrate having embedded passive substrate discrete components and method for making same
One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling...

06/19/14 - 20140167274 - Array substrate and display device
The embodiments of the present invention disclose an array substrate and a display device. The array substrate comprises a substrate and a first transparent conductive layer, an insulating layer and a second transparent conductive layer sequentially formed on the substrate, wherein the second transparent conductive layer has a plurality of...

06/19/14 - 20140167275 - Embedded package and method of manufacturing the same
When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized....

06/19/14 - 20140167276 - Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
A semiconductor package includes a package substrate, semiconductor chips adhered over the package substrate and configured to include bonding pads, one or more dummy patterns disposed at specific intervals in peripheries of the semiconductor chips, an insulating layer formed over the package substrate including the semiconductor chips and the dummy...

06/19/14 - 20140167277 - Semiconductor wiring patterns
A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes...

06/19/14 - 20140167278 - Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first...

06/19/14 - 20140167279 - Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a...