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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum > Layered > At Least One Layer Containing Silver Or Copper At Least One Layer Containing Silver Or CopperAt Least One Layer Containing Silver Or Copper patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/17/08 - 20080012142 - Structure and method of chemically formed anchored metallic vias Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating ... 01/03/08 - 20080001296 - Bond pad structures and semiconductor devices using the same A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor ... 12/20/07 - 20070290359 - Inexpensive method of fabricating a higher performance capacitance density mimcap integrable into a copper interconnect scheme A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. ... 11/29/07 - 20070273043 - Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. ... 11/01/07 - 20070252281 - Wirebond pad for semiconductor chip or wafer In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and ... 10/04/07 - 20070228575 - Wiring material and wiring board using the same A wiring material for TFT-LCD which comprises an Ag alloy containing Ag and Zr as essential components and further one or more metals selected from the group consisting of Au, Ni, Co and Al; and a wiring material which comprises a Cu alloy comprising Au and/or Co and Cu, wherein ... 09/13/07 - 20070210455 - Carbon nanotube-modified low-k materials An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the ... 09/06/07 - 20070205517 - Semiconductor devices and method for fabricating the same Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by ... 08/16/07 - 20070187833 - Method of fabricating semiconductor memory device and semiconductor memory device driver Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in ... 08/16/07 - 20070187832 - Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second ... 08/09/07 - 20070182016 - Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or ... 07/19/07 - 20070164442 - Use of ain as cooper passivation layer and thermal conductor A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the ... 07/19/07 - 20070164441 - Method of wire bonding over active area of a semiconductor circuit A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over ... 07/19/07 - 20070164439 - In-situ deposition for cu hillock suppression A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than ... 05/31/07 - 20070120263 - Conductor track arrangement and associated production method A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally ... 05/17/07 - 20070108619 - Bonding pad with high bonding strength to solder ball and bump A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form ... 04/19/07 - 20070085213 - Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers ... 04/12/07 - 20070080463 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a lower insulating film formed on the semiconductor substrate, an interconnect-forming metal film provided so as to fill a recess formed in the surficial portion of the lower insulating film, and containing copper as a major constituent, an upper insulating film formed on ... 04/12/07 - 20070080462 - Electrode and method for forming the same An electrode and a method for forming the electrode. The electrode comprises: a substrate; and a plurality of metal particles adhering to the substrate. The method comprises steps of: providing a substrate; providing a solution including a solvent and a plurality of metal particles on the substrate; removing the solvent; ... 04/05/07 - 20070075430 - Solder joint intermetallic compounds with improved ductility and toughness A method including forming a intermetallic compound including (1) an interfacial reaction product between a solder and a contact point and (2) a reaction species. A method including doping a solder material with a species; and forming a intermetallic compound including an interfacial reaction product between the solder material and ... 03/08/07 - 20070052104 - Grafted seed layer for electrochemical plating Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable ... 03/01/07 - 20070045853 - Method for forming metal line, method for manufacturing semiconductor device using the method, and semiconductor device Provided is a method for forming a metal line. According to the method, a silicon carbide (SiC) layer is formed on a semiconductor substrate, a silicon oxide layer is formed on the silicon carbide layer, the silicon oxide layer including an alkyl group, and a via hole and a trench ... 02/22/07 - 20070040277 - Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, ... 02/15/07 - 20070035029 - Production of a self-aligned cusin barrier A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly ... 02/08/07 - 20070029677 - Interconnection structure An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the ... 02/01/07 - 20070023917 - Semiconductor device having multilayer wiring lines and manufacturing method thereof A plurality of wiring layers made from a conductive material are formed in the same level layer on a substrate. A plurality of cavity layers are formed in the same level layer as the plurality of wiring layers. The plurality of cavity layers have a cavity ratio which is not ... 01/25/07 - 20070018330 - Semiconductor device and method of manufacturing the same A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 ... 01/25/07 - 20070018329 - Interconnection having dual-level or multi-level capping layer and method of forming the same An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the ... 01/25/07 - 20070018328 - Piezoelectric stress liner for bulk and soi A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a piezoelectric layer overlying the n-channel transistor and the p-channel transistor. In a preferred embodiment of the invention, the piezoelectric layer is biased ... 01/18/07 - 20070013078 - Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating thin film transistor substrate Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer ... 01/18/07 - 20070013077 - Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier ... 01/04/07 - 20070001310 - Thermal interface material and method A thermal interface material is provided using composite particles. Advantages include increased thermal conductivity and improved mechanical properties such as lower viscosity. In selected embodiments free particles such as metallic particles or carbon nanotubes, etc. are included in a thermal interface material along with composite particles. An advantage of including ... 12/28/06 - 20060289999 - Selective copper alloy interconnections in semiconductor devices and methods of forming the same A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the ... 11/30/06 - 20060267205 - Integrated circuit arrangement with layer stack, and process An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a ... 11/30/06 - 20060267204 - Semiconductor device and manufacturing method thereof The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating ... 11/30/06 - 20060267203 - Structure and method for bond pads of copper-metallized integrated circuits A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window ... 11/23/06 - 20060261487 - Electrode material and semiconductor element A semiconductor electrode material in the form of a material represented by a composition formula AXBYCZ (A: at least one element selected from Group 1B metal elements, B: at least one element selected from Group 8 metal elements, C: at least one element selected from S and Se), where X, ... 09/28/06 - 20060214304 - Memory device with improved data retention The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. ... 09/21/06 - 20060208362 - Carbon nanotubes with controlled diameter, length, and metallic contacts Some embodiments of the present invention include fabricating carbon nanotube bundles with controlled length, diameter, and metallic contacts. ... 08/24/06 - 20060186549 - Semiconductor device and method of manufacturing the same A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of ... 08/17/06 - 20060180936 - Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also ... 08/17/06 - 20060180935 - Semiconductor device A structure of a semiconductor device provided with a surface electrode can be simplified. Cu, which is a solderable metal, is employed for the gate electrode 101 and the source electrode 104 in a semiconductor device 100. Therefore, unlike as in the conventional technology, it is not necessary to separately ... 07/27/06 - 20060163740 - Semiconductor mounting board A semiconductor mounting board 80 is prepared by electrically joining an IC chip 70 via an interposer 60 of high rigidity to external pads 41 and internal pads 43, which are formed on the uppermost surface of a build-up layer 30. When the IC chip 70 generates heat, since pads ... 07/27/06 - 20060163739 - Semiconductor device and method for production thereof Disclosed herein is a semiconductor device with improved electromigration durability and a method for producing the semiconductor device. A semiconductor device includes: an interlayer insulating film formed on a first metal wiring; a second metal wiring formed by embedding in the interlayer insulating film; a metal contact formed by embedding ... 07/20/06 - 20060157860 - Semiconductor constructions The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the ... 07/20/06 - 20060157859 - Led packaging method and package structure A LED packaging method is disclosed. The LED packaging method includes the steps of forming a high reflectivity alloy layer on an electrode layer of a support; coating a polymer adhesive on a portion of the upper surface of the high reflectivity alloy layer to form an adhering point; and ... 07/20/06 - 20060157858 - Structure for cooling a surface An apparatus for cooling a surface having a metal structure made of a material with high thermal conductivity, and designed to provide efficient cooling of the surface while minimizing mechanical stress between the metal structure and the surface. ... 07/06/06 - 20060145351 - Adhesion of a metal layer to a substrate and related structures Methods and resulting structures are described in which a metal layer is adhered to a surface of a substrate. The methods involve applying a sacrificial acidic organic layer to the surface of the substrate prior to depositing the metal layer onto the substrate. During deposition of the metal layer, the ... 07/06/06 - 20060145350 - High frequency conductors for packages of integrated circuits High frequency conductors can be used with packages of integrated circuits. It includes metal traces on the surface of a semiconductor chip with integrated circuits as well as electrical connections of chips in a stack to an interposer or other interfaces which must comply with requirements for high frequencies such ... 06/29/06 - 20060138670 - Method of forming copper line in semiconductor device A method of forming a copper line in a semiconductor device may enhance reliability of the copper line. The method includes the steps of forming a trench in a substrate; forming a copper layer filling the trench; planarizing the copper layer with respect to the trench; annealing the planarized copper ... 06/29/06 - 20060138669 - Semiconductor devices and methods for manufacturing the same Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer ... 06/29/06 - 20060138668 - Passivation structure for semiconductor devices A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the ... 06/22/06 - 20060131755 - Method of making circuitized substrate A method of making a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric ... 06/15/06 - 20060125103 - Information handling system An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized ... 06/01/06 - 20060113674 - Semiconductor device and manufacturing method of semiconductor device A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend ... 06/01/06 - 20060113673 - Semiconductor device and fabrication method thereof A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the ... 05/18/06 - 20060103026 - Amorphous carbon-based non-volatile memory A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A metal-containing layer is formed between the amorphous carbon layer and the second electrode. ... 05/11/06 - 20060097397 - Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device A method for providing a highly reliable, low resistance interconnect comprises forming a trench in a dielectric layer, forming a first liner in the trench then forming a resilient layer such as a tungsten layer within the trench. The resilient layer is etched back to remove the layer from a ... 05/04/06 - 20060091554 - Multilayered barrier metal thin-films A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film ... 05/04/06 - 20060091553 - Wiring board and method for producing same The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of ... 05/04/06 - 20060091552 - Refractory metal substrate with improved thermal conductivity A substrate for semiconductor and integrated circuit components including: a core plate containing a Group VIB metal from the periodic table of the elements and/or an anisotropic material, having a first major surface and a second major surface and a plurality of openings extending, at least partially, from the first ... 05/04/06 - 20060091551 - Differentially metal doped copper damascenes A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a ... 04/20/06 - 20060081993 - High luminance coated glass A coating composition and related coated substrates are disclosed. The coating composition of the present invention includes a first dielectric layer having a thickness ranging from 380 Å to 430 Å; a first metal layer over the first dielectric layer having a thickness ranging from 60 Å to 130 Å; ... 04/13/06 - 20060076685 - Selective capping of copper wiring Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided. ... 04/06/06 - 20060071340 - Methods to deposit metal alloy barrier layers Metal alloy barrier layers formed of a group VII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as ... 03/23/06 - 20060060977 - Semiconductor device A semiconductor device includes a low dielectric constant insulating layer formed above a semiconductor substrate having an element region, and a Cu wiring isolated by the low dielectric constant insulating layer. Between the low dielectric constant insulating layer and the Cu wiring, there is disposed an ionization suppressing layer containing ... 03/23/06 - 20060060976 - Integrated circuit comprising copper lines and process for forming copper lines An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation. ... 03/23/06 - 20060060975 - Semiconductor device and method for manufacturing same A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device comprises a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device comprises ... 03/23/06 - 20060060974 - Polishing composition and process for producing wiring structure using it A polishing composition comprising the following components (a) to (e): (a) silicon dioxide, (b) an alkaline compound, (c) an anticorrosive, (d) a water soluble polymer compound, and (e) water. ... 02/09/06 - 20060027931 - Semiconductor device and method fabricating the same A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the insulating film. The copper interconnection includes: a first copper interconnection having a relatively narrow width; and a second copper interconnection having a relatively ... 02/09/06 - 20060027930 - Copper alloy via bottom liner Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection ... 02/02/06 - 20060022349 - Glass substrate having a grooved portion, method for fabricating the same, and press mold for fabricating the glass substrate A press mold for fabricating a glass substrate, the glass substrate comprising a substrate; and a terrace-shaped flat portion formed on the substrate and having a grooved portion formed therein, is characterized in that the press mold comprises a top mold and a bottom mold; at least one of the ... 02/02/06 - 20060022348 - Method of sealing low-k dielectrics and devices made thereby Methods for sealing porous low-k dielectrics, and devices made thereby, are described, comprising treating the porous low-k dielectrics by atomic layer deposition so as to seal the pores. ALD reactants are chosen in part based on their size, such that they do not deeply penetrate the interconnected pore structures of ... 02/02/06 - 20060022347 - Amorphous carbon-based non-volatile memory A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A metal-containing layer is formed between the amorphous carbon layer and the second electrode. ... 01/26/06 - 20060017169 - Electroplated interconnection structures on integrated circuit chips A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features ... 01/12/06 - 20060006543 - Semiconductor device A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper ... 01/05/06 - 20060001170 - Conductive compound cap layer An interconnect structure and method thereof comprising: a interconnect and a compound cap layer. The interconnect has a compound cap layer thereover. The interconnect is preferably comprised of copper. The compound cap layer is preferably comprised of a copper-metal (Cu-Me) compound or a metal; and is more preferably comprised of ... 12/29/05 - 20050285273 - Copper alloy sputtering target and semiconductor element wiring Provided is a first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wt ppm or less of Si; a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wt ppm or less of Mn; the first or the ... 12/08/05 - 20050269708 - Tungsten encapsulated copper interconnections using electroplating An interconnection structure is provided wherein comprises a substrate having a dielectric layer with a via opening therein; wherein the opening has a barrier layer; and electrodeposited copper. ... 12/01/05 - 20050263902 - Barrier free copper interconnect by multi-layer copper seed A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers ... 11/03/05 - 20050242442 - Customizing back end of the line interconnects Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless ... 10/13/05 - 20050224986 - Stable metal structure with tungsten plug In the preferred embodiment, a thick regular-k dielectric is formed on a substrate. A tungsten plug is formed in the thick regular-k dielectric. The thick regular-k dielectric is recessed and a thin low-k dielectric is formed on the thick regular-k dielectric. The thin low-k dielectric acts as a glue layer ... 10/13/05 - 20050224985 - Circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same A circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer. An electrical ... 10/13/05 - 20050224984 - Structure and method for contact pads having a protected bondable metal plug over copper-metallized integrated circuits An integrated circuit having copper interconnecting metallization (311, 312) protected by a first, inorganic overcoat layer (320), portions of the metallization exposed in windows (301, 302) opened through the thickness of the first overcoat layer. A patterned conductive barrier layer (330) is positioned on the exposed portion of the copper ... 10/06/05 - 20050218524 - Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part ... 10/06/05 - 20050218523 - Integrated circuit with metal layer having carbon nanotubes and methods of making same A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution. ... 09/29/05 - 20050212139 - Seed layer formation The present invention produces a seed layer for the deposition of copper for metallizing integrated circuits. A diffusion barrier is deposited upon the wafer. In one embodiment of the invention, a metal oxide layer is then formed on the diffusion barrier. The oxidized metal is then reduced to a conductive ... 09/22/05 - 20050206007 - Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat layer. The metal structure comprises a patterned conductive barrier layer (330) positioned on ... 09/15/05 - 20050200025 - Low-k dielectric material system for ic application A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical ... 09/08/05 - 20050194689 - Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, ... 09/01/05 - 20050189655 - Integrated circuit chip utilizing carbon nanotube composite interconnection vias Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing ... 08/18/05 - 20050179138 - Method for creating barriers for copper diffusion A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is ... 08/18/05 - 20050179137 - Semiconductor device having copper damascene interconnection and fabricating method thereof A silicon carbon nitride film is formed on an interlayer dielectric film having Si—H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption and prevents deterioration associated with the moisture absorption by a lower-layer insulating film and a Cu film, thereby suppressing ... 07/28/05 - 20050161828 - Method for making a semiconductor device having increased conductive material reliability A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once ... 07/14/05 - 20050151264 - Fabrication process for a semiconductor integrated circuit device In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers ... 07/14/05 - 20050151263 - Wiring structure forming method and semiconductor device After a via hole to connect a lower wiring and an upper wiring not shown is formed in an insulating film using an etching stopper film and a hard mask, a base film made from tantalum is formed on the insulating film so as to cover an inner wall of ... 07/07/05 - 20050146044 - Semiconductor devices and method for fabricating the same Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by ... 07/07/05 - 20050146043 - Method and structure to form capacitor in copper damascene process for integrated circuit devices A method and resulting structure of forming a metal on metal capacitor structure for an integrated circuit device, e.g., mixed signal. The method includes forming a dual damascene structure, where the structure has a first conductive portion comprising copper material that is separated by a dielectric material from a second ... 06/30/05 - 20050140013 - Semiconductor device and manufacturing process therefor as well as plating solution A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting ... 06/30/05 - 20050140012 - Method for forming copper wiring of semiconductor device The method for forming the copper wiring of the semiconductor device includes the steps of forming a first copper wiring on a semiconductor substrate having a predetermined low structure, implanting magnesium ion on the first copper wiring, forming a magnesium oxide layer on the first copper wiring by thermal treating ... 06/16/05 - 20050127515 - Sidewall sealing of porous dielectric materials A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is patterned, and a photosensitive material is spun-on over the patterned porous dielectric material. A portion of the photosensitive material is formed over, and/or soaks into sidewalls of the ... 06/16/05 - 20050127514 - Line level air gaps In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air ... 06/09/05 - 20050121795 - Semiconductor component and corresponding fabrication/mounting method A semiconductor component (1) has a substrate (21) and a structure (22, 23) formed from semiconductor/insulator/conductor layers (24 to 26) on/in the substrate (21). Furthermore, there is an insulator layer (32) which covers the surface and at least parts of the side walls of the semiconductor component (1) but leaves ... ### FreshPatents.com Support - Terms & Conditions |