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Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit)

Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum > Layered > Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit)



Semiconductor devices with multilayer flex interconnect structures
12/04/14 - 20140353830 - Semiconductor devices with multilayer flex interconnect structures. In some embodiments, a semiconductor device may include a semiconductor chip coupled to a planar substrate and a multilayer flex interconnect structure coupled to the semiconductor chip, the multilayer flex interconnect structure including at least: a first conductive layer, a second conductive layer,...

Interconnect with hybrid metallization
11/13/14 - 20140332963 - An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating...

Semiconductor device and manufacturing method thereof
10/23/14 - 20140312499 - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties...

Semiconductor device having groove-shaped via-hole
10/16/14 - 20140306346 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Interconnect structure and method of forming the same
09/18/14 - 20140264880 - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK...

Methods and structures to facilitate through-silicon vias
09/18/14 - 20140264881 - In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad...

Interconnect structure and methods of making same
09/11/14 - 20140252628 - A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter...

Functional material systems and processes for package-level interconnects
08/14/14 - 20140225265 - Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package...

Surface modified tsv structure and methods thereof
06/26/14 - 20140175654 - Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within...

Semiconductor device including two groove-shaped patterns
05/29/14 - 20140145335 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Semiconductor device including two groove-shaped patterns
05/29/14 - 20140145336 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Copper interconnect structure and method for manufacturing the same
05/22/14 - 20140138835 - A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming...

Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
05/15/14 - 20140131874 - A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically...

Damascene gap structure
04/24/14 - 20140110845 - One or more techniques or systems for forming a damascene gap structure are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region...

Dual hard mask lithography process
04/24/14 - 20140110846 - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first...

Semiconductor device and manufacturing method thereof
04/03/14 - 20140091468 - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties...

Structure to increase resistance to electromigration
03/06/14 - 20140061923 - A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration....

Interconnect structure and method
03/06/14 - 20140061924 - An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises...

Low resistivity gate conductor
03/06/14 - 20140061925 - Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form...

Electronic structure containing a via array as a physical unclonable function
02/13/14 - 20140042627 - A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced...

Structure with sub-lithographic random conductors as a physical unclonable function
02/13/14 - 20140042628 - A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly...

Semiconducting multi-layer structure and method for manufacturing the same
02/13/14 - 20140042629 - A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and...

Semiconductor structure
01/23/14 - 20140021616 - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to...

Semiconductor substrate and method of fabricating the same
01/23/14 - 20140021617 - A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging...

Semiconductor device and method for manufacturing the same
01/16/14 - 20140015139 - According to one embodiment, a method for manufacturing a semiconductor device, includes: forming, on a first surface of a semiconductor substrate containing silicon, a ring-like insulating film having a ring-like shape; laminating a first insulating film, a first silicon film and a first metal film on the first surface and...

Corrosion/etching protection in integration circuit fabrications
12/05/13 - 20130320544 - A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and...

Semiconductor device with self-aligned interconnects and blocking portions
10/31/13 - 20130285246 - A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first...

Semiconductor device and production method of the same
10/31/13 - 20130285247 - A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and...

Through via process
10/24/13 - 20130277844 - A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a...

Semiconductor device with self-aligned interconnects
10/17/13 - 20130270704 - A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further...

Bonding pad structure with dense via array
10/03/13 - 20130256893 - A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island...

Semiconductor device and a method of manufacturing the same
09/19/13 - 20130241067 - The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly...

Interconnect structures
09/05/13 - 20130228927 - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at...

Inductors and wiring structures fabricated with limited wiring material
08/08/13 - 20130200521 - Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A...

Semiconductor device and fabrication process thereof
07/25/13 - 20130187275 - A three dimensional semiconductor integrated circuit device includes a stacking of a plurality of semiconductor chips each including a plurality of through via-plugs, in each of the semiconductor chips, a plurality of through via-plugs are connected commonly with each other by a connection pad provided on a top surface or...

Microelectronic device having metal interconnection levels connected by programmable vias
07/25/13 - 20130187276 - A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected...

Semiconductor device having groove-shaped via-hole
07/11/13 - 20130175691 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Semiconductor device having groove-shaped via-hole
07/11/13 - 20130175692 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Semiconductor device having groove-shaped via-hole
07/04/13 - 20130168865 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Electronic device and method for producing same
04/18/13 - 20130093092 - An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher...

Structure and method for reducing vertical crack propagation
03/28/13 - 20130075913 - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric...

Bonding pad structure for semiconductor devices
03/21/13 - 20130069235 - A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of...

Efficient semiconductor device cell layout utilizing underlying local connective features
03/21/13 - 20130069236 - Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which...

Semiconductor arrangement
02/21/13 - 20130043593 - A semiconductor arrangement includes a circuit carrier, a bonding wire and at least N half bridge circuits. N is an integer that amounts to at least 1. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and...

Substrate for semiconductor device, semiconductor device having the substrate, and manufacturing method thereof
02/14/13 - 20130037955 - A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal...

Multilayer metallization with stress-reducing interlayer
01/31/13 - 20130026633 - A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 μm and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer...

Semiconductor device having groove-shaped via-hole
12/20/12 - 20120319281 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Semiconductor device
12/13/12 - 20120313245 - One embodiment provides a semiconductor device having: a core substrate having first and second surfaces and an accommodation hole penetrating therethrough; a semiconductor element accommodated in the accommodation hole so that a front surface thereof is on the first surface side; a first metal film formed on a back surface...

Semiconductor device and structure for heat removal
12/06/12 - 20120306082 - A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron...

Semiconductor integrated circuit with multi-cut via and automated layout method for the same
12/06/12 - 20120306083 - A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to...

Shielded electronic components and method of manufacturing the same
11/22/12 - 20120292772 - A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant...

Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
09/27/12 - 20120241961 - Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and...

Package carrier and manufacturing method thereof
07/19/12 - 20120181696 - A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed...

Barrierless single-phase interconnect
06/21/12 - 20120153483 - A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a...

Contact array for substrate contacting
05/24/12 - 20120126410 - The present invention relates to a contact arrangement (47, 48, 49, 50, 55, 56, 57) for substrate contacting, in particular for contacting terminal faces of a semiconductor substrate (21), comprising at least one inner contact (25) of the contact arrangement that is formed on a substrate surface by a base...

Microelectronic device provided with an array of elements made from a conductive polymer with a positive temperature coefficient
05/03/12 - 20120104615 - Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient...

Layer stacks and integrated circuit arrangements
03/22/12 - 20120068345 - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is...

Process for producing a metallization level and a via level and corresponding integrated circuit
01/26/12 - 20120018889 - A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic...

Method of producing a dual damascene multilayer interconnection and multilayer interconnection structure
12/29/11 - 20110316161 - In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed...

Semiconductor article having a through silicon via and guard ring
12/01/11 - 20110291279 - Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality...

Semiconductor device and manufacturing method thereof
12/01/11 - 20110291280 - A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film...

Structure and method for manufacturing interconnect structures having self-aligned dielectric caps
11/10/11 - 20110272812 - Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level....

Semiconductor device and method of manufacturing semiconductor device
11/10/11 - 20110272813 - A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on...

Semiconductor device, and manufacturing method of semiconductor device
11/03/11 - 20110266679 - Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make...

Carbon nanotube circuit component structure
11/03/11 - 20110266680 - The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer,...

Stress layer structure
10/06/11 - 20110241212 - A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and second active stress patterns in a region where active devices are formed. The first and second active stress...

Electromigration resistant aluminum-based metal interconnect structure
09/15/11 - 20110221064 - A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of...

Multi-surface ic packaging structures
09/08/11 - 20110215475 - An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated....

Post passivation interconnection schemes on top of the ic chips
07/21/11 - 20110175227 - A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick...

Semiconductor device, method of manufacturing semiconductor device, and substrate processing apparatus
07/07/11 - 20110163452 - Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed adjacent to the insulating film. The...

Semiconductor device and method for manufacturing the same
07/07/11 - 20110163453 - a second electrode formed in an exposed state and external to the second surface of the semiconductor substrate and electrically connected to the through-substrate contact plug....