FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents


Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum > Layered > Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit)

Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit)

Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264880 - Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK...

09/18/14 - 20140264881 - Methods and structures to facilitate through-silicon vias
In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad...

09/11/14 - 20140252628 - Interconnect structure and methods of making same
A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter...

08/14/14 - 20140225265 - Functional material systems and processes for package-level interconnects
Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package...

06/26/14 - 20140175654 - Surface modified tsv structure and methods thereof
Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within...

05/29/14 - 20140145335 - Semiconductor device including two groove-shaped patterns
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

05/29/14 - 20140145336 - Semiconductor device including two groove-shaped patterns
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

05/22/14 - 20140138835 - Copper interconnect structure and method for manufacturing the same
A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming...

05/15/14 - 20140131874 - Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically...

04/24/14 - 20140110845 - Damascene gap structure
One or more techniques or systems for forming a damascene gap structure are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region...

04/24/14 - 20140110846 - Dual hard mask lithography process
A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first...

04/03/14 - 20140091468 - Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties...

03/06/14 - 20140061923 - Structure to increase resistance to electromigration
A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration....

03/06/14 - 20140061924 - Interconnect structure and method
An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises...

03/06/14 - 20140061925 - Low resistivity gate conductor
Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form...

02/13/14 - 20140042627 - Electronic structure containing a via array as a physical unclonable function
A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced...

02/13/14 - 20140042628 - Structure with sub-lithographic random conductors as a physical unclonable function
A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly...

02/13/14 - 20140042629 - Semiconducting multi-layer structure and method for manufacturing the same
A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and...

01/23/14 - 20140021616 - Semiconductor structure
A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to...

01/23/14 - 20140021617 - Semiconductor substrate and method of fabricating the same
A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging...

01/16/14 - 20140015139 - Semiconductor device and method for manufacturing the same
According to one embodiment, a method for manufacturing a semiconductor device, includes: forming, on a first surface of a semiconductor substrate containing silicon, a ring-like insulating film having a ring-like shape; laminating a first insulating film, a first silicon film and a first metal film on the first surface and...

12/05/13 - 20130320544 - Corrosion/etching protection in integration circuit fabrications
A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and...

10/31/13 - 20130285246 - Semiconductor device with self-aligned interconnects and blocking portions
A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first...

10/31/13 - 20130285247 - Semiconductor device and production method of the same
A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and...

10/24/13 - 20130277844 - Through via process
A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a...

10/17/13 - 20130270704 - Semiconductor device with self-aligned interconnects
A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further...

10/03/13 - 20130256893 - Bonding pad structure with dense via array
A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island...

09/19/13 - 20130241067 - Semiconductor device and a method of manufacturing the same
The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly...

09/05/13 - 20130228927 - Interconnect structures
A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at...

08/08/13 - 20130200521 - Inductors and wiring structures fabricated with limited wiring material
Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A...

07/25/13 - 20130187275 - Semiconductor device and fabrication process thereof
A three dimensional semiconductor integrated circuit device includes a stacking of a plurality of semiconductor chips each including a plurality of through via-plugs, in each of the semiconductor chips, a plurality of through via-plugs are connected commonly with each other by a connection pad provided on a top surface or...

07/25/13 - 20130187276 - Microelectronic device having metal interconnection levels connected by programmable vias
A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected...

07/11/13 - 20130175691 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

07/11/13 - 20130175692 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

07/04/13 - 20130168865 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

04/18/13 - 20130093092 - Electronic device and method for producing same
An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher...

03/28/13 - 20130075913 - Structure and method for reducing vertical crack propagation
A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric...

03/21/13 - 20130069235 - Bonding pad structure for semiconductor devices
A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of...

03/21/13 - 20130069236 - Efficient semiconductor device cell layout utilizing underlying local connective features
Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which...

02/21/13 - 20130043593 - Semiconductor arrangement
A semiconductor arrangement includes a circuit carrier, a bonding wire and at least N half bridge circuits. N is an integer that amounts to at least 1. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and...

02/14/13 - 20130037955 - Substrate for semiconductor device, semiconductor device having the substrate, and manufacturing method thereof
A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal...

01/31/13 - 20130026633 - Multilayer metallization with stress-reducing interlayer
A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 μm and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer...

12/20/12 - 20120319281 - Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

12/13/12 - 20120313245 - Semiconductor device
One embodiment provides a semiconductor device having: a core substrate having first and second surfaces and an accommodation hole penetrating therethrough; a semiconductor element accommodated in the accommodation hole so that a front surface thereof is on the first surface side; a first metal film formed on a back surface...

12/06/12 - 20120306082 - Semiconductor device and structure for heat removal
A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron...

12/06/12 - 20120306083 - Semiconductor integrated circuit with multi-cut via and automated layout method for the same
A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to...

11/22/12 - 20120292772 - Shielded electronic components and method of manufacturing the same
A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant...

09/27/12 - 20120241961 - Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and...

07/19/12 - 20120181696 - Package carrier and manufacturing method thereof
A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed...

06/21/12 - 20120153483 - Barrierless single-phase interconnect
A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a...

05/24/12 - 20120126410 - Contact array for substrate contacting
The present invention relates to a contact arrangement (47, 48, 49, 50, 55, 56, 57) for substrate contacting, in particular for contacting terminal faces of a semiconductor substrate (21), comprising at least one inner contact (25) of the contact arrangement that is formed on a substrate surface by a base...