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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum > Layered

Layered

Layered patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

08/21/14 - 20140231997 - Semiconductor device and method for manufacturing the same
A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0...

06/12/14 - 20140159240 - Thermal management structure with integrated heat sink
A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions for a first contact of a first type located on a first side of the device. The electroplated metal can form a bridge structure over a contact region for...

05/22/14 - 20140138830 - Metal interconnection structure
A metal interconnection structure includes a substrate and a protective laver. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity...

05/22/14 - 20140138831 - Surface finish on trace for a thermal compression flip chip (tcfc)
Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface...

05/15/14 - 20140131871 - Interconnection structure and fabrication thereof
A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in...

02/20/14 - 20140048936 - High temperature interconnect assemblies for high temperature electronics utilizing transition pads
An interconnect assembly that operates in environments well exceeding 200° C. without degradation and/or failure. The interconnect assembly of the present invention eliminates the incompatible metal interfaces of the prior art and relies on aluminum first-metal wire to electrically connect to first-metal pads on a chip and a second-metal wire...

02/06/14 - 20140035139 - Semiconductor device and method of manufacturing the same
To prevent cracking in a passivation film by oxidation of an antireflection film, a semiconductor device includes a metal wiring layer for a pad, an insulating layer which is provided so as to cover the metal wiring layer and which includes an opening portion from which a part of a...

02/06/14 - 20140035140 - Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive...

11/21/13 - 20130307151 - Method to resolve hollow metal defects in interconnects
A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where...

11/21/13 - 20130307152 - Semiconductor package and fabrication method thereof
A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating...

10/03/13 - 20130256890 - Shallow via formation by oxidation
A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may...

09/05/13 - 20130228922 - Semiconductor device structures and printed circuit boards comprising semiconductor devices
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the...

08/29/13 - 20130221526 - System in package and method for manufacturing the same
A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by...

08/08/13 - 20130200518 - Devices including metal-silicon contacts using indium arsenide films and apparatus and methods
Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in...

03/14/13 - 20130062768 - Method for the production of a substrate having a coating comprising copper, and coated substrate and device prepared by this method
A method for producing a substrate with a copper or a copper-containing coating is disclosed. The method comprises a first step wherein a first precursor, a second precursor and a substrate are provided. The first precursor is a copper complex that contains no fluorine and the second precursor is selected...

01/31/13 - 20130026631 - Semiconductor apparatus and manufacturing method thereof
Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at...

10/25/12 - 20120267784 - Semiconductor device and bonding wire
A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum....

09/13/12 - 20120228770 - Metal cap for back end of line (beol) interconnects, design structure and method of manufacture
A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal...

06/21/12 - 20120153476 - Etched wafers and methods of forming the same
Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using...

06/07/12 - 20120139112 - Selective seed layer treatment for feature plating
Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes...

05/17/12 - 20120119364 - Adding cap to copper passivation flow for electroless plating
An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad...

05/17/12 - 20120119365 - Integrated circuit devices having conductive structures with different cross sections
A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern,...

05/03/12 - 20120104610 - Interconnect structure with enhanced reliability
An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap...

05/03/12 - 20120104611 - Semiconductor structure with insulated through silicon via
Techniques described herein generally relate to laminated semiconductor structures. In some examples, method of forming a polyimide film are described. An example method may include forming a through hole in a laminated semiconductor structure that includes multiple stacked semiconductor layers. An inner wall of the laminated semiconductor structure can define...

04/05/12 - 20120080790 - Apparatus and method for uniform metal plating
Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense...

02/09/12 - 20120032331 - Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof
A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is...

02/02/12 - 20120025379 - Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication....

09/15/11 - 20110221062 - Methods for fabrication of an air gap-containing interconnect structure
Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which...

09/08/11 - 20110215473 - Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a first contact, a second contact, and an intermediate interconnection. The first contact is made of a first conductive material. The second contact is made of a second conductive material. A lower end portion of the second contact is connected to an...

08/11/11 - 20110193231 - Electronic device package and method for fabricating the same
An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop...

07/21/11 - 20110175225 - Method of forming an em protected semiconductor die
In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls....

07/07/11 - 20110163449 - Superfilled metal contact vias for semiconductor devices
In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A...

06/16/11 - 20110140274 - Forming thick metal interconnect structures for integrated circuits
Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed....

05/19/11 - 20110115090 - Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same
A photoresist conversion that changes a patterned photoresist into a permanent patterned interconnect dielectric is described. The photoresist conversion process includes adding a dielectric enabling element into a patterned photoresist. The dielectric enabling element-containing photoresist is converted into a permanent patterned dielectric material by performing a curing step. In one...

03/10/11 - 20110057315 - Memory device peripheral interconnects
An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias...

01/13/11 - 20110006425 - Semiconductor device
A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in...

11/18/10 - 20100289144 - 3d integration structure and method using bonded metal planes
A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line...

09/23/10 - 20100237500 - Semiconductor substrate and method of forming conformal solder wet-enhancement layer on bump-on-lead site
A semiconductor substrate includes a first conductive layer formed over the semiconductor substrate. The first conductive layer has first and second portions which are electrically isolated during formation of the first conductive layer. A solder resist layer is formed over the first conductive layer and semiconductor substrate. An opening is...

09/23/10 - 20100237501 - Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided...

07/22/10 - 20100181669 - Semiconductor device and method for manufacturing the same
In order to improve a bonding reliability of a semiconductor device, in the semiconductor device, the wiring patterns on the substrate surface and the connection electrodes are electrically connected by face-down mounting. The connection electrodes are formed on the connecting surface of the semiconductor element and made from a conductive...

04/01/10 - 20100078816 - Display device and method of manufacturing the same
A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum...

03/25/10 - 20100072620 - Semiconductor chip with backside conductor structure
Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure...

03/04/10 - 20100052167 - Metal line having a moxsiy/mo diffusion barrier of semiconductor device and method for forming the same
A metal line having a MoxSiy/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming...

12/31/09 - 20090321932 - Coreless substrate package with symmetric external dielectric layers
A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist...

12/10/09 - 20090302471 - Semiconductor device and manufacturing method therefor
There is provided a semiconductor device including a semiconductor substrate on which a plurality of semiconductor chips having electrode pads is formed, an internal connection terminal provided on each of the electrode pads, an insulating layer provided to cover the plurality of semiconductor chips and the internal connection terminals, and...

12/03/09 - 20090294967 - Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the...

10/08/09 - 20090250815 - Surface treatment for selective metal cap applications
Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal...

08/27/09 - 20090212431 - Thermally programmable anti-reverse engineering interconnects and methods of fabricating same
An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by...

08/13/09 - 20090200667 - Ohmic contact film in semiconductor device
The invention provides an ohmic contact film formed between a doped semiconductor material layer and a conductive material layer of a semiconductor device. The composition of the ohmic contact film according to a preferred embodiment of the invention is represented by the general formula MxQzNy, where M represents the II...

06/11/09 - 20090146304 - Carbon nanotube integrated circuit devices and methods of fabrication therefor using protected catalyst layers
A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so...

05/07/09 - 20090115060 - Integrated circuit device and method
An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer....