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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum > Layered LayeredLayered patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070252276 - Thin film for vertical form fill and seal packaging of flowable materials A multi-layer film for vertical form, film and seal systems for liquid, powder, granules and/or other flowables packaging, said multi-layer comprising: an inner layer made of polyethylene, a blend of polyethylenes or ethylene copolymers; a core, comprising one or more than one layer, made from a blend of polypropylene, linear ... 10/25/07 - 20070246829 - Semiconductor device and method for producing the same A method for producing a semiconductor device of the present invention includes forming a surface electrode on a semiconductor element, forming a solder layer by plating on one principal surface of the surface electrode, mounting the semiconductor element on the sub-mount so that the solder layer contacts a principal surface ... 10/04/07 - 20070228569 - Interconnects forming method and interconnects forming apparatus The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the ... 09/27/07 - 20070222075 - Wiring material and a semiconductor device having a wiring using the material, and the manufacturing method thereof An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display ... 09/27/07 - 20070222074 - Electric device with vertical component A method of providing an electric device with a vertical component and the device itself are disclosed. The electric device may be a transistor device, such as a FET device, with a vertical channel, such as a gate around transistor, or double-gate transistor First an elongate structure, such as a ... 08/23/07 - 20070194449 - Pattern and fabricating method therefor, device and fabricating method therefor, electro-optical apparatus, electronic apparatus, and method for fabricating active matrix substrate A method for fabricating a pattern on a substrate, includes the steps of forming banks according to formation areas of the pattern on the substrate, disposing a first function liquid between the banks, disposing a second function liquid on the first function liquid, and applying predetermined treatments to the first ... 08/02/07 - 20070176292 - Bonding pad structure Bonding pad structure is provided. The bonding pad structure comprises a semiconductor substrate having a top metal layer thereon, a first passivation layer formed on the semiconductor substrate and the top metal layer, and a bonding pad formed on the first passivation layer and connected to the top metal layer. ... 07/05/07 - 20070152332 - Single or dual damascene via level wirings and/or devices, and methods of fabricating same The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal ... 05/31/07 - 20070120255 - Semiconductor chip having island dispersion structure and method for manufacturing the same The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in ... 05/17/07 - 20070108615 - Integrated circuit system with metal-insulator-metal circuit element An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact ... 05/03/07 - 20070096319 - Method for fabricating and beol interconnect structures with simultaneous formation of high-k and low-k dielectric regions A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in ... 04/12/07 - 20070080458 - Hybrid module and method of manufacturing the same A hybrid module includes a silicon substrate having a plurality of part mounting openings formed therein, the plurality of part mounting openings composed of through holes, a plurality of mounted parts that are mounted in the part mounting openings such that input/output portion forming surfaces are substantially flush with a ... 04/05/07 - 20070075427 - Amine-free deposition of metal-nitride films A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where ... 03/29/07 - 20070069382 - Semiconductor device The invention includes a layer having an integrated circuit, a first terminal which is formed over the layer having the integrated circuit and is electrically connected to the layer having the integrated circuit, a conductive layer which functions as an antenna, which is formed over the first terminal and is ... 03/29/07 - 20070069381 - Interconnect structure with polygon cell structures Interconnect structures with polygonal cell structures. An exemplary interconnect structure comprises a substrate and a first dielectric layer, overlying the substrate and exposing a conductive feature formed therethrough and connected with the substrate, wherein the first dielectric layer includes a plurality of polygon cell structures with hollow interior. ... 02/01/07 - 20070023912 - Integrating metal with ultra low-k-dielectrics In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed ... 02/01/07 - 20070023911 - Electronic device and method for manufacturing the electronic device A method for manufacturing an electronic device in which a bonding pad composed of a foundation layer and a surface layer is formed on an Si layer or an Si-base insulation layer, comprises: forming, on the Si layer or Si-base insulation layer and by a droplet discharging method, the foundation ... 11/30/06 - 20060267198 - High performance integrated circuit device and method of making the same A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground ... 11/23/06 - 20060261477 - Method of forming contact for dual liner product A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first film is formed which extends over the second ... 11/09/06 - 20060249845 - Semiconductor device and manufacturing method of the same The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of ... 11/02/06 - 20060244143 - Coating process to enable electrophoretic deposition The present invention relates to a process for the deposition of protective coatings on complex shaped Si-based substrates which are used in articles and structures subjected to high temperature, aqueous environments comprises a non-line-of-sightprocess, particularly, electrophoretic deposition (EPD) process. ... 09/21/06 - 20060208360 - Top via pattern for bond pad structure Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line ... 08/24/06 - 20060186545 - Semiconductor chip capable of implementing wire bonding over active circuits A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the ... 07/20/06 - 20060157852 - Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined ... 07/20/06 - 20060157851 - Semiconductor device and method for manufacturing the same A semiconductor device includes a first insulating film, a second insulating film and a third insulating film that are stacked in this order, and a first wiring formed in a first wiring trench formed in the stacked insulating films. The first insulating film is made of a film whose dielectric ... 05/18/06 - 20060103022 - Semiconductor device with superimposed poly-silicon plugs A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating ... 05/04/06 - 20060091547 - Substrate provided with a thin film pattern, method of manufacturing a device, electro-optic device, and electronic instrument A thin film pattern substrate, including an area provided to the substrate to form a recess and including a wider section and a linear section connected to the wider section, wherein the wider section having a width greater than the width of the linear section, and a thin film pattern ... 05/04/06 - 20060091546 - Layer system On account of their type of coating, layer systems of the prior art often exhibit poor adhesion to the substrate. If the components are subject to high mechanical stresses, the layer can then become detached. The layer system according to the invention has separately produced anchoring means which allow stronger ... 04/27/06 - 20060087039 - Ubm structure for improving reliability and performance A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad ... 04/06/06 - 20060071335 - Semiconductor device using multi-layer unleaded metal plating, and method of manufacturing the same A semiconductor device comprises a semiconductor integrated circuit, an external connection terminal connecting the semiconductor integrated circuit to an external device, and a plurality of tin or tin-alloy plating layers formed on the external connection terminal as multiple unleaded metal plating layers. The multiple unleaded metal plating layers comprise a ... 03/23/06 - 20060060970 - Interconnection structure of integrated circuit chip An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the ... 03/16/06 - 20060055043 - Connection structure for semiconductor devices The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two ... 03/09/06 - 20060049524 - Post passivation interconnection process and structures A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. ... 02/23/06 - 20060038292 - Semiconductor device having wires that vary in wiring pitch A semiconductor device includes a first wiring layer having a first wiring pitch and a second wiring layer having a second wiring pitch that differs from the first wiring pitch. The device further includes a third wiring layer which connects the first wiring layer and the second wiring layer and ... 02/09/06 - 20060027923 - Coating process to enable electrophoretic deposition The present invention relates to a process for the deposition of protective coatings on complex shaped Si-based substrates which are used in articles and structures subjected to high temperature, aqueous environments comprises a non-line-of-sight process, particularly, electrophoretic deposition (EPD) process. ... 02/09/06 - 20060027922 - High performance metallization cap layer A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the ... 02/02/06 - 20060022340 - Electrical conducting structure and liquid crystal display device comprising the same An electrical conducting structure including an integrated circuit, a substrate, and a plurality of bumps, wherein at least one bump comprises a first conductive part connected to the integrated circuit at one end; a second conductive part connected to the integrated circuit at one end; a conductive connection part connecting ... 01/26/06 - 20060017163 - Device having contact pad with a conductive layer and a conductive passivation layer A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided ... 01/26/06 - 20060017162 - Semiconductor device and manufacturing method of the same A semiconductor device is disclosed, which comprises a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and multi-level wiring structure including first wirings at a plurality of levels, in which the first wirings at at least one of the levels are provided at different heights in a cross-sectional ... 01/19/06 - 20060012044 - Plating method Methods for depositing a metal or metal alloy on a substrate and articles made with the methods are described. The metal or metal alloy is deposited on the substrate electrolytically. The current is periodically interrupted during deposition to improve throwing power and reduce nodule formation on the metal or metal ... 01/05/06 - 20060001160 - Surface treatment of metal interconnect lines Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first ... 12/29/05 - 20050285267 - Interconnect alloys and methods and apparatus using same Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate interconnects in integrated circuits, such as memory devices. The interconnects can ... 12/22/05 - 20050280152 - Interlayer connector for preventing delamination of semiconductor device and methods of forming same An interlayer connector for preventing delamination of semiconductor layers, and methods of forming the connector are disclosed. The connector includes a first connector head in a first distal layer, a second connector head in a second distal layer and a connector body coupling the first and second connector heads. Each ... 12/08/05 - 20050269702 - Method for fabricating semiconductor device capable of scribing chips with high yield A method for fabricating a semiconductor device in which a scribe area can be diced with high yield. The method for fabricating a semiconductor device comprises (a) a step for providing a semiconductor wafer having a plurality of chip areas in which semiconductor elements are formed, and a scribe area ... 12/01/05 - 20050263889 - Semiconductor device A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A ... 10/20/05 - 20050230830 - Method and apparatus for production of metal film or the like In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are ... 07/14/05 - 20050151257 - Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate having a first area on which a semiconductor element is mounted, a second area which surrounds the first area, and a third area located in a central portion of the first area; wirings extending from the second area to the third area and formed ... 07/14/05 - 20050151256 - Freestanding multilayer ic wiring structure A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes ... 07/14/05 - 20050151255 - Semiconductor device having schottky junction electrode A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure ... 06/23/05 - 20050133918 - Via including multiple electrical paths A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. ... 06/02/05 - 20050116344 - Microelectronic element having trace formed after bond layer An article is provided which includes a structure overlying a face of an element. The structure includes a first metal layer and a wettable metal layer overlying the first metal layer. A conductive trace overlies and contacts at least one of the first metal layer and the wettable metal layer, ... ### FreshPatents.com Support - Terms & Conditions |