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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum

Of Specified Material Other Than Unalloyed Aluminum

Of Specified Material Other Than Unalloyed Aluminum patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/10/14 - 20140097537 - Thin film compositions and methods
Certain embodiments of the present invention include a versatile and scalable process, “patterned regrowth,” that allows for the spatially controlled synthesis of lateral junctions between electrically conductive graphene and insulating h-BN, as well as between intrinsic and substitutionally doped graphene. The resulting films form mechanically continuous sheets across these heterojunctions....

04/03/14 - 20140091465 - Leadframe having sloped metal terminals for wirebonding
A method of assembling semiconductor devices includes dispensing a metal paste including metal particles in a solvent onto a bonding area of a plurality of metal terminals of a leadframe. The dispensing provides a varying thickness over the bonding area. The solvent is evaporated to form a sloped metal coating...

04/03/14 - 20140091466 - Pitch quartering to create pitch halved trenches and pitch halved air gaps
A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are used for metallization of inter connecting wires....

03/27/14 - 20140084464 - Passivation scheme
A method includes forming a passivation layer over an electrically conductive pad. A stress buffer layer is formed over the passivation layer. An opening is formed through the stress buffer layer over the electrically conductive pad wherein the opening does not reach the electrically conductive pad. The stress buffer layer...

03/27/14 - 20140084465 - System and method of novel mx to mx-2
A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks...

03/27/14 - 20140084466 - Manganese silicate film forming method, processing system, semiconductor device manufacturing method and semiconductor device
According to an embodiment of present disclosure a manganese silicate film forming method for forming a manganese silicate film by transforming metal manganese to silicate. The method includes forming a metal manganese film on a silicon-containing base by using a manganese compound gas; annealing the metal manganese film in an...

03/27/14 - 20140084467 - Forming functionalized carrier structures with coreless packages
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die,...

03/20/14 - 20140077374 - Through via structure and method
An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive...

03/20/14 - 20140077375 - Substrate structure, method of mounting semiconductor chip, and solid state relay
This invention provides a substrate structure that can effectively prevent scattering of solder balls which are produced due to explosion attributable to evaporation of flux during reflow soldering, and spreading of molten solder to the surroundings. On a substrate, a semiconductor chip is mounted via solder paste. The substrate is...

03/20/14 - 20140077376 - Semiconductor chip, method for producing a semiconductor chip and method for soldering a semiconductor chip to a carrier
A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2...

03/13/14 - 20140070414 - Semiconductor plural gate lengths
Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical...

03/13/14 - 20140070415 - Microelectronic packages having trench vias and methods for the manufacture thereof
Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which...

03/13/14 - 20140070416 - Guard ring structure and method for forming the same
A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed...

03/06/14 - 20140061909 - Pre-sintered semiconductor die structure
A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried...

03/06/14 - 20140061910 - Semiconductor device structures and methods for copper bond pads
A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first...

03/06/14 - 20140061911 - Self-aligning hybridization method
A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating...

02/20/14 - 20140048935 - Integrated circuit device
An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of...

02/13/14 - 20140042624 - Power mosfet having selectively silvered pads for clip and bond wire attach
A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of...

01/23/14 - 20140021610 - Chip package and a method for manufacturing a chip package
A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad...

01/16/14 - 20140015135 - Self-aligned via interconnect using relaxed patterning exposure
Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for...

01/02/14 - 20140001633 - Copper interconnect structure and method for fabricating thereof
A method for fabricating a copper interconnect structure is disclosed. A substrate having a conductive region is provided. An insulating layer with a via opening is formed on the substrate. The via opening exposes the conductive region. A copper layer is formed on the first insulating layer and fills the...

12/26/13 - 20130341792 - Method for producing graphene, graphene produced on substrate, and graphene on substrate
A production method for producing graphene on a substrate, and the like are provided. According to the method, in a forming step heating is conducted to a solid solution temperature at which a solid solution of carbon dissolved in a metal is able to be formed, and a solid solution...

12/19/13 - 20130334686 - Carrier-free land grid array ic chip package and preparation method thereof
A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at...

12/19/13 - 20130334687 - Semiconductor device
A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and...

12/19/13 - 20130334688 - Multi-elements-doped zinc oxide film, manufacturing method and application thereof
The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of Ga2O3, Al2O3, SiO2 and ZnO according to the following percentage...

12/12/13 - 20130328195 - Utilization of a metallization scheme as an etching mask
An aspect of this disclosure includes a wafer. The wafer comprises a plurality of die regions; a plurality of kerf regions between the plurality of die regions; and a metallization area on the plurality of die regions....

11/21/13 - 20130307150 - Copper interconnect structure and its formation
A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal...

11/14/13 - 20130299985 - Process for fabricating gallium arsenide devices with copper contact layer
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols...

11/14/13 - 20130299986 - Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and at least partially over conductive elements on the semiconductor die. The photoimageable dielectric adhesive material may be removed from over the conductive elements. The conductive elements are aligned...

11/14/13 - 20130299987 - Semiconductor structure having etch stop layer
A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over...

11/07/13 - 20130292835 - Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional...

10/31/13 - 20130285243 - Easily assembled chip assembly and chip assembling method
A chip assembly includes a PCB, a connecting pad fixed on the PCB, and a chip. The connecting pad defines a through hole. The chip is received in the through hole and fixed on the PCB by an adhesive distributed in the through hole. A thickness of the adhesive is...

10/24/13 - 20130277841 - Rigid interconnect structures in package-on-package assemblies
System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling...

10/10/13 - 20130264710 - Semiconductor device
Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface...

10/03/13 - 20130256888 - Interconnect structure and method for forming the same
A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom...

10/03/13 - 20130256889 - Substrate and semiconductor device
A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region...

09/26/13 - 20130249093 - Conductive film and semiconductor device
A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction....

09/19/13 - 20130241060 - Method and composition for electrodeposition of copper in microelectronics with dipyridyl-based levelers
A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound....

09/19/13 - 20130241061 - Semiconductor element and method of manufacturing same
A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate....

09/19/13 - 20130241062 - Integrated circuits and methods for processing integrated circuits with embedded features
Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect,...

09/12/13 - 20130234330 - Semiconductor packages and methods of formation thereof
In one embodiment, a method of forming a semiconductor package includes applying a film layer having through openings over a carrier and attaching a back side of a semiconductor chip to the film layer. The semiconductor chip has contacts on a front side. The method includes using a first common...

08/29/13 - 20130221524 - Integrated circuits with improved interconnect reliability using an insulating monolayer and methods for fabricating same
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes an interlayer dielectric material having a top surface and overlying semiconductor devices formed on a semiconductor substrate. The integrated circuit includes a metal interconnect formed in the interlayer dielectric material. The metal interconnect...

08/22/13 - 20130214411 - Metal interconnect of semiconductor device and method of manufacturing the same
Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus...

08/22/13 - 20130214412 - Method of forming thin film interconnect and thin film interconnect
A method of forming a thin film interconnect in which a film is formed by sputtering method using a Cu—Ca alloy target and a thin film interconnect formed by the method, the method comprising: forming a Cu—Ca alloy film by sputtering method using a Cu—Ca alloy target that contains 0.5...

08/22/13 - 20130214413 - Conductive line structures and methods of forming the same
Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive...

08/15/13 - 20130207264 - Stress reduction apparatus
A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure,...

08/15/13 - 20130207265 - Structure and method of making the same
A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting...

08/08/13 - 20130200517 - Interposer frame and method of manufacturing the same
The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through...

08/01/13 - 20130193573 - Methods of stress balancing in gallium arsenide wafer processing
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid...

08/01/13 - 20130193574 - 3d chip stack having encapsulated chip-in-chip
A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second...

07/18/13 - 20130181349 - Semiconductor device having through-substrate via
According to an embodiment, a semiconductor device includes a first circuit block, a first through-substrate via, and a back surface wiring. The first circuit block is provided on a surface side of a semiconductor substrate. The first through-substrate via is provided along a circumference of the first circuit block so...