FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents

Of Specified Material Other Than Unalloyed Aluminum

Of Specified Material Other Than Unalloyed Aluminum patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Combined With Electrical Contact Or Lead > Of Specified Material Other Than Unalloyed Aluminum



Self-aligned via interconnect using relaxed patterning exposure
12/18/14 - 20140367855 - Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for...

Semiconductor manufacturing process and structure thereof
12/18/14 - 20140367856 - A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer...

Silicidation blocking process using optically sensitive hsq resist and organic planarizing layer
12/04/14 - 20140353825 - A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which...

Graphene-metal e-fuse
11/27/14 - 20140346674 - A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal...

Semiconductor integrated circuit and fabricating the same
11/27/14 - 20140346675 - A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second...

Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
11/13/14 - 20140332958 - A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing...

Molding material and method for packaging semiconductor chips
10/23/14 - 20140312497 - A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip...

Semiconductor device and method of manufacturing same
10/23/14 - 20140312498 - In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly...

Semiconductor device having groove-shaped via-hole
10/09/14 - 20140299987 - The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a...

Power semiconductor device fabrication method, power semiconductor device
09/25/14 - 20140284797 - A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on...

Rectifier diode
09/18/14 - 20140264860 - A rectifier diode includes a substrate defining an even number of through holes, one or a number of bare chip diodes placed on the top surface of the substrate with even number of conducting grooves thereof respectively kept in alignment with respective through holes of the substrate, and a conducting...

Sputter etch processing for heavy metal patterning in integrated circuits
09/18/14 - 20140264861 - A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of...

Interconnect structure and method
09/18/14 - 20140264862 - A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal...

Conductive line system and process
09/18/14 - 20140264863 - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to...

Surface treatment method and apparatus for semiconductor packaging
09/11/14 - 20140252614 - A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires...

Semiconductor device using carbon nanotube, and manufacturing method thereof
09/11/14 - 20140252615 - According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed...

Silicided trench contact to buried conductive layer
08/28/14 - 20140239498 - A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on...

Semiconductor device and method for production of semiconductor device
08/28/14 - 20140239499 - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto....

Semiconductor device, and method of manufacturing device
08/21/14 - 20140231995 - A device including a first substrate in which a functional element and an electrode are formed; a second substrate in which a through electrode is formed; a joining material that joins the first substrate and the second substrate while reserving a predetermined space between the functional element and the second...

Semiconductor integrated circuit and fabricating the same
07/24/14 - 20140203434 - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of...

System and method of combining damascenes and subtract metal etch for advanced back end of line interconnections
07/03/14 - 20140183735 - Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a...

Graphene electrodes for electronic devices
07/03/14 - 20140183736 - A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such...

Electronic device including electrically conductive vias having different cross-sectional areas and related methods
06/26/14 - 20140175649 - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have...

Methods and apparatus for package with interposers
06/19/14 - 20140167263 - Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of...

Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
06/19/14 - 20140167264 - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the...

Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
06/19/14 - 20140167265 - One illustrative device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in the layer of insulating material and a bi-layer cap layer comprised of a first layer of material positioned on the copper-based conductive structure and a second layer of material positioned on the first...

Semiconductor device having peripheral polymer structures
06/19/14 - 20140167266 - A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of...

Package having thermal compression flip chip (tcfc) and chip with reflow bonding on lead
06/12/14 - 20140159238 - Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of...

Methods of selectively removing a substrate material and related semiconductor structures
06/12/14 - 20140159239 - A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant...

Method for manufacturing a semiconductor component and structure therefor
06/05/14 - 20140151883 - A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated...

Systems and methods for producing low work function electrodes
05/15/14 - 20140131868 - According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution...

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
05/15/14 - 20140131869 - A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is...

Multi-chip package and manufacturing method
05/15/14 - 20140131870 - Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip,...

Thin film compositions and methods
04/10/14 - 20140097537 - Certain embodiments of the present invention include a versatile and scalable process, “patterned regrowth,” that allows for the spatially controlled synthesis of lateral junctions between electrically conductive graphene and insulating h-BN, as well as between intrinsic and substitutionally doped graphene. The resulting films form mechanically continuous sheets across these heterojunctions....

Leadframe having sloped metal terminals for wirebonding
04/03/14 - 20140091465 - A method of assembling semiconductor devices includes dispensing a metal paste including metal particles in a solvent onto a bonding area of a plurality of metal terminals of a leadframe. The dispensing provides a varying thickness over the bonding area. The solvent is evaporated to form a sloped metal coating...

Pitch quartering to create pitch halved trenches and pitch halved air gaps
04/03/14 - 20140091466 - A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are used for metallization of inter connecting wires....

Passivation scheme
03/27/14 - 20140084464 - A method includes forming a passivation layer over an electrically conductive pad. A stress buffer layer is formed over the passivation layer. An opening is formed through the stress buffer layer over the electrically conductive pad wherein the opening does not reach the electrically conductive pad. The stress buffer layer...

System and method of novel mx to mx-2
03/27/14 - 20140084465 - A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks...

Manganese silicate film forming method, processing system, semiconductor device manufacturing method and semiconductor device
03/27/14 - 20140084466 - According to an embodiment of present disclosure a manganese silicate film forming method for forming a manganese silicate film by transforming metal manganese to silicate. The method includes forming a metal manganese film on a silicon-containing base by using a manganese compound gas; annealing the metal manganese film in an...

Forming functionalized carrier structures with coreless packages
03/27/14 - 20140084467 - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die,...

Through via structure and method
03/20/14 - 20140077374 - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive...

Substrate structure, method of mounting semiconductor chip, and solid state relay
03/20/14 - 20140077375 - This invention provides a substrate structure that can effectively prevent scattering of solder balls which are produced due to explosion attributable to evaporation of flux during reflow soldering, and spreading of molten solder to the surroundings. On a substrate, a semiconductor chip is mounted via solder paste. The substrate is...

Semiconductor chip, method for producing a semiconductor chip and method for soldering a semiconductor chip to a carrier
03/20/14 - 20140077376 - A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2...

Semiconductor plural gate lengths
03/13/14 - 20140070414 - Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical...

Microelectronic packages having trench vias and methods for the manufacture thereof
03/13/14 - 20140070415 - Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which...

Guard ring structure and method for forming the same
03/13/14 - 20140070416 - A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed...

Pre-sintered semiconductor die structure
03/06/14 - 20140061909 - A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried...

Semiconductor device structures and methods for copper bond pads
03/06/14 - 20140061910 - A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first...

Self-aligning hybridization method
03/06/14 - 20140061911 - A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating...

Integrated circuit device
02/20/14 - 20140048935 - An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of...

Power mosfet having selectively silvered pads for clip and bond wire attach
02/13/14 - 20140042624 - A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of...

Chip package and a method for manufacturing a chip package
01/23/14 - 20140021610 - A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad...

Self-aligned via interconnect using relaxed patterning exposure
01/16/14 - 20140015135 - Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for...

Copper interconnect structure and method for fabricating thereof
01/02/14 - 20140001633 - A method for fabricating a copper interconnect structure is disclosed. A substrate having a conductive region is provided. An insulating layer with a via opening is formed on the substrate. The via opening exposes the conductive region. A copper layer is formed on the first insulating layer and fills the...

Method for producing graphene, graphene produced on substrate, and graphene on substrate
12/26/13 - 20130341792 - A production method for producing graphene on a substrate, and the like are provided. According to the method, in a forming step heating is conducted to a solid solution temperature at which a solid solution of carbon dissolved in a metal is able to be formed, and a solid solution...

Carrier-free land grid array ic chip package and preparation method thereof
12/19/13 - 20130334686 - A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at...

Semiconductor device
12/19/13 - 20130334687 - A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and...

Multi-elements-doped zinc oxide film, manufacturing method and application thereof
12/19/13 - 20130334688 - The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of Ga2O3, Al2O3, SiO2 and ZnO according to the following percentage...

Utilization of a metallization scheme as an etching mask
12/12/13 - 20130328195 - An aspect of this disclosure includes a wafer. The wafer comprises a plurality of die regions; a plurality of kerf regions between the plurality of die regions; and a metallization area on the plurality of die regions....

Copper interconnect structure and its formation
11/21/13 - 20130307150 - A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal...

Process for fabricating gallium arsenide devices with copper contact layer
11/14/13 - 20130299985 - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols...

Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
11/14/13 - 20130299986 - Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and at least partially over conductive elements on the semiconductor die. The photoimageable dielectric adhesive material may be removed from over the conductive elements. The conductive elements are aligned...

Semiconductor structure having etch stop layer
11/14/13 - 20130299987 - A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over...

Conformal low temperature hermetic dielectric diffusion barriers
11/07/13 - 20130292835 - Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional...

Easily assembled chip assembly and chip assembling method
10/31/13 - 20130285243 - A chip assembly includes a PCB, a connecting pad fixed on the PCB, and a chip. The connecting pad defines a through hole. The chip is received in the through hole and fixed on the PCB by an adhesive distributed in the through hole. A thickness of the adhesive is...

Rigid interconnect structures in package-on-package assemblies
10/24/13 - 20130277841 - System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling...

Semiconductor device
10/10/13 - 20130264710 - Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface...

Interconnect structure and method for forming the same
10/03/13 - 20130256888 - A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom...

Substrate and semiconductor device
10/03/13 - 20130256889 - A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region...

Conductive film and semiconductor device
09/26/13 - 20130249093 - A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction....

Method and composition for electrodeposition of copper in microelectronics with dipyridyl-based levelers
09/19/13 - 20130241060 - A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound....

Semiconductor element and method of manufacturing same
09/19/13 - 20130241061 - A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate....

Integrated circuits and methods for processing integrated circuits with embedded features
09/19/13 - 20130241062 - Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect,...