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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Bump Leads > Ball Shaped Ball ShapedBall Shaped patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/31/08 - 20080023834 - Raised solder-mask-defined (smd) solder ball pads for a laminate electronic circuit board A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad on a laminate electronic circuit board. The method may comprise forming a base bump, covering the base bump with a conductive bump layer and ... 01/24/08 - 20080017986 - Electronic component of vqfn design and method for producing the same A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points ... 01/24/08 - 20080017985 - Electronic device with a plurality of substrates and method for manufacturing same An electronic device with a plurality of substrates and method for manufacturing same is disclosed. One embodiment provides three-dimensional wiring structure including a basis substrate that includes recesses in the edge region of which electroconductive elements are arranged which cooperate with the electric contact points of substrates that are arranged ... 01/17/08 - 20080012132 - Chip structure with redistribution traces A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second ... 01/10/08 - 20080006943 - Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the ... 12/20/07 - 20070290345 - Structure and method for producing multiple size interconnections An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically ... 12/13/07 - 20070284741 - Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows ... 12/13/07 - 20070284740 - Semiconductor device with improved contacts A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic ... 12/06/07 - 20070278678 - Semiconductor device and method for fabricating the same A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and ... 12/06/07 - 20070278677 - Semiconductor module featuring solder balls having lower melting point than that of solder electrode terminals of passive element device In a semiconductor module including a wiring board having a top surface and a bottom surface, a passive element device Is soldered on the top surface of the wiring board by a first solder material, and an external solder electrode terminal is adhered on the bottom surface of the wiring ... 12/06/07 - 20070278675 - System and method to reduce metal series resistance of bumped chip Provided herein, in accordance with one aspect of the present invention, are exemplary embodiments of semiconductor chips having low metallization series resistance. In one embodiment, the semiconductor chip comprises a semiconductor substrate and a metallization structure formed on the semiconductor substrate; an under bump metallurgy (“UBM”) structure layer formed over ... 11/29/07 - 20070273026 - Semiconductor package substrate A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one ... 11/15/07 - 20070262448 - Semiconductor device, power supply apparatus using same, and electronic device A semiconductor device capable of suppressing diffusion of noise signals is provided. The semiconductor device has a BGA (Ball Grid Array) structure in which a plurality of electrode terminals to do input and/or output of signals from and to the outside is arranged in a matrix form. The semiconductor device ... 10/11/07 - 20070235874 - Semiconductor integrated circuit device A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner ... 10/11/07 - 20070235873 - Pad structures and methods for forming pad structures Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For ... 10/11/07 - 20070235872 - Semiconductor package structure A semiconductor package structure includes a semiconductor chip on which an electrical connection region having a plurality of chip bonding pads and a non-electrical connection region are defined, a substrate having a plurality of substrate bonding pads respectively corresponding to the chip bonding pads on a surface facing the semiconductor ... 10/04/07 - 20070228566 - Ball grid array package construction with raised solder ball pads The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a ... 10/04/07 - 20070228565 - Ball grid array housing having a cooling foil A ball grid array housing, a semiconductor device having a ball grid array housing and an electronic circuit are disclosed. In one embodiment, a ball grid array housing includes a substrate with solder ball connections pointing out from a housing and at least one semiconductor chip. For better heat dissipation ... 10/04/07 - 20070228564 - Flip chip bonded package applicable to fine pitch technology A flip chip bonded package applicable to a fine pitch technology uses, inter alia, insulative posts instead of using conductive bumps, which correspond to electrodes one by one. The insulative posts are assigned to every two bonding pads for the sake of flip chip bonding. This makes it possible to ... 10/04/07 - 20070228563 - High-performance semiconductor package A high-speed and high-performance semiconductor package reduces degradation of chip characteristics when chips are packaged. The semiconductor package includes a semiconductor chip including a plurality of bonding pads, a redistribution layer formed on the semiconductor chip while being connected with the bonding pads, a substrate attached to an upper surface ... 09/27/07 - 20070222073 - Structure and method to improve current-carrying capabilities of c4 joints A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer ... 09/06/07 - 20070205512 - Solder bump structure for flip chip package and method for manufacturing the same A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied ... 08/16/07 - 20070187827 - Semiconductor package, stack package using the same package and method of fabricating the same A semiconductor package may include a substrate. A conductive bump may be provided on a bottom surface of the substrate. A semiconductor chip may be provided on a top surface of the substrate. A sealing material may seal the semiconductor chip on the top of the substrate. A first conductive ... 08/16/07 - 20070187826 - 3-d package stacking system The present invention provides a system for 3D package stacking system, comprising providing a substrate, attaching a ball grid array package, in an inverted position, to the substrate, forming a lower package, the lower package having the ball grid array package and the substrate encapsulated by a molding compound and ... 08/09/07 - 20070182012 - Methods for bonding and devices according to such methods A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a ... 07/19/07 - 20070164433 - Ball grid array package A ball grid array package includes a substrate with a top and bottom surface. A circuit component is located on the bottom surface. The circuit component has a pair of ends. A pair of conductors are located on the bottom surface. The conductors are connected to the ends of the ... 06/21/07 - 20070138635 - Semiconductor device and manufacturing method of the same A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas ... 05/24/07 - 20070114664 - Packaged device and method of forming same A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to ... 05/17/07 - 20070108613 - Microelectronic connection component A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths ... 05/17/07 - 20070108612 - Chip structure and manufacturing method of the same A chip structure and a manufacturing method of the same. The chip structure includes a base, a pad, a first passivation layer, a second passivation layer and a bump. The pad is formed on the base. The first passivation layer is formed on the base exposing the pad. The second ... 05/17/07 - 20070108611 - Stacking method and stacked structure for attaching memory components to associated device A stacking method and structure for attaching memory components to a ball grid array (BGA) device are provided. A specialized carrier includes multiple memory devices such as memory die, or chip scale packaging (CSP) memory. The specialized carrier is attached to a mating supporting carrier to form a stacked structure. ... 05/03/07 - 20070096318 - Semiconductor device with solder balls having high reliability A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder ball is configured to be placed on ... 04/26/07 - 20070090529 - Method of fabricating a vertically mountable ic package A method of fabricating a vertically mountable integrated circuit (IC) package is presented. An integrated circuit is mounted on a printed circuit board (PCB) and electrically coupled to a bond pad on the PCB. The bond pad is coupled with a via that is embedded in the PCB. The IC, ... 04/12/07 - 20070080456 - Arrangement of conductive pads on grid array package and on circuit board The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group ... 04/12/07 - 20070080455 - Semiconductors and methods of making A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial ... 03/29/07 - 20070069379 - Lead-free solder ball A Sn—Ag—Cu based lead-free solder ball which does not undergo yellowing of its surface when formed into a solder bump on an electrode of an electronic part such as a BGA package. The solder ball has excellent wettability and does not form voids at the time of soldering, even when ... 03/15/07 - 20070057372 - External contact material for external contacts of a semiconductor device and method of making the same An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are ... 03/15/07 - 20070057371 - Semiconductor device A semiconductor device including: a semiconductor chip in which an integrated circuit is formed; a plurality of electrodes formed on the semiconductor chip and arranged in a plurality of rows and a plurality of columns; a plurality of resin protrusions formed on a surface of the semiconductor chip on which ... 03/01/07 - 20070045848 - Wafer structure A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation ... 03/01/07 - 20070045847 - Printed wiring board and method for fabricating the same The invention is characterized in a printed wiring board having a wiring pattern including a pad for mounting a solder ball as a connection terminal, wherein the pad is constituted by laminating a conductive layer constituting the wiring pattern, a lower layer plating layer, and an upper layer plating layer ... 03/01/07 - 20070045846 - Semiconductor packages for surface mounting and method of producing same A semiconductor package for surface mounting has a substrate having electrode patterns formed on both its surfaces which are electrically connected through passages such as throughholes formed through the substrate, all of these electrode patterns having a metal film formed by an electrolytic plating process. Semiconductor chips are wire-bonded onto ... 03/01/07 - 20070045845 - Ball grid array interface structure and method A structure and method (1000) of forming an interface for a ball grid array includes forming pad (204), (1002) on a substrate (202) and creating a positive feature (206) on the pad (1004). The positive feature (206) provides an interface for a solder ball (208). The improved pad can be ... 03/01/07 - 20070045844 - Alpha particle shields in chip packaging A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N ... 03/01/07 - 20070045843 - Substrate for a ball grid array and a method for fabricating the same The present invention relates to a substrate for a Ball Grid Array device comprising a support element, a solder ball pad arranged on the support element and adapted to be applied by a solder bump, a bond pad arranged on the support element and adapted to be bonded by a ... 02/15/07 - 20070035023 - Semiconductor device having improved mechanical and thermal reliability A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic ... 02/08/07 - 20070029674 - Board-on-chip package and stack package using the same Provided is a board-on-chip package and stack package using the same to reduce the likelihood that bonding wires in an encapsulant may be damaged due to mechanical stresses applied during a package stacking process. A semiconductor package may have a spacer provided along the opposing sides of an encapsulant. The ... 02/01/07 - 20070023910 - Dual bga alloy structure for improved board-level reliability performance A method of improving the performance of a ball grid array package under temperature cycling and drop tests is disclosed. The method comprises forming a ball grid array with two types of solder balls. The first type of ball has a composition that improves performance under temperature cycling and the ... 02/01/07 - 20070023909 - System including self-assembled interconnections A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite ... 02/01/07 - 20070023908 - Method of fabricating self-assembled electrical interconnections A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite ... 02/01/07 - 20070023907 - Self-assembled interconnection particles A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite ... 01/25/07 - 20070018324 - Wafer-level-chip-scale package and method of fabrication A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and ... 01/25/07 - 20070018323 - Reduced inductance in ball grid array packages Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within ... 01/25/07 - 20070018322 - Wafer level package and its manufacturing method A semiconductor package includes a semiconductor die having a plurality of bond pads, a first protective layer formed at the periphery of the bond pads of the semiconductor die, UBM (Under Bump Metals) formed at the bond pads of the semiconductor die, a plurality of solder balls wetted to the ... 01/18/07 - 20070013068 - Integrated circuit package and method with an electrical component embedded in a substrate via An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel ... 01/11/07 - 20070007652 - Stack type package A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate short circuits caused by prior art lead wires. ... 12/28/06 - 20060289992 - Stacked semiconductor component, fabrication method and fabrication system A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer ... 12/21/06 - 20060284316 - Chip size package A chip size package comprises a substrate to one surface of which a chip is mounted, a solder ball land formed on the other surface of the substrate and having a projecting center part, a solder mask formed on the other surface of the substrate and having an opening for ... 11/16/06 - 20060255461 - Handling and positioning of metallic plated balls for socket application in ball grid array packages A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a ... 11/16/06 - 20060255460 - Multi-chip electronic package with reduced line skew, method of making same and information handling system utilizing same An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to ... 11/16/06 - 20060255459 - Stacked semiconductor memory device A stacked semiconductor memory device includes memory device contacts to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package which is stacked above a second package. The first and second packages ... 11/02/06 - 20060244142 - Electronic component and electronic configuration An electronic component includes a substrate with outer contact areas comprising copper. Lead-free solder bumps are disposed on the outer contact areas of the electronic component. An electronic configuration includes an electronic component and a printed circuit board. The electronic component is mounted on the printed circuit board by lead-free ... 10/26/06 - 20060237845 - Semiconductor integrated circuit package having electrically disconnected solder balls for mounting Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with ... 10/26/06 - 20060237844 - Semiconductor integrated circuit package having electrically disconnected solder balls for mounting Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with ... 10/26/06 - 20060237843 - Bga-type multilayer circuit wiring board Provided is a BGA-type multilayer circuit wiring board which is mounted on a printed wiring board directly via a solder ball with the electrode pad for solder ball connection formed thereon and in which the electric connection reliability of the filled via connected to the electrode pad for solder ball ... 10/19/06 - 20060231953 - Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein There is provided a structure for mounting a semiconductor part having improved productivity, in which a bump is detached from a land portion and a method of manufacturing a mounting substrate used therein. The structure for mounting the semiconductor part includes a mounting substrate 1 having an insulating substrate 2 ... 10/19/06 - 20060231952 - Bga semiconductor chip package and mounting structure thereof In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy ... 10/12/06 - 20060226545 - Semiconductor device A semiconductor device includes: a semiconductor substrate having a semiconductor element; an electrode pad electrically connected to the semiconductor element; an insulating layer formed on the substrate, the insulating layer having an opening extended to the electrode pad; a wiring portion electrically connected to the electrode pad via the opening, ... 10/05/06 - 20060220247 - Semiconductor device and manufacturing method therefor A semiconductor device includes: a semiconductor substrate; an insulation layer which is disposed on the semiconductor substrate and includes a groove formed on a second surface of the insulation layer, opposite from a first surface of the insulation layer facing the semiconductor substrate; and a conductive part disposed on the ... 10/05/06 - 20060220246 - Bump land structure of circuit substrate for semiconductor package A bump land structure of a circuit substrate for a semiconductor package may have a combination of an SMD type bump land structure and an NSMD type bump land structure. A lower portion of a solder mask and a lower layer of a bump land may form the SMD type ... 10/05/06 - 20060220245 - Flip chip package and the fabrication thereof The invention discloses a flip chip package using an interposer to electrically and mechanically connect the chip and the carrier. The interposer comprises: an insulation layer, two adhesive layers and a plurality of conductive elements. The insulation layer is also the mechanical support of interposer and has one adhesive layer ... 10/05/06 - 20060220244 - Contact pad and bump pad arrangement for high-lead or lead-free bumps A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with ... 09/28/06 - 20060214294 - Semiconductor device and a semiconductor device manufacturing method A semiconductor device for fingerprint sensors reduces a mounting area of the semiconductor device and improves a processing capacity of assembling and testing process. The semiconductor device has a functional surface that provides a predetermined function. A semiconductor element has a circuit formation surface on which a plurality of electrodes ... 09/21/06 - 20060208359 - Double density method for wirebond interconnect A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post. ... 09/21/06 - 20060208358 - Stacked package integrated circuit The invention relates to an integrated circuit, electronic device, and method for assembling an integrated circuit package with at least one bottom module with a stacked die package comprising at least two dies within one single mold cap. To allow chip area reduction, the invention provides at least one memory ... 09/21/06 - 20060208357 - Integrated device and electronic system The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged ... 09/14/06 - 20060202335 - Tape ball grid array package with electromagnetic interference protection and method for fabricating the package A tape ball grid array (TBGA) package and method for fabricating the package utilizes at least one electrical connection between a conductive stiffener and a patterned metal layer of a tape substrate, which is connected to a solder ball that is designated to be connected to AC ground, so that ... 08/17/06 - 20060180929 - Substrate for an fbga semiconductor component An FBGA semiconductor component has a chip side for receiving a semiconductor chip, a solder ball side for applying solder balls on ball pads, and a bonding channel embodied as an opening between the chip side and the solder ball side and serving for leading through wire bridges between the ... 08/10/06 - 20060175702 - Ball grid array package A circuit assembly comprising a first circuit board and a second circuit board and an electrical connection between the first board and the second board, wherein the electrical connection comprises an outer coating of a electrically conductive first material and two inner cores of a second material, the first material ... 08/03/06 - 20060170102 - Bump structure of semiconductor device and method of manufacturing the same In connection with a bump of a semiconductor device and a manufacturing method thereof, a groove is formed in a bump pad region of a semiconductor substrate. An under bump metal layer is then formed in the groove, and a lower end portion of the bump fills the groove on ... 08/03/06 - 20060170101 - Low thermal resistance package Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and ... 07/27/06 - 20060163729 - Structure and manufacturing method of a chip scale package A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip ... 07/27/06 - 20060163728 - Semiconductor device and method for manufacturing semiconductor device A semiconductor device includes: a semiconductor chip having a plurality of electrode pads formed on a principal surface thereof; a sealing resin, which covers both (i) side surfaces of the semiconductor chip and (ii) a surface of the semiconductor chip opposite to the principal surface; and external connection pads, which ... 07/27/06 - 20060163727 - Semiconductor device The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a ... 07/20/06 - 20060157850 - Semiconductor device and manufacturing method thereof A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection ... 07/20/06 - 20060157849 - Electronic component with semiconductor chip and semiconductor wafer with contact pads, and method for the production thereof An electronic component with semiconductor chips and a semiconductor wafer with contact pads are described, as well as methods of forming such structures. The contact pads on the semiconductor chip include mesa structures that are dimensioned in such a way that they are adapted to the sizes of compression heads ... 07/06/06 - 20060145345 - Bga package substrate and method of fabricating same Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same. ... 06/15/06 - 20060125097 - Semiconductor apparatus A semiconductor apparatus includes a printed circuit board, a peripheral type first semiconductor package which has a first group of ball electrodes arranged in a peripheral type first arrangement area and a first group of additional ball electrodes arranged inside the first arrangement area and which is arranged on a ... 06/08/06 - 20060118953 - Semiconductor component having thinned die with conductive vias A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the ... 05/25/06 - 20060108686 - Semiconductor device for fingerprint recognition A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a ... 05/18/06 - 20060103021 - Bga package having substrate with exhaust hole The present invention relates to a BGA package having a substrate with an exhaust hole. The BGA package comprises the substrate, a chip and a molding compound. The substrate comprises a plurality of plated through holes electrically connecting an upper surface and a lower surface of the substrate. At least ... 05/18/06 - 20060103020 - Redistribution layer and circuit structure thereof A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, ... 05/11/06 - 20060097392 - Wafer structure, chip structure and bumping process A kind of wafer structure including a plurality of chip, first passivation layer, a plurality of buffer pad, second passivation layer, and a plurality of bump. Each chip has an active surface, on which a plurality of bonding pad are disposed. The first passivation layer is disposed on the active ... 05/04/06 - 20060091545 - Printed circuit board for high-speed electrical connectors A printed circuit board exit arrangement is disclosed for use in high speed connector mounting applications. A ground plane has one or more open areas formed in it that surround pairs of signal vias formed in the board that are used to convey differential signals. The ground plane has a ... 05/04/06 - 20060091544 - Wiring board and manufacturing method therefor A wiring board is manufactured by a step of forming a meshy cylindrical body, where plural conductive rings are connected to each other at plural positions in the respective peripheral direction, a step of forming laminated meshy sheets, by squashing the meshy cylindrical body in the radial direction, a step ... 05/04/06 - 20060091543 - Land grid array module Disclosed is a land grid array module comprising: a substrate; a plurality of active and passive components mounted on both sides of the substrate; and a molding compound for encapsulating the both sides of the substrate with the active and passive components mounted thereon. The land grid array module mounts ... 05/04/06 - 20060091542 - Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The flip chip package can further include an encapsulate. The encapsulate can protect the flip ... 04/27/06 - 20060087038 - Packaged device and method of forming same A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to ... 04/27/06 - 20060087037 - Substrate structure with embedded chip of semiconductor package and method for fabricating the same A substrate structure with embedded chips of a semiconductor package and a method for fabricating the same are proposed. First of all, a carrier structure having a first carrier plate and a second carrier plate being directly formed on the first carrier plate is provided. The second carrier plate is ... 04/27/06 - 20060087036 - Chip-size package structure and method of the same The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking ... 04/20/06 - 20060081984 - Power grid layout techniques on integrated circuits Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive ... 04/20/06 - 20060081983 - Wafer level microelectronic packaging with double isolation A microelectronic package may include front and rear covers overlying the front and rear surfaces of a microelectronic element such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector spaced from ... 04/06/06 - 20060071333 - Packaging substrate and semiconductor device A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the ... 03/16/06 - 20060055040 - Cavity ball grid array apparatus having improved inductance characteristics A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond ... 03/16/06 - 20060055039 - Stackable layer containing ball grid array package Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the ... 03/16/06 - 20060055038 - Tape ball grid array package with electromagnetic interference protection and method for fabricating the package A tape ball grid array (TBGA) package and method for fabricating the package utilizes at least one electrical connection between a conductive stiffener and a patterned metal layer of a tape substrate, which is connected to a solder ball that is designated to be connected to AC ground, so that ... 03/09/06 - 20060049523 - Wire-bonding method for connecting wire-bond pads and chip and the structure formed thereby A wire-bonding method for connecting a wire-bond pad and a chip is characterized in that a metal ball is disposed on the wire-bond pad such that a bonding wire can be electrically connected to the wire-bond pad and raised to a certain height by the metal ball. In this arrangement, ... 03/09/06 - 20060049522 - Grooved substrates for uniform underfilling solder ball assembled electronic devices A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a ... 03/02/06 - 20060043587 - Apparatus and method for reducing signal cross talk between wire bonds of semiconductor packages A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the ... 03/02/06 - 20060043586 - Board level solder joint support for bga packages under heatsink compression A system comprising a ball grid array (“BGA”) substrate adapted to electrically couple to an application board using a plurality of solder balls, and a film adapted to abut the application board and the BGA substrate, the film comprising a plurality of perforations, the solder balls adapted to couple to ... 02/23/06 - 20060038291 - Electrode structure of a semiconductor device and method of manufacturing the same In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode ... 02/16/06 - 20060033212 - Wafer level package, multi-package stack, and method of manufacturing the same A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a ... 02/16/06 - 20060033211 - Power gridding scheme An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and ... 02/09/06 - 20060027921 - Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression support In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported with respect to each other so as to prevent tilting and teetering of the lid during socketing, testing, application of heat sinks, and ... 02/02/06 - 20060022339 - Solder ball opening protrusion for semiconductor assembly A ball grid array (“BGA”) package substrate, comprising a metallic core, a layer of copper abutting at least a portion of said core, a layer of nickel abutting at least a portion of the layer of copper, a layer of gold abutting at least some of the layer of nickel, ... 01/19/06 - 20060012042 - Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same A wire-bonding substrate is described. The wire-bonding substrate includes a copper metallization and a gold surface finish disposed above and on the copper metallization. The gold surface finish completes a structure that includes at least one of a bond finger for wire bonding of a first side of the substrate, ... 01/19/06 - 20060012041 - Connection between two circuitry components A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 μm2. ... 01/19/06 - 20060012040 - Semiconductor package A semiconductor package includes a substrate, a first chip, a nonconductive adhesive, a second chip and a plurality of supporting balls. The first chip has an upper surface and a lower surface opposite to the upper surface, and the lower surface is mounted on the substrate. The nonconductive adhesive is ... 01/12/06 - 20060006536 - Bga package and manufacturing method In the ball grid array (BGA) package and its manufacturing method, an open region of a bonding pad is etched to a depth reaching below the solder mask to give an etched portion which is planar at the bottom center and slanted at the periphery. With this structure of the ... 01/05/06 - 20060001158 - Package stress management Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient ... 01/05/06 - 20060001157 - Methods and apparatus for integrated circuit ball bonding using stacked ball bumps An integrated circuit comprises at least one circuit element having at least one bond site and a passivation layer. The bond site is accessible through an aperture in the passivation layer. At least two ball bumps are disposed at the bond site. A first ball bump is bonded to the ... 12/29/05 - 20050285266 - Arrangement for increasing the reliability of substrate-based bga packages An arrangement increases the reliability of substrate-based Ball-Grid-Array (BGA) packages, with a die (chip) that is mounted on a substrate and electrically connected to interconnects of the substrate and for which the substrate is provided with solder balls arranged in a predetermined grid. The arrangement is particularly simple to realize ... 12/15/05 - 20050275099 - Semiconductor apparatus and method of manufacturing semiconductor apparatus A semiconductor apparatus comprises a circuit board on which a plurality of wiring patterns are formed, a semiconductor device having a plurality of bumps electrically connected to the wiring patterns, the semiconductor device being mounted onto the circuit board via the bumps, the wiring patterns including a pair of wiring ... 12/08/05 - 20050269701 - Semiconductor device In a semiconductor device, bonding-wires can be applied parallel to each other to electrodes of high-speed signal lines when mounting a highly densified semiconductor element on a low-cost substrate while reducing a length of the bonding-wires. An impedance-matched substrate having wiring that impedance-matched with circuits of a semiconductor element is ... 12/01/05 - 20050263888 - Integrated circuit assemblies and assembly methods A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, the method includes removing oxide from bumps, applying no-flow underfill to ... 12/01/05 - 20050263887 - Circuit carrier and fabrication method thereof A circuit carrier adapted for a pin grid array (PGA) package is disclosed. The circuit carrier comprises a substrate, at least one pin pad, at least one solder mask layer, at least one solder layer, at least one pin and a fixing layer. The pin pad is disposed over the ... 12/01/05 - 20050263886 - Integrated circuit package with optimized mold shape The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. ... 11/24/05 - 20050258540 - Semiconductor device A semiconductor device, in which it is possible to maintain high reliability in that interfacial breakdown does not occur between a solder ball and a conductive film, is provided. The semiconductor device according to the present invention comprises an uppermost layer interconnection 101, an insulating film, which is provided above ... 11/24/05 - 20050258539 - Semiconductor device A semiconductor device, which is capable of suppressing interfacial breakdown between a solder ball and a conductive film, is provided. The semiconductor device of the present invention, when “a” is distance between a terminal part of the solder ball 108 in a face coming into contact with an insulating resin ... 11/24/05 - 20050258538 - Double density method for wirebond interconnect A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post. ... 11/24/05 - 20050258537 - Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ... 11/17/05 - 20050253264 - Semiconductor device and method of manufacturing the semiconductor device A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite ... 11/03/05 - 20050242437 - Method and apparatus for supporting microelectronic substrates A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to ... 10/20/05 - 20050230829 - Semiconductor device A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on ... 10/20/05 - 20050230828 - Carrier, chip package structure, and circuit board package structure A chip package structure is provided. The chip package structure has a chip and a carrier, wherein the carrier has a package substrate and a plurality of contacts. The package substrate has a carrying surface and a back surface. The chip is disposed on the carrying surface of the package ... 10/06/05 - 20050218518 - Semiconductor device assemblies and packages including multiple semiconductor device components A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g., semiconductor devices) may be assembled with the interposer. For example, at least one contact pad of a semiconductor device component adjacent to one surface ... 10/06/05 - 20050218517 - Semiconductor flip-chip package and method for the fabrication thereof A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. ... 10/06/05 - 20050218516 - Sacrificial component A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached ... 09/29/05 - 20050212134 - Semiconductor package structure with reduced parasite capacitance and method of fabricating the same A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive ... 09/29/05 - 20050212133 - Under bump metallization layer to enable use of high tin content solder bumps Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially ... 09/29/05 - 20050212132 - Chip package and process thereof The chip package and the process thereof are disclosed. In the chip package, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover ... 09/22/05 - 20050205995 - Wire bonding method and semiconductor device A wire bonding method for bonding a plurality of conducting wires to connect first conductors and second conductors has the following steps. 1) Bonding a first conducting ball on a first first conductor. 2) Bonding a first conducting wire on the first conducting ball, the first conducting wire being connected ... 09/22/05 - 20050205994 - Signal transmitting device with vias and solder balls A signal transmitting device with vias and solder balls comprises: at least one main structure(s), a second substrate, a third substrate, at least one via(s), at least one conductive layer(s), at least one solder pad(s) and at least one solder ball(s). The main structure comprises at least one first substrate ... 09/22/05 - 20050205993 - Semiconductor device A semiconductor device includes a semiconductor chip which has a top surface, a conductive member which includes a first portion which is located on the electrode pad and a second portion which is extended from the first portion, and a sealing resin which seals the top surface of the semiconductor ... 09/15/05 - 20050200019 - Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The ... 09/15/05 - 20050200018 - Semiconductor device with increased number of external connection electrodes The semiconductor device of the present invention has a semiconductor substrate having a top surface of a quadrangular shape on which a plurality of connection pads are formed, an insulation film formed on the semiconductor substrate except the connection pads, and a plurality of external connection electrodes formed on the ... 09/08/05 - 20050194687 - Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument A semiconductor substrate has an integrated circuit, an interconnect electrically connected to the inside of the semiconductor substrate, and an electrode formed on the interconnect. A plurality of resin layers are separately formed on the semiconductor substrate so that part of the semiconductor substrate is exposed. A redistribution interconnect is ... 09/08/05 - 20050194686 - Semiconductor device and manufacturing method for the same A semiconductor device according to the present invention comprises an electrode pad electrically conducted to an electric circuit formed on an element-formed surface of a silicon wafer; a wiring pattern re-wired by being electrically conducted to the electrode pad; and an oxide film formed on a surface of the wiring ... 09/08/05 - 20050194685 - Method for mounting semiconductor chips and corresponding semiconductor chip system A method for mounting semiconductor chips includes the steps of: a) providing a semiconductor chip having a surface that has a diaphragm region and a peripheral region, the peripheral region having a mounting region; b) providing a substrate which has a surface having a recess; c) mounting the mounting region ... 09/08/05 - 20050194684 - Semiconductor device and manufacturing method for same A semiconductor device in which moisture penetration into the package interior is suppressed, comprising a rewiring layer formed by plating, with improved reliability of electrical characteristics. On the main surface of a semiconductor chip comprising circuit elements and formed on a wafer, a passivation film opposing the circuit elements is ... 09/08/05 - 20050194683 - Bonding structure and fabrication thereof A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is ... 09/01/05 - 20050189650 - Low fabrication cost, high performance, high reliability chip scale package The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is ... 08/25/05 - 20050184391 - Semiconductor device A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include ... 08/25/05 - 20050184390 - Optimized power delivery to high speed, high pin-count devices A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; ... 08/11/05 - 20050173798 - Semiconductor device and method of manufacturing the same A semiconductor device is configured such that an electrode pad connected to an internal circuit is formed on a surface of a semiconductor substrate, wires are formed near and around the electrode pad, a protective film is formed which covers the edge of the electrode pad, the wires, and the ... 08/04/05 - 20050167834 - Semiconductor device including semiconductor element mounted on another semiconductor element A semiconductor device 100 includes the first semiconductor device 110 having a plurality of bumps 3 which are formed on the backside surface thereof, and the second semiconductor device 120 having a plurality of terminals 2 which are formed on the front surface thereof and are to be electrically connected ... 08/04/05 - 20050167833 - Bumped ic, display device and electronic device using the same A driver IC, which is mounted on an active matrix substrate by means of COG, is provided. The driver IC includes an input-output circuit, an internal circuit region having a plurality of internal circuits, a plurality of substrate-coupling bumps coupled to the input-output circuit, and at least one dummy bump. ... 08/04/05 - 20050167832 - Semiconductor device and method for manufacturing the same There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one ... 07/28/05 - 20050161816 - Semiconductor device A semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, an inner annular stiffener provided on the substrate in an outer side of the semiconductor element, and an outer annular stiffener provided on the substrate in an outer side of the inner annular stiffener. The inner annular ... 07/28/05 - 20050161815 - Package of a semiconductor device with a flexible wiring substrate and method for the same A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a ... 07/14/05 - 20050151252 - Semiconductor device having capacitors for reducing power source noise A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by ... 07/14/05 - 20050151251 - Mounting substrate and electronic component using the same A mounting substrate of an embodiment of the present invention comprises a first main surface constituting a mounting surface on which an electric device is mounted, and having formed thereon an electrode pattern comprising a plurality of electrode pads that are electrically connected to the electronic device via a bump, ... 07/14/05 - 20050151250 - Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode. ... 07/07/05 - 20050146033 - High density chip level package for the packaging of integrated circuits and method to manufacture same A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The ... 07/07/05 - 20050146032 - Semiconductor chip with external connecting terminal A semiconductor device having a semiconductor chip and protective resin covering a sidewall of the semiconductor chip and having a surface formed so as to be flush with an inactive surface of the semiconductor chip. The semiconductor chip may be joined to a wiring board or another semiconductor chip. The ... 07/07/05 - 20050146031 - Low profile stacking system and method The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is ... 07/07/05 - 20050146030 - Solder ball pad structure An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact ... 06/30/05 - 20050140008 - Electronic circuit unit and method of fabricating the same A electronic circuit unit contains electrodes to which bumps of a semiconductor chip are adhered. The electrodes are arranged on an upper surface of a circuit board. Land units to which chip parts is soldered are arranged on a rear surface of the circuit board. such that an insulating plate ... 06/30/05 - 20050140007 - Semiconductor device and method of fabricating the same A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent ... 06/30/05 - 20050140006 - Method of manufacturing a semiconductor device Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and ... 06/23/05 - 20050133916 - Multiple chip package module having inverted package stacked over die A module having multiple die includes a first die on a first substrate and an inverted second package (such as a land grid array package) stacked over the first die, with, where necessary, provision (such as by a spacer) is made for a standoff between the second package and the ... 06/23/05 - 20050133915 - System and method for increasing the number of io-s on a ball grid pattern A microelectronic circuit package having an integrated circuit chip bonded through an intermediate layer to a substrate. The integrated circuit chip has pads located on opposite surfaces, with the pads on one surface bonded to wire bond fingers for connection to the substrate, and pads on the opposite surface for ... 06/09/05 - 20050121785 - Method for the hermetic encapsulation of a component For hermetic encapsulation of a component, which includes a chip with component structures applied on a substrate in a flip-chip construction, a material is applied onto the lower edge of the chip and regions of the substrate abutting the chip, and then a first continuous metal layer is applied on ... 06/02/05 - 20050116341 - Selective deposition of solder ball contacts Some embodiments of the invention include methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions ... ### FreshPatents.com Support - Terms & Conditions |