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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead > Bump Leads

Bump Leads

Bump Leads patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/10/14 - 20140097534 - Dual-phase intermetallic interconnection structure and method of fabricating the same
Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound...

04/03/14 - 20140091456 - Using collapse limiter structures between elements to reduce solder bump bridging
Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the...

04/03/14 - 20140091457 - Controlled solder height packages and assembly processes
An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the...

04/03/14 - 20140091458 - Encapsulated wafer-level chip scale (wlscp) pedestal packaging
Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite...

04/03/14 - 20140091459 - Chip-size, double side connection package and method for manufacturing the same
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the...

04/03/14 - 20140091460 - Semiconductor device and method of fabricating the same
A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The...

03/27/14 - 20140084453 - Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package
Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive...

03/27/14 - 20140084454 - Direct multiple substrate die assembly
A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one...

03/27/14 - 20140084455 - Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip;...

03/27/14 - 20140084456 - Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages
A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first...

03/27/14 - 20140084457 - Bump structures, electrical connection structures, and methods of forming the same
A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion....

03/27/14 - 20140084458 - Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; a sensing layer disposed on the first surface of the substrate, wherein the sensing layer has a sensing region; a conducting pad structure disposed on the substrate and electrically...

03/27/14 - 20140084459 - Multiple die packaging interposer structure and method
System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding...

03/27/14 - 20140084460 - Contact bumps methods of making contact bumps
Contact bumps between a contact pad and a substrate can include recesses and protrusions that can mate with the material of the substrate. The irregular mating surfaces between the contact bumps and the contact pads can enhance the bonding strength of the contacts, for example, against shear and tension forces,...

03/20/14 - 20140077355 - Three-dimensional semiconductor package device having enhanced security
A semiconductor package device that includes an integrated circuit device package having a storage circuitry is disclosed. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to (e.g., adjacent...

03/20/14 - 20140077356 - Post passivation interconnect structures and methods for forming the same
A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion....

03/20/14 - 20140077357 - Circuit substrate and process for fabricating the same
A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings...

03/20/14 - 20140077358 - Bump structure and method of forming same
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the...

03/20/14 - 20140077359 - Ladder bump structures and methods of making same
An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a...

03/20/14 - 20140077360 - Interconnection structure and method of forming same
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a...

03/20/14 - 20140077361 - Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud...

03/20/14 - 20140077362 - Semiconductor device and method of forming dual-sided interconnect structures in fo-wlcsp
A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and...

03/20/14 - 20140077363 - Semiconductor device and method of forming dual-sided interconnect structures in fo-wlcsp
A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant...

03/20/14 - 20140077364 - Semiconductor device and method of forming wire studs as vertical interconnect in fo-wlp
A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the...

03/20/14 - 20140077365 - Metal bump and method of manufacturing same
An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump...

03/20/14 - 20140077366 - Wafer level fan-out package with a fiducial die
A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed...

03/20/14 - 20140077367 - Solder interconnect with non-wettable sidewall pillars and methods of manufacture
A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall....

03/20/14 - 20140077368 - Repairing anomalous stiff pillar bumps
A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to...

03/13/14 - 20140070401 - Extrusion-resistant solder interconnect structures and methods of forming
Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4...

03/13/14 - 20140070402 - Stress reduction apparatus
A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of...

03/13/14 - 20140070403 - Packaging methods and packaged devices
Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL,...

03/13/14 - 20140070404 - Semiconductor package structure and interposer therefor
An interposer for a semiconductor package structure includes a base substrate, a plurality of passive devices formed on the base substrate, and an identification (ID) code. The base substrate includes a first surface and an opposite second surface. The ID code is formed on the first surface or the second...

03/13/14 - 20140070405 - Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
One illustrative device disclosed herein includes a device substrate having a plurality of first die formed adjacent a front side of the device substrate, a glass window wafer attached to a back side of the device substrate, wherein the glass window wafer has a plurality of openings formed therein and...

03/13/14 - 20140070406 - Devices and methods for 2.5d interposers
Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5...

03/13/14 - 20140070407 - Semiconductor package and method of fabricating the same
According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower...

03/13/14 - 20140070408 - Plating structure for wafer level packages
A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around...

03/13/14 - 20140070409 - Semiconductor device and semiconductor assembly with lead-free solder
A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least...

03/13/14 - 20140070410 - Semiconductor device and method of forming multi-layered ubm with intermediate insulating buffer layer to reduce stress for semiconductor wafer
A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed...

03/13/14 - 20140070411 - Semiconductor device
Provided is a semiconductor device in which a semiconductor element mounted on a wiring substrate is placed in a hollow portion, the hollow portion being formed by the wiring substrate, a protective member, and a wall member, with the wiring substrate, the protective member, and the wall member being a...

03/06/14 - 20140061896 - Die underfill structure and method
A method of attaching an IC wafer having a plurality of copper pillars (“CuP's) projecting from one face thereof to a substrate having a plurality of contact pads on one face thereof including applying a film having a substantial amount of filler particles therein to the one face of the...

03/06/14 - 20140061897 - Bump structures for semiconductor package
A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a...

03/06/14 - 20140061898 - Metal pads with openings in integrated circuits
A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and...

03/06/14 - 20140061899 - Wafer level package structure and manufacturing method of the same
The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back...

03/06/14 - 20140061900 - Semiconductor package with improved redistribution layer design and fabricating method thereof
A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled...

03/06/14 - 20140061901 - Precise-aligned lock-and-key bonding structures
Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad,...

02/27/14 - 20140054763 - Thin wafer handling and known good die test method
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the...

02/27/14 - 20140054764 - Semiconductor package and method of manufacturing the same
A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation...

02/27/14 - 20140054765 - Driving chip and method of manufacturing the same
A driving chip and a method of manufacturing the driving chip are disclosed. In one aspect, the method includes forming an inside metal portion of a connection terminal on a base element by patterning a first metal layer; forming a first insulating layer on the inside metal portion of the...

02/27/14 - 20140054766 - Lead-free solder bump bonding structure
According to a lead-free solder bump bonding structure, by causing the interface (IMC interface) of the intermetallic compound layer at a lead-free-solder-bump side to have scallop shapes of equal to or less than 0.02 [portions/μm] without forming in advance an Ni layer as a barrier layer on the surfaces of...

02/27/14 - 20140054767 - Terminal structure and semiconductor device
The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal...

02/27/14 - 20140054768 - Terminal structure and semiconductor device
The present invention relates to a terminal structure comprising: a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal...

02/27/14 - 20140054769 - Terminal structure, and semiconductor element and module substrate comprising the same
A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on...

02/27/14 - 20140054770 - Terminal structure, and semiconductor element and module substrate comprising the same
A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region...

02/27/14 - 20140054771 - Method for self-assembly of substrates and devices obtained thereof
A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the...