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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead

Combined With Electrical Contact Or Lead

Combined With Electrical Contact Or Lead patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/17/14 - 20140103519 - Power semiconductor module
A power semiconductor module comprising a substrate. The power semiconductor module has first and second DC voltage load current connection elements and first and second power semiconductor components. The first and second power semiconductor components are arranged along a lateral first direction of the substrate. The power semiconductor module has...

04/03/14 - 20140091454 - Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or...

04/03/14 - 20140091455 - Semiconductor device and method of using a standardized carrier in semiconductor packaging
A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first...

03/27/14 - 20140084450 - Processes for multi-layer devices utilizing layer transfer
A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered...

03/27/14 - 20140084451 - Split loop cut pattern for spacer process
A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or...

03/27/14 - 20140084452 - Element mounting board and semiconductor module
Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and...

02/13/14 - 20140042612 - Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having...

02/13/14 - 20140042613 - Semiconductor device and method of manufacturing the same
A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second...

02/06/14 - 20140035124 - Semiconductor device and manufacturing method of same
An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal...

01/16/14 - 20140015121 - Wiring substrate and manufacturing method thereof
A wiring substrate includes: a core substrate made of glass and having: a first surface; a second surface opposite to the first surface; and a side surface between the first surface and the second surface; and an insulating layer and a wiring layer, which are formed on at least one...

12/26/13 - 20130341783 - Interposer with identification system
Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the...

12/19/13 - 20130334678 - Device for supporting a substrate, as well as methods for manufacturing and using such a device
A device (10) supports a substrate during the manufacture of semiconductor components. The device includes a substantially flat plate with an upper surface (11) on which the substrate can be positioned. In some embodiments, the device (10) is of inexpensive and simple construction and allows for the passage of a...

12/19/13 - 20130334679 - Metal conservation with stripper solutions containing resorcinol
Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations...

12/05/13 - 20130320519 - Semiconductor device and method of backgrinding and singulation of semiconductor wafer while reducing kerf shifting and protecting wafer surfaces
A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and...

12/05/13 - 20130320520 - Chemically altered carbosilanes for pore sealing applications
A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will...

11/21/13 - 20130307137 - Chip package and method for forming the same
Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected...

11/21/13 - 20130307138 - Deskewed multi-die packages
A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective...

11/14/13 - 20130299964 - Method for forming a fine pattern using isotropic etching
A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first...

10/24/13 - 20130277822 - Interconnect structures for integrated circuits and their formation
An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive...

10/24/13 - 20130277823 - Split loop cut pattern for spacer process
A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or...

10/24/13 - 20130277824 - Manufacturing method for semiconductor device and semiconductor device
In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer....

10/24/13 - 20130277825 - Method for preventing corrosion of copper-aluminum intermetallic compounds
The packaging of an electric contact including a semiconductor chip (102) having terminals (101) of a first metal and connecting wires (111, 112) of a second metal, the wires forming at the terminals regions (113) of intermetallic compounds of the first and second metals; a solution of an aromatic azole...

10/17/13 - 20130270692 - Method for creating semiconductor junctions with reduced contact resistance
Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form...

09/26/13 - 20130249075 - Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package
A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the...

09/19/13 - 20130241048 - Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different cte insulating layers
A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over...

09/12/13 - 20130234314 - Flexible micro-system and fabrication method thereof
A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is...

09/05/13 - 20130228915 - Semiconductor package and fabrication method thereof
A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the...

08/29/13 - 20130221515 - Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device including a first region and a second region contacting the first region along a boundary line, includes forming a pattern having an on-boundary-line line portion with a width defined by a first line which is arranged in the first region and is parallel...

07/25/13 - 20130187264 - Low ohmic contacts
A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a...

07/18/13 - 20130181337 - Power routing with integrated decoupling capacitance
An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network (200) which comprises,...

07/11/13 - 20130175680 - Dielectric material with high mechanical strength
A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH2)n—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen,...

07/04/13 - 20130168847 - Anisotropic conductive film and electronic device including the same
An electronic device includes an anisotropic conductive film as a connection material, the anisotropic conductive film being formed from an anisotropic conductive film-forming composition. The anisotropic conductive film-forming composition includes a polycyclic aromatic ring-containing epoxy resin, a fluorene epoxy resin, nano silica and conductive particles....

06/27/13 - 20130161809 - Substrate structure, semiconductor package device, and manufacturing method of substrate structure
A substrate structure, semiconductor package device, and a manufacturing method of substrate structure are provided. The substrate structure includes a conductive structure, comprising a first metal layer, a second metal layer, and a third metal layer. The second metal layer is disposed on the first metal layer, and the third...

06/20/13 - 20130154086 - Exposing connectors in packages through selective treatment
A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component....

06/20/13 - 20130154087 - Method for forming interconnection pattern and semiconductor device
According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the...

05/30/13 - 20130134576 - Semiconductor apparatus, semiconductor-apparatus manufacturing method and electronic equipment
A method for manufacturing the semiconductor apparatus includes an anchor process of forming a barrier metal film and carrying out physical etching making use of sputter gas. The anchor process is carried out at the same time on a wire connected to the lower portion of a first aperture serving...

05/23/13 - 20130127038 - Semiconductor device bonded by an anisotropic conductive film
A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a conductive adhesive layer and an insulating adhesive layer stacked thereon, an amount of reactive monomers in the conductive adhesive layer being higher than an amount of reactive monomers in the insulating adhesive layer....

05/16/13 - 20130119531 - Semiconductor device and method for manufacturing the same
According to one embodiment, a method for manufacturing a semiconductor device includes: forming an underlayer film that contains atoms selected from the group consisting of aluminum, boron and alkaline earth metal; and forming a silicon oxide film on the underlayer film by a CVD method or an ALD method by...

05/09/13 - 20130113091 - Method of packaging semiconductor die
A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded...

05/09/13 - - Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is...

05/02/13 - 20130105965 - Chip
A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light reflective region that adjoins the light trapping region and that is able to reflect light. The...

04/04/13 - 20130082378 - Resin sealing method of semiconductor device
A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization...

03/21/13 - 20130069219 - Semiconductor package and method for manufacturing the semiconductor package
A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed...

03/21/13 - 20130069220 - Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material,...

03/14/13 - 20130062753 - C-rich carbon boron nitride dielectric films for use in electronic devices
A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or...

03/14/13 - 20130062754 - Wiring substrate and semiconductor package
A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body...

01/31/13 - 20130026617 - Methods of forming a metal silicide region in an integrated circuit
Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second...

01/10/13 - 20130009302 - Semiconductor device and manufacturing method therefor
A semiconductor device (130) including: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90a) bonded to the bonding substrate (100), the semiconductor element including a semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on...

01/03/13 - 20130001766 - Processing method and processing device of semiconductor wafer, and semiconductor wafer
According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a...

01/03/13 - 20130001767 - Package and method for manufacturing package
A method for manufacturing a package, includes preparing a substrate having a first surface on which a connecting pad is formed, mounting a sacrificing material on the connecting pad, forming a package portion covering the first surface of the substrate, exposing the sacrificing material from a surface of the package...

01/03/13 - 20130001768 - Method of manufacturing an electronic system
A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main...