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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead Combined With Electrical Contact Or LeadCombined With Electrical Contact Or Lead patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/10/08 - 20080006939 - Packaging of hybrib integrated circuits Improved sensor packaging is provided with a hybrid integration approach. In one example, an application specific integrated circuit (ASIC) for sensor signal conditioning is packaged. The ASIC package has an aperture in it that exposes a chip to chip bonding interface of the ASIC chip. The rest of the ASIC ... 11/22/07 - 20070267744 - Manufacturing a bump electrode with roughened face A semiconductor device and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit. ... 10/25/07 - 20070246827 - Semiconductor integrated circuit and method of designing semiconductor integrated circuit A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring ... 10/18/07 - 20070241455 - Method for forming dual damascenes with supercritical fluid treatments A method for forming a damascene structure by providing a single process solution for resist ashing while avoiding and repairing plasma etching damage as well as removing absorbed moisture in the dielectric layer, the method including providing a substrate comprising an uppermost photoresist layer and an opening extending through a ... 10/11/07 - 20070235869 - Integrated circuit package system with wire bond pattern An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads. ... 10/04/07 - 20070228560 - Semiconductor device that improves electrical connection reliability A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with ... 10/04/07 - 20070228558 - Semiconductor packaging unit with sliding cage A semiconductor packaging unit mounts onto a board by solder joints. The unit includes, disposed along one axis, a semiconductor component having on a rear face protruding electrical connection lugs designed to be soldered onto the board and an external cage surrounding the component and having a rear edge designed ... 10/04/07 - 20070228556 - Power semiconductor component with a power semiconductor chip and method for producing the same A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top side and its rear side, which cover essentially the entire top side and rear side, respectively. The top side also includes, alongside the large-area ... 09/27/07 - 20070222070 - Contact piece member, contactor and contact method In a contactor contact piece members can be arranged at a fine pitch, and a contact can be made surely by a small contact pressure. The contact piece members electrically connect an electronic part to an external circuit. The contact piece member is formed of an electrically conductive material in ... 09/27/07 - 20070222066 - Structure and method of forming electrodeposited contacts A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and ... 09/20/07 - 20070216025 - Device having a contacting structure A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours. ... 09/13/07 - 20070210451 - Semiconductor device and method of fabricating the same There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects. ... 09/13/07 - 20070210449 - Memory device and an array of conductive lines and methods of making the same An array of conductive lines is formed on or at least partially in a semiconductor substrate. The array includes a number of conductive lines extending in a first direction, a number of landing pads made of a conductive material, with individual landing pads being connected to corresponding ones of the ... 09/13/07 - 20070210448 - Electroless cobalt-containing liner for middle-of-the-line (mol) applications A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner ... 09/06/07 - 20070205508 - Bond pad structure for wire bonding A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate ... 09/06/07 - 20070205507 - Carbon and nitrogen based cap materials for metal hard mask scheme A semiconductor structure having a novel cap layer on a low-k dielectric layer and a method for forming the same are provided. The cap layer preferably includes a material selected from the group consisting essentially of CNx, SiCN, SiCO, SiC, and combinations thereof. The semiconductor structure further includes a via ... 08/30/07 - 20070200237 - Semiconductor device and method of manufacturing the same An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A barrier metal film is formed on an inner wall in the wiring trench except an upper end and operative to prevent ... 08/30/07 - 20070200234 - Flip-chip device having underfill in controlled gap A flip-chip and underfilled device, which includes a semiconductor chip (101) with contact pads and a workpiece (102) with contact pads in matching locations; the workpiece may be an insulating substrate or another semiconductor chip. The workpiece and the chip are spaced by a gap (103) of substantially uniform average ... 08/30/07 - 20070200233 - Bond pad structures with reduced coupling noise A bond pad structure with reduced coupling noise is provided. An exemplary embodiment of the bond pad structure comprises a first dielectric layer with a first conductive layer therein, wherein the first conductive layer is grounded. A second dielectric layer with a second conductive layer, a plurality of conductive contacts ... 08/23/07 - 20070194448 - Semiconductor interconnection line and method of forming the same An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to ... 08/23/07 - 20070194447 - Semiconductor component comprising an integrated semiconductor chip and a chip housing, and electronic device A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the underside and top side of the chip housing in such a ... 08/23/07 - 20070194446 - Memory module comprising an electronic printed circuit board and a plurality of semiconductor components and method A memory module is proposed which has a first contact bank at a first edge of its electronic printed circuit board and a second contact bank at a second edge. The printed circuit board has first lines that reach from the first contact bank as far as input connections of ... 08/23/07 - 20070194445 - Semiconductor device and manufacturing method for the same To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor ... 08/09/07 - 20070182003 - Stackable semiconductor device and method for producing the same The stackable semiconductor device includes at least one first electrode on a top side and a large-area second electrode on an underside of a semiconductor chip. The semiconductor chip also includes a control electrode on one of: the top side or the underside. Through contact blocks are arranged on the ... 08/09/07 - 20070182002 - Package structure of a microphone A kind of microphone package structure is disclosed. It comprises at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bounding pad of the substrate ... 08/09/07 - 20070182001 - Semiconductor device The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like ... 07/26/07 - 20070170585 - Composite integrated device and methods for forming thereof A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer ... 07/26/07 - 20070170584 - Semiconductor interconnect having adjacent reservoir for bonding and method for formation A semiconductor device and method has interconnects with adjoining reservoir openings. A dielectric layer is formed as part of an uppermost of the one or more interconnect layers. Openings formed in the dielectric layer result in modified portions of the dielectric layer along portions of sidewalls of the openings. The ... 07/19/07 - 20070164430 - Carbon nanotube circuit component structure The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, ... 07/19/07 - 20070164428 - High power module with open frame package A semiconductor assembly is disclosed. The semiconductor assembly includes a multilayer substrate having at least two layers with conductive patterns insulated by at least two dielectric layers. The substrate includes a first surface and a second surface. A leadless package comprising a control chip is coupled to the multilayer substrate. ... 07/12/07 - 20070158839 - Thermally balanced via A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall ... 07/12/07 - 20070158837 - Semiconductor device A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers ... 07/12/07 - 20070158835 - Method for designing interconnect for a new processing technology A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors ... 07/12/07 - 20070158834 - Electrical connections made with dissimilar metals Electrical connections between different materials. An electrical connection system includes electrical components and an electrical connection between the electrical components. The electrical connection includes a functionally graded material. A method of making an electrical connection between different materials includes the steps of: providing an electrical component which includes a material; ... 07/12/07 - 20070158833 - Integrated circuit package system including stacked die An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed ... 07/12/07 - 20070158832 - Electronic device and method of manufacturing the same An electronic device wherein an electronic element is electrically connected to a substrate through an interposer and a method of manufacturing the same are disclosed. The electronic device comprises an electronic element and an interposer including an interposer base to which the electronic element is joined and plural post electrodes ... 07/05/07 - 20070152329 - Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same A semiconductor chip, a tape package of the chip and a tape wiring substrate of the chip may be configured so as to effectively radiate heat generated from the chip externally through certain wiring patterns connected to certain pads. In an example, the chip may include a plurality of input ... 07/05/07 - 20070152328 - Fluxless chip attached processes and devices Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the ... 06/28/07 - 20070145583 - Semiconductor device and method of manufacturing the same A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an ... 06/14/07 - 20070132096 - Semiconductor device and method of manufacturing the same A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. ... 06/14/07 - 20070132095 - Integrated circuit chip with external pads and process for fabricating such a chip An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed ... 05/31/07 - 20070120252 - Nano-wire electronic device An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making ... 05/31/07 - 20070120251 - Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface ... 05/17/07 - 20070108608 - Multi-chip package semiconductor device and method of detecting a failure thereof A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output ... 05/17/07 - 20070108607 - Semiconductor device A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes ... 05/17/07 - 20070108606 - Semiconductor device A semiconductor device includes a semiconductor substrate, an electrode pad electrically connected to a circuit element formed on the semiconductor substrate, a connection wiring electrically connected to the electrode pad and extending on the semiconductor substrate, and a post electrode formed on the connection wiring. The semiconductor device further includes ... 05/17/07 - 20070108605 - Bump chip carrier semiconductor package system A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the ... 05/17/07 - 20070108604 - Stacked integrated circuit leadframe package system A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe. ... 05/17/07 - 20070108603 - Method of putting isolated metallic interconnections onto a metallic substrate A method and substrate are provided for supporting one or more electronic devices including a first layer having a plurality of interconnected metallic frames laid out in a predetermined pattern. Each frame includes a frame member surrounding at least a portion of each frame, one or more metal pads and ... 05/17/07 - 20070108602 - Mos device with a high voltage isolation structure The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried ... 05/17/07 - 20070108601 - Integrated circuit package system including ribbon bond interconnect An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device. ... 05/10/07 - 20070102814 - Semiconductor device and method of manufacturing the same In a method of manufacturing a semiconductor package, a semiconductor chip including a circuit unit that has a first circuit and a second circuit spaced apart from each other, a first conductive member for electrically connecting the first circuit to the second circuit and a cut-out portion for disconnecting the ... 05/10/07 - 20070102813 - Semiconductor device, method of manufacturing a semiconductor device and substrate to be used to manufacture a semiconductor device A semiconductor device comprises a first electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film and a second Ni film stacked in order, a second electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film ... 05/10/07 - 20070102812 - Reduction of macro level stresses in copper/low-k wafers by altering aluminum pad/passivation stack to reduce or eliminate imc cracking in post wire bonded dies A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the ... 05/03/07 - 20070096312 - Structure and self-locating method of making capped chips A capped chip is provided in which a cap member has a bottom surface facing a front surface of the chip and a top surface opposite the front surface. A plurality of through holes is desirably provided in the cap member which extend from the bottom surface to the top ... 05/03/07 - 20070096311 - Structure and method of making capped chips having vertical interconnects Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form ... 05/03/07 - 20070096310 - Semiconductor device A semiconductor device having macro circuit including concentrated fine interconnections and extension wiring for connecting the macro circuit and the outer circuit. The widths of the fine interconnections are less than 0.1 μm. An end of the extension wiring is connected to at least two of fine interconnections of the ... 05/03/07 - 20070096309 - Semiconductor device, method of forming wiring pattern, and method of generating mask wiring data A semiconductor device includes a first wiring portion and a second wiring portion. The first wiring portion is configured to include a plurality of fine wirings placed densely. The second wiring portion configured to include a wiring, which is connected to one of the plurality of fine wirings in the ... 05/03/07 - 20070096308 - Semiconductor device A semiconductor device comprises: a plurality of semiconductor chip; a socket; and a mounting board equipped with the socket. Each of the semiconductor chips has a major surface, a back surface and a plurality of connection terminals on the major surface. The socket has internal connection terminals inside and external ... 05/03/07 - 20070096307 - Semiconductor device In a semiconductor device, a occupation ratio of the surface of a resin substrate encapsulated with resin by conductor patterns provided on the same surface is set so as to be 70% or higher in order to raise the toughness of the resin substrate during heating and pressurization. Preferably, the ... 05/03/07 - 20070096306 - Semiconductor device and fabrication method thereof A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a ... 05/03/07 - 20070096305 - Semiconductor component with a thin semiconductor chip and a stiff wiring substrate, and methods for producing and further processing of thin semiconductor chips A semiconductor component includes a thin semiconductor chip and a wiring substrate that carries the semiconductor chip on its upper side and includes external contacts on its underside and/or its edge sides. The semiconductor chip is preferably produced from monocrystalline silicon having a thickness d≦25 μm. ... 05/03/07 - 20070096304 - Interconnects and heat dissipators based on nanostructures The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices. ... 04/26/07 - 20070090526 - Semiconductor device that attains a high integration A semiconductor device includes a substrate a first wiring layer and a bonding wiring layer. On the substrate, semiconductor elements are formed. The first wiring layer is laminated on the substrate. The bonding wiring layer is bondable and laminated on the first wiring layer. The first wiring layer includes a ... 04/26/07 - 20070090525 - System and method for decreasing stress on solder holding bga module to computer motherboard Mechanical stress on solder joints that hold BGA modules to computer motherboards is reduced by adding to the motherboard a topmost layer, and forming V-shaped channels into the layer next to the BGA module so that stress is shielded from the BGA module and its solder joints. ... 04/19/07 - 20070085203 - Multilayer printed wiring board A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided ... 04/19/07 - 20070085202 - Semiconductor device and communication system using the semiconductor device With respect to a semiconductor device which communicates data by wireless communication, an object of the present invention is to improve sensitivity of an antenna and to protect a chip from noise without increasing the size of the device. A coiled antenna and a semiconductor integrated circuit which is electrically ... 04/12/07 - 20070080449 - Interconnect substrate and electronic circuit device An interconnect substrate 10 includes an insulating resin layer 12 (base material), an interconnect 14 and an electrode pad 16. On the insulating resin layer 12, the interconnect 14 and the electrode pad 16 are provided. The interconnect 14 and the electrode pad are integrally formed. A first metal material, ... 04/05/07 - 20070075421 - Ultra-thin wafer system An ultra-thin wafer system providing thinning a wafer on a protective tape to an ultra-thin thickness and forming electrical interconnects on the thinned wafer on a support plate. ... 03/29/07 - 20070069377 - Clock distribution networks and conductive lines in semiconductor integrated circuits A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side ... 03/29/07 - 20070069376 - Component with chip through-contacts A panel for the production of electronic components is disclosed. The components have a substantially planar semiconductor chip with chip through-contacts which are provided with electrically conductive material. A rewiring region is subdivided into an insulating layer and also a first rewiring arranged therein, the rewiring projecting laterally beyond the ... 03/22/07 - 20070063343 - Substrate for semiconductor device and semiconductor device The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating the mounting of a circuit component, such as a decoupling capacitor, fabricated separately from the substrate. The substrate (30) for a semiconductor device, on which the circuit component ... 03/08/07 - 20070052092 - Interconnection structure An interconnection structure for a pad region of the substrate is provided. A semiconductor circuit and a pad are disposed on the substrate of the pad region. The interconnection structure includes a first and a second dielectric layers, via plugs and contact plugs. The patterned conductive layer includes an auxiliary ... 03/01/07 - 20070045839 - Lead-containing solder paste The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. ... 03/01/07 - 20070045838 - Lead-containing anodes The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. ... 03/01/07 - 20070045837 - Semiconductor device and semiconductor chip A semiconductor device including: a semiconductor layer; an electrode pad provided above the semiconductor layer; an insulating layer provided above the electrode pad and having an opening which exposes at least part of the electrode pad; and a metal electrode provided at least in the opening and including a first ... 03/01/07 - 20070045836 - Stacked chip package using warp preventing insulative material and manufacturing method thereof In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable ... 03/01/07 - 20070045835 - Chip package structure A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto ... 03/01/07 - 20070045834 - Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, ... 03/01/07 - 20070045833 - Copper bump barrier cap to reduce electrical resistance A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of the copper metal. The barrier cap is formed from nickel or cobalt and it can either be formed on ... 03/01/07 - 20070045832 - Electrical connection pattern in an electronic panel A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. Each connector has a strip connected to a bump pad. Each strip has a certain required strip width and each bump pad has a certain required pad width. Each bump pad on one electronic device ... 02/22/07 - 20070040271 - Integrated circuit package An integrated circuit package comprising: an substrate having a first main surface and a second main surface which are opposite to each other; a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and a second plurality of external terminals disposed on the second ... 02/15/07 - 20070035019 - Semiconductor component and method of manufacture A semiconductor component having a positionally adaptable locking feature and a method for manufacturing the semiconductor component using a wire bond tool. A conductive support substrate having a flag portion, a lead portion and tie-bars is provided. A semiconductor chip is coupled to the flag portion of the conductive support ... 02/08/07 - 20070029669 - Integrated circuit with low-stress under-bump metallurgy An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact ... 02/01/07 - 20070023900 - Bonding pad fabrication method, method for fabricating a bonding pad and an electronic device, and electronic device A method for fabricating a bonding pad 45 includes disposing a droplet L including a liquid containing a conductive material on a substrate P by a droplet ejection method and solidifying the disposed droplet L to forms the pad. The bonding pad 45 formed has a cylindrical shape and includes ... 02/01/07 - 20070023899 - Wiring substrate, electro-optic device, electric apparatus, method of manufacturing wiring substrate, method of manufacturing electro-optic device, and method of manufacturing electric apparatus A wiring substrate includes a substrate, a first film, and a second film formed between the substrate and the first film, and an empty space is formed between at least a part of the second film and the substrate. ... 02/01/07 - 20070023898 - Integrated circuit chip and integrated device Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are intelligently arranged to reduce the loop inductance of corresponding signal and power supply bond wires. ... 01/25/07 - 20070018317 - Semiconductor device A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above ... 01/25/07 - 20070018316 - Electrode, method for producing same and semiconductor device using same There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, ... 01/25/07 - 20070018315 - Conductive adhesive composition A conductive adhesive composition includes a cross-linkable, adhesive component, a fluxing agent, and a conductive metal that has a surface on which is present a metal oxide. The adhesive component includes an epoxy resin and the fluxing agent includes a phenol. The phenol is reactive with the metal oxide on ... 01/18/07 - 20070013063 - Self alignment features for an electronic assembly Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The ... 01/18/07 - 20070013062 - Semiconductor device A semiconductor device includes: a semiconductor substrate having a first face in which a hole is formed; an insulating section made of an insulating material, the insulating material accommodated in the hole; and a wire having a turning pattern and arranged on the insulating section. ... 01/11/07 - 20070007649 - Low cte substrates for use with low-k flip-chip package devices Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one ... 01/04/07 - 20070001301 - Under bump metallization design to reduce dielectric layer delamination An under-bump metallization (UBM) design comprises a semiconductor chip having a plurality of interconnect layers, a passivation layer atop the plurality of interconnect layers, and a UBM layer atop the passivation layer, wherein a surface of the UBM layer comprises at least a first area recessed into the passivation layer ... 12/21/06 - 20060284312 - Flip chip packaging using recessed interposer terminals A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having multiple recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the multiple recesses ... 12/21/06 - 20060284311 - Method of manufacturing self-aligned contact openings and semiconductor device A method of manufacturing self-aligned contact openings is provided. A substrate having a plurality of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the ... 12/21/06 - 20060284310 - Offset via on pad A printed circuit board with an electrically conductive bonding pad disposed on an outer surface of the printed circuit board. The bonding pad has a bonding pad perimeter at immediately bounding edges of the bonding pad. An electrically conductive via directly electrically contacts the bonding pad, and is disposed within ... 12/14/06 - 20060278981 - Electronic chip contact structure A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer. ... 12/14/06 - 20060278980 - Patterned contact A chip having at least one electrical contact having a first end proximate to the chip and a second end removed from the chip, the second end including a pattern configured to facilitate penetration of the at least one contact into a malleable contact on another chip, the pattern comprising ... 12/14/06 - 20060278979 - Die stacking recessed pad wafer design A die-to-die alignment structure is disclosed that facilitates the alignment and/or positional retention of die during a 3-D stacked assembly process. ... 12/07/06 - 20060273459 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a ... 12/07/06 - 20060273458 - Substrate structure of semiconductor package A substrate structure of a semiconductor package is proposed. The structure includes a substrate with at least one opening; a grounding ring formed on the substrate and around the opening; and a plurality of plating through holes (PTH) formed in the substrate and corresponding to the grounding ring. The grounding ... 12/07/06 - 20060273457 - Data line layout in semiconductor memory device and method of forming the same In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n<m, and M=m+1, and ... 12/07/06 - 20060273456 - Multiple spacer steps for pitch multiplication Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one ... 11/30/06 - 20060267195 - Wiring substrate and radiation detector using same A wiring substrate section 2, which has a wiring substrate 20 with through holes 20c each filled with a conductive member 21 serving as a conduction path for guiding a detected signal, is installed between a radiation detecting section 1 comprised of a scintillator 10 and a PD array 15, ... 11/23/06 - 20060261474 - Electrical connector with printed circuit board An electrical connector (1) comprises an insulative housing (10) and a conductive member (20). The conductive member is assembled in the insulative housing, and comprises a plurality of first conductive pads (21) and a plurality of second conductive pads (22) arranged in a lateral direction of the conductive member, each ... 11/09/06 - 20060249843 - Semiconductor device, circuit board, and electronic instrument A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the ... 11/09/06 - 20060249842 - Semiconductor device A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land ... 11/09/06 - 20060249841 - Small scale wires with microelectromechanical devices A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are ... 11/02/06 - 20060244137 - Semiconductor package board using a metal base A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within ... 11/02/06 - 20060244136 - Semiconductor device A semiconductor device includes a base member made of a material containing at least a thermosetting resin, and at least one semiconductor constructing body mounted on the base member, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is ... 11/02/06 - 20060244135 - Microelectronic component and assembly having leads with offset portions A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a ... 11/02/06 - 20060244134 - Multilayer printed wiring board An IC chip for a high frequency region, particularly, a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer is formed at a thickness of 30 μm on a core substrate and a conductive circuit on an interlayer resin insulation layer ... 10/05/06 - 20060220241 - Packaged semiconductor device and method of manufacture using shaped die A semiconductor packaging technique provides for a semiconductor device with improved electrical and thermal performance. According to one embodiment of the invention, die edges are shaped before encapsulation to move the peripheral area of the die, which is more susceptible to stress and cracking, further inside the molding compound. This ... 10/05/06 - 20060220240 - Analytic structure for failure analysis of semiconductor device An analytic structure includes a plurality of analytic fields formed on a predetermined region of a semiconductor substrate; semiconductor transistors arranged in the analytic fields to compose an array structure, each transistor having a gate electrode and an impurity region; wordlines arranged crosswise on the analytic fields and connecting the ... 10/05/06 - 20060220239 - Lga socket with emi protection A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies include stamped and formed contacts having an insulative plastic ... 09/28/06 - 20060214291 - Semiconductor device A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10−6/° C. to 8×10−6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of ... 09/21/06 - 20060208356 - Wiring board and method of manufacturing the same A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of ... 09/14/06 - 20060202329 - Chip package and fabricating method thereof A chip package and fabricating method thereof are provided to maintain the thermal dissipating efficiency and reduce the damage to the chip. The edge of the exposed portion would be cracked caused by external force because of the substrate of the chip is brittle. The crack in the edge of ... 08/24/06 - 20060186537 - Delamination reduction between vias and conductive pads Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board. ... 08/17/06 - 20060180927 - Contact structure and method for manufacturing the same A contact structure includes contact members having leg portions which are deflected using internal stresses. Since the internal stress is used, the leg portions of the contact members are easily and reliably deflected even when the size of the contact members is reduced in accordance with the size reduction of ... 08/10/06 - 20060175701 - Dissociated fabrication of packages and chips of integrated circuits A method of fabricating a semiconductor component includes providing a prefabricated frame that includes metal traces and lead-through contacts. A semiconductor chip is mounted into the prefabricated frame such that the semiconductor chip is embedded within a rim of the prefabricated frame. Contact regions on a surface of the semiconductor ... 08/03/06 - 20060170099 - Transistor-level signal cutting method and structure A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a ... 07/06/06 - 20060145342 - Power semiconductor component and method for the production thereof A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, ... 07/06/06 - 20060145341 - Mounting pad structure for wire-bonding type lead frame packages A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath ... 06/29/06 - 20060138656 - Electrode for an electronic device An embodiment of the present invention pertains to an electrode that includes a metal oxide layer, and a conductive layer on that metal oxide layer. The metal oxide layer is an alkali metal oxide or an alkaline earth metal oxide that is formed by: (1) decomposing a compound that includes ... 06/15/06 - 20060125094 - Solder interconnect on ic chip A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. ... 06/01/06 - 20060113665 - Wire bond interconnection A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond ... 05/18/06 - 20060103018 - Coating support and method for the selective coating of conductive tracks on one such support The present invention concerns a lining support comprising a plurality of conductive pads (12) associated with a shared addressing contact (18) and means of selecting at least one pad to be lined by electrochemical means among the plurality of pads. In accordance with the invention, the selection means comprise means ... 05/11/06 - 20060097390 - Semiconductor devices having a trench in a side portion of a conducting line pattern and methods of forming the same A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed ... 05/11/06 - 20060097389 - Nanowire interconnection and nano-scale device applications A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second ... 05/04/06 - 20060091537 - Semiconductor device and method of fabricating the same Slit-like gap regions are provided at sides of a bonding pad that surrounds a window for bonding. The bonding pad is divided into a region at the side of the window and another region at the side of an adjoining interconnection layer in which the gap regions are the boundaries ... 05/04/06 - 20060091536 - Bond pad structure with stress-buffering layer capping interconnection metal layer A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected ... 05/04/06 - 20060091535 - Fine pitch bonding pad layout and method of manufacturing same Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one embodiment, the bonding pad comprises a bonding portion having a bonding surface configured to receive an electrical connector. ... 04/27/06 - 20060087032 - Compliant interconnects for semiconductors and micromachines A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed ... 04/27/06 - 20060087031 - Assembly and method An assembly comprises a substrate, such as a printed circuit board, with an electrically insulating layer provided thereon. The electrically insulating layer defines at least one opening, said opening being formed in a shape of an indicium relating to an aspect of the assembly. ... 04/27/06 - 20060087030 - Array capacitor with resistive structure An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, ... 04/20/06 - 20060081981 - Method of forming a bond pad on an i/c chip and resulting structure A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a ... 04/13/06 - 20060076678 - Thick metal layer integrated process flow to improve power delivery and mechanical buffering A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may ... 04/13/06 - 20060076677 - Resist sidewall spacer for c4 blm undercut control A method and system for preventing undercutting of the solder bump in a C4 package by forming a barrier of resist that effectively widens the footprint of the solder bump. The BLM is then etched to the perimeter edge of the barrier rather than the solder bump, thereby precluding any ... 04/06/06 - 20060071332 - Face-to-face bonded i/o circuit die and functional logic circuit die system An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets ... 03/30/06 - 20060065977 - Reliable printed wiring board assembly employing packages with solder joints and related assembly technique An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in ... 03/30/06 - 20060065976 - Method for manufacturing wafer level chip scale package structure The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The ... 03/16/06 - 20060055034 - Projected contact structures for engaging bumped semiconductor devices and methods of making the same A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are ... 03/16/06 - 20060055033 - Methods of forming semiconductor packages The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods ... 03/16/06 - 20060055032 - Packaging with metal studs formed on solder pads A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second substrate having at least one conductive pad on its surface; at least one conductive stud; and at least one solder bump ... 03/09/06 - 20060049516 - Nickel/gold pad structure of semiconductor package and fabrication method thereof A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying ... 02/23/06 - 20060038290 - Process for making electrode pairs The present invention is a process for making a matching pair of surfaces, which involves creating a network of channels on one surface of two substrate. The substrates are then coated with one or more layers of materials, the coating extending over the regions between the channels and also partially ... 02/23/06 - 20060038289 - Integrated inductors and compliant interconnects for semiconductor packaging Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging. ... 02/16/06 - 20060033209 - Hybrid integrated circuit device In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid ... 02/16/06 - 20060033208 - Contacting structure for a semiconductor material and a method for providing such structures Contact structures and methods for forming such contact structures are disclosed. An example contact structure includes a layer of semiconductor material having an interface and an electrical contact at the interface of the layer of semiconductor material, where the electrical contact includes a granular metal. An example method for forming ... 02/09/06 - 20060027919 - Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of ... 02/09/06 - 20060027918 - Electroplated wire layout for package sawing An electroplated wire layout for package sawing comprises a substrate with a plurality of chip arrays disposed thereon. A kerf having two scribe lines is disposed between every two chip arrays. Several solder ball pads corresponding to the chip arrays are disposed on a back surface of the substrate. Each ... 02/02/06 - 20060022336 - Microelectronic packages including solder bumps and ac-coupled interconnect elements Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, ... 01/26/06 - 20060017158 - Power supply wiring structure Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings ... 01/12/06 - 20060006530 - Semiconductor device and manufacturing method therefor In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or ... 01/12/06 - 20060006529 - Semiconductor package and method for manufacturing the same A semiconductor package positioned on a first substrate includes a second substrate having a first surface and a second surface, a chip positioned on the first surface of the second substrate, a plurality of first bonding balls positioned on the second surface of the second substrate and arranged in a ... 12/22/05 - 20050280151 - Methods for forming openings in doped silicon dioxide Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas ... 12/22/05 - 20050280150 - Photolithographic techniques for producing angled lines The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal ... 12/22/05 - 20050280149 - Semiconductor device A semiconductor device should have a structure that allows locating electronic components in a region under a bonding pad. The semiconductor device includes a bonding pad constituting the external connection terminal; a region under the bonding pad including at least two copper layers and a connection via plug, under said ... 12/22/05 - 20050280148 - Device mounting board and semiconductor apparatus using the same A device mounting board for a device to be mounted on, comprising: a substrate; and a laminated film composed of a plurality of insulating layers formed on one side of the substrate. Here, any of the second and subsequent insulating layers from the substrate is a photosolder resist layer containing ... 12/22/05 - 20050280147 - Imprinting lithography using the liquid/solid transition of metals and their alloys A method is provided for imprinting a pattern having nanoscale features from a mold into the patternable layer on a substrate. The method comprises: providing the mold; forming the patternable layer on the substrate; and imprinting the mold into the patternable layer, wherein the patternable layer comprises a metal or ... 12/15/05 - 20050275093 - Semiconductor device and manufacturing method of the same The invention provides a package type semiconductor device and a manufacturing method thereof where reliability is improved without increasing a manufacturing cost. A resin layer and a supporting member are formed on a top surface of a semiconductor substrate formed with pad electrodes. Then, openings are formed penetrating the resin ... 12/15/05 - 20050275092 - Semiconductor substrate and thin processing method for semiconductor substrate A semiconductor substrate having a first substrate surface which includes a device area in which semiconductor devices are formed and a substrate peripheral portion which does not overlap with the device area. A concavo-convex portion is formed in the substrate peripheral portion. Preferably, a concavo-convex portion is formed in a ... 12/08/05 - 20050269696 - Semiconductor device and manufacturing method of the same The invention provides a semiconductor device and a manufacturing method thereof where mounting strength and accuracy can be improved without making processes complex. Grooves are formed on a back surface of a semiconductor substrate along a dicing line. Via holes are formed penetrating the semiconductor substrate from its back surface ... 11/17/05 - 20050253261 - Electronic device package structures A sealing layer is provided on the surface of a substrate such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of ... 11/17/05 - 20050253260 - Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus A surface, which is opposite to a plane polygon of a resin layer, includes a third side opposed to a first side of the plane polygon, and a fourth side oppose to a second side of the plane polygon. A first space between the first side and third side is ... 11/17/05 - 20050253259 - Integrated circuit packaging method and structure for redistributing configuration thereof A packaging method and structure for altering the configuration of an integrated circuit are disclosed. The packaging structure includes a die, a redistribution layer, a lead frame, and a passivation layer. The die has a plurality of first pads and the lead frame has a plurality of lead pads. The ... 11/17/05 - 20050253258 - Solder flow stops for semiconductor die substrates A substrate, which has semiconductor die arranged thereon, uses at least one solder flow stop, closely surrounding at least a portion of at least one mounting pad on which the die are mounted, to prevent die rotation during solder reflow. The at least one solder stop is non-wetting, during a ... 11/10/05 - 20050248030 - Semiconductor device and manufacturing method of the same The invention is directed to an improvement of reliability in a chip-size package type semiconductor device and a manufacturing method thereof. A semiconductor substrate formed with a pad electrode is prepared, and a first protection layer formed of epoxy resin is formed on a front surface of the semiconductor substrate. ... 11/10/05 - 20050248029 - Embedded chip semiconductor without wire bondings An embedded chip semiconductor has a substrate, at least one chip, an insulation boundary and a circuit pattern. The substrate has a thickness, a top surface, a bottom surface and at least one chip recess. The at least one chip has a thickness, a top face, a bottom face, outer ... 11/03/05 - 20050242432 - Semiconductor chip having pads with plural junctions for different assembly methods The present invention improves development efficiency and mass production efficiency of a semiconductor chip (LSI). The LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with the junction consisting of a window formed in ... 11/03/05 - 20050242431 - Integrated circuit dies An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent ... 11/03/05 - 20050242430 - Multi-level semiconductor device with capping layer with improved adhesion A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping ... 10/20/05 - 20050230821 - Semiconductor packages, and methods of forming semiconductor packages The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods ... 10/06/05 - 20050218513 - Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor ... 10/06/05 - 20050218512 - Semiconductor device, electrical inspection method thereof, and electronic apparatus including the semiconductor device A semiconductor device is arranged so as to include (i) a wire L1, connected directly to an LSI chip, which serves as a VGL wire for supplying a voltage VGL to the LSI chip, and (ii) a wire LB1 connected not directly to but to one of a pair of ... 09/29/05 - 20050212127 - Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) ... 09/22/05 - 20050205991 - System and method of heat dissipation in semiconductor devices The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive ... 09/15/05 - 20050200010 - Circuit board The present invention provides a circuit board which prevents an adverse effect to be caused on electronic components by flux or the like that is produced at the time of soldering. According to this invention, land patterns 6 and 7 for connecting a flat cable 5 and a slide switch ... 09/15/05 - 20050200009 - Method and apparatus for bonding a wire A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the ... 09/08/05 - 20050194680 - Electrical connection materials and electrical connection methods The present invention is to provide an electrical connection material through which an electrical connection via conductive particles can be performed reliably regardless of a little unevenness of an object. The electrical connection material is an electrical connection material 100 for electrically connecting an electrical connection portion of a first ... 09/08/05 - 20050194679 - Semiconductor device with multilayer interconnection structure A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings ... 09/08/05 - 20050194678 - Bonding pad structure, display panel and bonding pad array structure using the same and manufacturing method thereof A bonding pad structure is provided. The bonding pad is suitable for, such as display device including liquid crystal panel, printed circuit board (PCB) or other loader requiring a plurality of pins requiring high precision of bonding. The bonding pad structure includes a plurality of stacked pin layers and at ... 08/25/05 - 20050184388 - Seal ring design without stop layer punch through during via etch In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in ... 08/04/05 - 20050167828 - High performance rf inductors and transformers using bonding technique A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the ... 08/04/05 - 20050167827 - Solder alloy and semiconductor device A lead-free solder alloy and a semiconductor device are provided, both of which achieve high interconnect reliability. Internal electrodes formed on the integrated circuit side of a semiconductor chip and bonding pads formed on the upper surface of a package substrate are connected through solder bumps, whereby the semiconductor chip ... 08/04/05 - 20050167826 - Bumpless wafer scale device and board assembly A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar ... 08/04/05 - 20050167825 - Fuse corner pad for an integrated circuit A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the ... 07/28/05 - 20050161811 - Conductive sintered compact for fixing electrodes in electronic device envelope A conductive sintered compact for fixing electrodes inside an electronic device envelope is provided. The sintered compact is made of a conductive composition calcined. The conductive composition includes at least 10 vol % to 60 vol % of Ag particles, a low melting-point glass containing 10 vol % to 80 ... 07/28/05 - 20050161810 - Semiconductor device In a semiconductor device such as a chip having both of an analog circuit and a digital circuit, each of a first power supply wiring (20) for supplying power to an I/O circuit (digital circuit) positioned in the semiconductor device and a third power supply wiring (30) for supplying power ... 07/28/05 - 20050161809 - Power converter, power system provided with same, and mobile body To provide a power converter equipped with a current detector which is small and can carry out highly accurate current detection, in the power converter equipped with a power module 16 having a power controlling semiconductor element 7 disposed on the power module base 27 with a ceramic substrate 28 ... 07/21/05 - 20050156312 - Electronic component package An electronic component package and method of fabrication is provided. The electronic component package includes a ceramic substrate and a plurality of bonding pads formed on the substrate, each pad forming an interface with the ceramic. Formed on the bonding pads is a bonding material, and a plurality of electrical ... 07/14/05 - 20050151248 - Inter-dice signal transfer methods for integrated circuits The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible ... 06/30/05 - 20050140002 - Methods of forming contact structures for memory cells using etch stop layers and related devices Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the ... 06/23/05 - 20050133912 - Electrical connection structure An electrical connection structure for electrically connecting with a chip and a bearing element is provided. The chip has a first surface. The bearing element has a second surface corresponding to the first surface. The electrical connection structure includes two outer contact points on the first surface, M inner contact ... 06/23/05 - 20050133911 - Wire bonding package A wire bonding package has a housing having a plurality of pins, a circuit board installed inside the housing and having at least a trace connected to a pin of the housing, at least a die installed on the circuit board and having a plurality of bonding pads, and at ... 06/16/05 - 20050127506 - Method and an apparatus for a hard-coded bit value changeable in any layer of metal A method is disclosed to make a hard-coded bit in an integrated circuit on a semiconductor chip changeable in any one and only one metal layer of the semiconductor chip. In one embodiment, the method further comprising fabricating a cell on each metal layer of the semiconductor chip and a ... 06/16/05 - 20050127505 - Semiconductor devices integrated with wafer-level packaging Active circuit elements for semiconductor devices are integrated with chip-scale bump-out beams. In some embodiments, regions of the beam itself are employed as part of an active element. The bump-out beam is employed to construct selected components of the active circuit elements such as a resistor, an inductor, a capacitor, ... 06/16/05 - 20050127504 - Semiconductor device, semiconductor chip, method for manufacturing semiconductor device, and electronic apparatus A semiconductor device including: a semiconductor chip including a substrate, an outer-connection electrode, and a bump, wherein the bump has a first conductive layer and a second conductive layer provided on the first conductive layer, and the second conductive layer is made of copper; a wiring board having a land; ... 06/16/05 - 20050127503 - Power semiconductor module and method for producing it A power semiconductor module and a method for producing it, wherein the module includes a substrate, with conductor tracks disposed on it to suit circuitry with which the module is used and with power semiconductor components disposed on the conductor tracks. Also disposed on the conductor tracks are spacer elements ... 06/02/05 - 20050116338 - Semiconductor device A semiconductor device has a bonding pad configured to be bonded to a bonding member, a test pad configured to contact with a test probe at a test, and an internal circuit electrically connected to the bonding pad and the test pad. The boding pad overlaps with the internal circuit ... ### FreshPatents.com Support - Terms & Conditions |