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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Lead Frame > With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/24/08 - 20080017959 - Surface mount multichip devices A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, ... 01/10/08 - 20080006916 - Method of manufacturing a semiconductor device The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer ... 01/03/08 - 20080001265 - Electronic package and semiconductor device using the same A package for an electronic component including a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate ... 12/27/07 - 20070296070 - Semiconductor package having functional and auxiliary leads, and process for fabricating it A semiconductor package and a process for fabricating such a package are presented. The package has a substantially parallelepipedal block, made of an encapsulation material. Embedded within the block is at least one integrated-circuit chip and a leadframe having functional leads for electrical connection to said chip. These functional leads ... 12/27/07 - 20070296069 - Semiconductor apparatus with decoupling capacitor A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair ... 12/13/07 - 20070284710 - Method for fabricating flip-chip semiconductor package with lead frame as chip carrier A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the ... 12/06/07 - 20070278631 - Self-aligned wafer level integration system A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into ... 11/08/07 - 20070257344 - Flip chip type led lighting device manufacturing method A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the ... 11/01/07 - 20070252251 - Flip chip mounted semiconductor device package having a dimpled leadframe A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead ... 10/18/07 - 20070241433 - Semiconductor device package with base features to reduce leakage A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into ... 10/11/07 - 20070235846 - Integrated circuit package system with net spacer An integrated circuit package system that includes forming a strip level net spacer including support bars, tie bars and paddles. Configuring the support bars, the tie bars and the paddles to form open regions and interconnecting the support bars, the tie bars and the paddles to provide structural support to ... 10/11/07 - 20070235845 - Apparatus, system and method for use in mounting electronic elements The present embodiments provide surface mount devices and/or systems. In some embodiments, the surface mount devices comprise a casing with a recess in a second surface; a first lead element partially encased by the casing comprising a coupling portion extending interior to the casing generally in a first direction and ... 09/20/07 - 20070215994 - Connecting a plurality of bond pads and/or inner leads with a single bond wire An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are ... 08/30/07 - 20070200211 - Multilayer wiring substrate and method of connecting the same In the case in which an electrical connection between upper and lower layers is to be carried out through a via opening portion 16 provided on an insulating layer 14 of a wiring substrate constituting a multilayer wiring substrate, the electrical connection between the upper and lower layers is performed ... 08/30/07 - 20070200210 - Methods and apparatus for improved thermal performance and electromagnetic interference (emi) shielding in integrated circuit (ic) packages Methods and apparatus for improved thermal performance and electromagnetic interference (EMT) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of ... 08/02/07 - 20070176271 - Integrated circuit package system having die-attach pad with elevated bondline thickness An integrated circuit package system is provided. A leadframe is provided having a die-attach pad. Elevated buttons are formed on the top surface of the die-attach pad configured to support an IC die in an elevated position thereon. ... 07/26/07 - 20070170560 - Apparatus and methods for packaging integrated circuit chips with antennas formed from package lead wires Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications. ... 07/26/07 - 20070170558 - Stacked integrated circuit package system A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first ... 07/19/07 - 20070164408 - Light emitting diode packaging structure A light emitting diode (LED) packaging structure includes a package body, a lead frame and a reflective wall. The package body includes a chip accommodating space for an LED chip, and a portion of the lead frame is exposed to the chip accommodating space. The reflective wall is connected with ... 07/05/07 - 20070152309 - Light emitting diode A light emitting diode comprises: at least two electrodes; a first encapsulant layer; at least a chip; and a second encapsulant layer. The electrodes are fixed by the first encapsulant layer. The chip is electrically connected to the electrodes. The chip and the electrodes are covered with the second encapsulant ... 06/28/07 - 20070145547 - Package having exposed integrated circuit device A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality ... 06/21/07 - 20070138610 - Semiconductor package structure and method of manufacture In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug ... 06/14/07 - 20070132077 - Flip chip mlp with conductive ink The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device ... 06/14/07 - 20070132076 - High temperature package flip-chip bonding to ceramic A sensor package apparatus and method are disclosed in which a sensor die is provided and based on a substrate. An integrated circuit is generally associated with the sensor die. A leadframe is also provided, which is connected by at least one weld to the integrated circuit and the substrate. ... 06/14/07 - 20070132075 - Structure and method for thin single or multichip semiconductor qfn packages A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second ... 06/07/07 - 20070126095 - Semiconductor device and manufacturing method thereof A semiconductor device has a semiconductor package with a semiconductor element is mounted on a mounting substrate. The mounting substrate has at least two anisotropic areas which are located at both sides of a semiconductor package mounting area in a way to sandwich it and have an anisotropic linear expansion ... 06/07/07 - 20070126094 - Microelectronic package having a stiffening element and method of making same A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between ... 05/31/07 - 20070120237 - Semiconductor integrated circuit To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor ... 05/24/07 - 20070114642 - Semiconductor device having a heat spreader exposed from a seal resin A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to ... 05/24/07 - 20070114641 - Ultra-thin quad flat no-lead (qfn) package An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and ... 05/17/07 - 20070108571 - Method for fabricating semiconductor package with stacked chips A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the ... 05/17/07 - 20070108570 - Semiconductor device and method of manufacturing the same There is provided a semiconductor device 100 by which flexibility in interconnection design may be improved. The semiconductor device 100 includes: a lead frame 102 provided with an island 101 and a plurality of lead units 104; a first chip 109 which is mounted on the island 101 at the ... 05/17/07 - 20070108569 - Integrated circuit package system with interconnect support An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the ... 05/17/07 - 20070108568 - Integrated circuit package to package stacking system An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package ... 05/17/07 - 20070108567 - Integrated circuit leadless package system An integrated circuit leadless package system is presented comprising forming a QFN leadframe comprises providing a die pad, forming a fishtail tie-bar on the die pad, forming a row of an outer contact pad around the die pad, forming an additional outer contact pad around the fishtail tie-bar, and forming ... 05/17/07 - 20070108566 - Integrated circuit package system with multi-planar paddle An integrated circuit package system includes a multi-planar paddle having an uplift rim and an attached integrated circuit over the uplift rim of the multi-planar paddle. ... 05/17/07 - 20070108565 - Etched leadframe flipchip package system The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the ... 05/03/07 - 20070096275 - Supporting frame for surface-mount diode package A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting ... 05/03/07 - 20070096274 - Ims formed as can for semiconductor housing An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow ... 04/19/07 - 20070085178 - Conductor substrate, semiconductor device and production method thereof A conductor substrate for mounting a semiconductor element, at least a portion thereof mounting the semiconductor element being sealed with an insulating resin, wherein an uppermost surface layer of the conductor substrate comprises copper or an alloy thereof, and the conductor substrate is partly or entirely covered with a layer ... 04/19/07 - 20070085177 - Semiconductor package with position member The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and ... 04/12/07 - 20070080438 - Semiconductor device, semiconductor module, and method of manufacturing the semiconductor module A semiconductor light-emitting device according to an embodiment of the present invention includes chip LEDs formed on a silicon submount, in which a wiring pattern having a chip connecting terminal portion connecting the chip LEDs, an external connecting terminal portion connecting an external unit, and a plurality of lead portions ... 04/12/07 - 20070080437 - Integrated circuit package system An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure ... 03/29/07 - 20070069350 - Method and apparatus for stacking electrical components using via to provide interconnection An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on ... 03/29/07 - 20070069349 - Method for micro-electro mechanical system package A method of manufacturing a multi-substrate semiconductor package. The method includes providing a first substrate with a plurality of first dies present thereon and forming a plurality of electrical contacts on an upper surface of a lateral extension portion of at least one of the plurality of first dies on ... 03/29/07 - 20070069348 - Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a ... 03/15/07 - 20070057354 - Multi-part lead frame with dissimilar materials A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed ... 03/15/07 - 20070057353 - Multi-part lead frame with dissimilar materials A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed ... 03/08/07 - 20070052076 - Partially patterned lead frames and methods of making and using the same in semiconductor packaging A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is ... 03/08/07 - 20070052075 - Semiconductor device and method of manufacturing the same A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which ... 03/08/07 - 20070052074 - Optical coupling element, method for producing the optical coupling element, and electronic device equipped with the optical coupling element After a light emitting element is mounted to a header of a light emitting lead frame, a light receiving element is mounted to a header of a light receiving lead frame and a power element is mounted to a header of a power lead frame, the light emitting element, the ... 03/08/07 - 20070052073 - Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device A semiconductor chip 23 is mounted on an island section 22 in a lead frame composed of a lead having the island section 22, a ground-bonding lead section 28 and a lead 21a each continuing in sequence, and other lead terminal sections 21b to 21d, and then a grounding electrode ... 03/01/07 - 20070045792 - Semiconductor device and semiconductor package The semiconductor device includes a chip, a sealing resin for sealing the chip, which includes a first lateral side and a second lateral side, both of which are located adjacent to each other, and a plurality of leads that protrude from different positions on the first lateral side. The positions ... 02/22/07 - 20070040252 - Semiconductor power component with a vertical current path through a semiconductor power chip A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor ... 02/22/07 - 20070040251 - Method for connecting a die assembly to a substrate in an integrated circuit and a semiconductor device comprising a die assembly A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the ... 02/15/07 - 20070034997 - Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for producing the same The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads on the circuit carrier. The conductor ... 01/25/07 - 20070018291 - Semiconductor package without chip carrier and fabrication method thereof A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one ... 01/18/07 - 20070013040 - Packaging of a microchip device The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the ... 01/11/07 - 20070007634 - Method for manufacturing semiconductor chip package A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over ... 01/04/07 - 20070001278 - Semiconductor die package and method for making the same Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. ... 01/04/07 - 20070001277 - Substrate connector for integrated circuit devices In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar ... 12/28/06 - 20060289975 - Alignment using fiducial features The present invention relates to positioning components of an assembly using fiducial features. A first fiducial feature on a first piece of the assembly can be located. A first component can be positioned on the first piece of the assembly based on the location of the first fiducial feature. A ... 12/21/06 - 20060284291 - Lead frame structure with aperture or groove for flip chip in a leaded molded package A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes ... 12/21/06 - 20060284290 - Chip-package structure and fabrication process thereof The present invention discloses a chip-package structure and a fabrication process thereof, wherein a mount board is used as a support part, which is removed after completing the chip-package process, in order to promote the planarity, firmness and reliability of the entire package structure, to reduce the height of the ... 11/30/06 - 20060267165 - Method for efficiently producing removable peripheral cards Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention is that the integrated circuit products are produced a batch at a time, and that singulation of the batch into individualized integrated circuit ... 11/23/06 - 20060261453 - Semiconductor package and stack arrangement thereof A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the ... 11/09/06 - 20060249823 - Semiconductor package having ultra-thin thickness and method of manufacturing the same A semiconductor package having an ultra thin thickness and a method of manufacturing the same are provided. The ultra thin semiconductor package comprises a circuit board in which a through hole is formed. A semiconductor chip is located in the through hole and a connecting element electrically connects the circuit ... 11/02/06 - 20060244113 - Leadless leadframe electronic package and sensor module incorporating same A leadless optical electronic package includes a lead frame having a die-attach pad and a plurality of leadless connection pads encapsulated in and extending through an encapsulation defining a planar mounting surface that can be soldered directly to a circuit board. The die-attach pad and connection pads define internal surfaces ... 10/26/06 - 20060237827 - Thermal enhanced low profile package structure and method for fabricating the same A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while ... 10/19/06 - 20060231934 - Semiconductor device Decrease in parasitic resistance caused by paste for adhering a semiconductor device to a lead frame or by a semiconductor substrate is disclosed. In a semiconductor device having a semiconductor substrate with an electrode formed on a rear surface thereof, an uneven structure is formed on the rear surface of ... 10/05/06 - 20060220196 - Semiconductor device and method of manufacturing the same, metal component and method of manufacturing the same A semiconductor device that includes: a metal component that has at least one face sealed with resin; a semiconductor element that is electrically or thermally connected to the metal component; and a protruding portion that is formed on the one face of the metal component by a push from the ... 10/05/06 - 20060220195 - Structure and method to control underfill A silicon die having a junction side being attachable to a substrate, a backside surface spaced from the junction side and an underfill control feature to prevent an underfill from settling above said backside surface is disclosed herein. ... 09/14/06 - 20060202313 - High performance chip scale leadframe with t-shape die pad and method of manufacturing package An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second ... 08/24/06 - 20060186517 - Semiconductor package having improved adhesiveness and ground bonding A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed ... 08/24/06 - 20060186516 - Semiconductor device with semiconductor chip mounted in package A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the ... 08/17/06 - 20060180904 - Non-leaded integrated circuit package system A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated ... 08/10/06 - 20060175690 - Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect ... 08/03/06 - 20060170085 - Semiconductor device and manufacturing method thereof A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In ... 07/27/06 - 20060163705 - Surface mount semiconductor device A surface mount semiconductor device using a lead frame can suppress stress applied to a package by a load in a forming process performed for the lead frame projecting from the package at a portion at which the lead frame projects the package. Concave portions can be provided in at ... 07/20/06 - 20060157831 - Low profile ball-grid array package for high power A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder ... 07/13/06 - 20060151862 - Lead-frame-based semiconductor package and lead frame thereof A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and ... 07/13/06 - 20060151861 - Method to manufacture a universal footprint for a package with exposed chip A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer ... 07/13/06 - 20060151860 - Lead frame routed chip pads for semiconductor packages A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a ... 07/06/06 - 20060145318 - Dfn semiconductor package having reduced electrical resistance A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die ... 07/06/06 - 20060145317 - Leadframe designs for plastic cavity transistor packages The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with ... 06/29/06 - 20060138620 - Resin-encapsulated package, lead member for the same and method of fabricating the lead member A resin-encapsulated package includes a semiconductor IC chip, wherein the ratio of the size of the semiconductor IC chip to the package size of the resin-encapsulated package including the semiconductor IC chip is large to miniaturize the resin-encapsulated package. The resin-encapsulated package includes a semiconductor IC chip sealed in a ... 06/29/06 - 20060138619 - Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a ... 06/22/06 - 20060131707 - Semiconductor device package with reduced leakage A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into ... 06/15/06 - 20060125065 - Multi-part lead frame with dissimilar materials A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed ... 06/08/06 - 20060118927 - Memory module having interconnected and stacked integrated circuits A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may ... 06/08/06 - 20060118926 - Semiconductor package, memory card including the same, and mold for fabricating the memory card A semiconductor package includes a printed circuit board, a semiconductor chip mounted on the printed circuit board, a wire structured to electrically connect the printed circuit board to the semiconductor chip, and an encapsulant that protects the semiconductor chip and the wire, the encapsulant disposed on the printed circuit board ... 06/01/06 - 20060113645 - Microelectronic assemblies incorporating inductors Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap ... 05/25/06 - 20060108672 - Die bonded device and method for transistor packages The specification describes a technique for die bonding that is tailored to air cavity plastic packages for high power devices. The die bonding method is simple and effective, and eliminates the step of placement of solder preforms in the die bonding operation. According to the invention the die that are ... 05/25/06 - 20060108671 - Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side ... 05/04/06 - 20060091507 - Ic package structures having separate circuit interconnection structures and assemblies constructed thereof Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less ... 04/27/06 - 20060087011 - Wired circuit board A wired circuit board having terminals that can provide reliable placement of molten metals on the terminals, to connect between the terminals and the external terminals with a high degree of precision. An insulating base layer 3 is formed on a supporting board 2, and a conductive pattern 4 is ... 04/27/06 - 20060087010 - Ic substrate and manufacturing method thereof and semiconductor element package thereby The present invention pertains to an IC substrate, a manufacturing method thereof and a semiconductor element packaged thereby, wherein a plurality of patterned through-trenches on a metallic board are filled with an insulating material or other materials of different electric conductivity in order to separate the metallic board into a ... 04/20/06 - 20060081967 - Multichip leadframe package A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially-cut away (such as by ... 04/13/06 - 20060076657 - Die attach paddle for mounting integrated circuit die An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper ... 04/06/06 - 20060071309 - Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is formed so as to surround a periphery of the source electrode 4. ... 03/30/06 - 20060065957 - Light emitting diode device A plurality of separate lead frames can be insert-molded in a reflector composed of a white resin having a high reflectivity to form a package for an LED device. A cavity is formed in the reflector. The cavity can have an inner circumferential surface that opens wider in an upward ... 03/16/06 - 20060055011 - Robust power semiconductor package A power semiconductor package, including a leadframe having at least one first terminal, a second terminal and a third terminal. The package also includes a semiconductor power die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a ... 03/02/06 - 20060043546 - Optoelectronic component and housing Disclosed is a housing for an optoelectronic component comprising a reflector and a heat dissipating element, wherein the housing comprises a mounting portion with at least one mounting area for mounting a semiconductor chip or a component provided with at least one semiconductor chip, plus at least one reflector wall ... 02/23/06 - 20060038266 - Qfn package and method therefor A semiconductor device (20) includes an integrated circuit (22) having a plurality of bonding pads (24) located on a peripheral portion of its top surface and a groove (26) formed in its bottom surface (28). The groove (26) extends from one end to an opposite end of the IC (22). ... 02/23/06 - 20060038265 - Multi-path bar bond connector for an integrated circuit assembly A solderable bar bond connector establishes a primary interconnect between a substrate and a high current terminal of an IC chip mounted on the substrate, and one or more secondary interconnects between the substrate and low current terminals of the IC chip. The bar bond connector includes a plate portion ... 02/09/06 - 20060027902 - Method and apparatus for stacked die packaging A method and apparatus for stacked die packaging provide a leadframe configured for supporting a lower semiconductor die. At least one pillar is formed on the leadframe for supporting an upper semiconductor die. The pillar is formed integrally with and of the same material as the leadframe, and is sized ... 02/09/06 - 20060027901 - Stacked chip package with exposed lead-frame bottom surface A stacked chip package with exposed lead-frame bottom surface is disclosed. The stacked chip package includes a first die encapsulated in an encapsulated molding compound, which is mounted on an active surface of a second die. A bottom surface of the second die is mounted to a top surface of ... 02/02/06 - 20060022318 - Packaged biomedical electrode unit and method of inspecting quality thereof Each of a pair of electrodes has a conductive face adapted to be brought into contact with a living body. A connector has a pair of terminals. Each of a pair of lead wires has a first end connected to one of the electrodes and a second end connected to ... 02/02/06 - 20060022317 - Chip-under-tape package structure and manufacture thereof The invention discloses a chip-under-tape package structure including a flexible substrate, a chip, a plurality of connecting members, a plurality of stud bumps, and a potting adhesive. The flexible substrate includes a plurality of inner pads and a plurality of outer pads. The chip is attached to a lower surface ... 02/02/06 - 20060022316 - Semiconductor package with flip chip on leadless leadframe A semiconductor package with flip chip on leadless leadframe includes a leadless leadframe, a ring-shaped tape, a flip chip and an underfilling material. The leadframe has a plurality of inner leads. Connecting regions are defined on the upper surfaces of the inner leads. The ring-shaped tape is disposed on the ... 02/02/06 - 20060022315 - Semiconductor package with stacked chips and method for fabricating the same A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the ... 01/12/06 - 20060006508 - Semiconductor device in which semiconductor chip is mounted on lead frame A semiconductor device including a lead frame having a plurality of inner leads having end portions and a plurality of outer leads integrated with the inner leads, the inner leads having first surfaces and second surfaces which are opposite to the first surfaces, first plating provided at the end portions ... 01/05/06 - 20060001136 - Quad flat non-leaded package The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is ... 01/05/06 - 20060001135 - Electronic package and semiconductor device using the same A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in ... 01/05/06 - 20060001134 - Package structure A package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame. ... 12/29/05 - 20050285241 - Quad flat no-lead (qfn) grid array package, method of making and memory module and computer system including same A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality ... 12/29/05 - 20050285240 - Semiconductor device and method of manufacturing the same A semiconductor device and manufacturing the semiconductor device are described. There is provided a method of manufacturing a semiconductor device including, disposing a lead frame inside an outer lead so as to couple between a coupling portion and a coupling acceptance portion, the lead frame including a chip mounting portion ... 12/29/05 - 20050285239 - Ultra thin dual chip image sensor package structure and method for fabrication A thin stacked image sensor package containing an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation ... 12/22/05 - 20050280126 - Flip chip in leaded molded package and method of manufacture thereof A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and ... 12/22/05 - 20050280125 - Co-packaged control circuit, transistor and inverted diode A copackaged electronic device comprises a diode device having an anode coupled to a drain electrode of a switching device and a cathode capable of being coupled to an external circuit. The switching device may be controlled by an integrated circuit mounted on a source electrode of the switching device ... 12/01/05 - 20050263864 - Partially patterned lead frames and methods of making and using the same in semiconductor packaging A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is ... 12/01/05 - 20050263863 - Semiconductor device and a method of manufacturing the same Miniaturization in a semiconductor device which has a chip part is attained. A QFP having the chip part includes a semiconductor chip, a plurality of inner leads arranged around the semiconductor chip, a sheet member which connects with the end part of the inner lead via insulating adhesive and which ... 11/24/05 - 20050258524 - Semiconductor device and method of manufacturing the same A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with ... 11/17/05 - 20050253227 - Resin-molded package with cavity structure A package includes: a substrate having a ridged peripheral portion and a center portion defined by and lower in level than the ridged peripheral portion. A semiconductor chip is mounted on the center portion. A plurality of lead is electrically coupled to the semiconductor chip and penetrates the substrate outwardly ... 11/10/05 - 20050248007 - Surface mount multichip devices A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, ... 11/03/05 - 20050242417 - Semiconductor chip package and method for manufacturing the same A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over ... 10/27/05 - 20050236702 - Semiconductor package for a large die A semiconductor package is provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality ... 10/27/05 - 20050236701 - Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. ... 10/27/05 - 20050236700 - Method of fabricating chips, and an associated support A method of fabricating a plurality of chips, with each chip including at least one circuit. This method includes the successive steps of creating chips on a layer of semiconductor material that is integral with a substrate; forming a weakening pattern corresponding to a predetermined cutting pattern on a support; ... 10/13/05 - 20050224934 - Circuit device In the case of mounting a passive element in a circuit device, since an electrode part is tin-plated, the passive element is fixed to a mounting land part by use of a solder material, and wires cannot intersect with each other in a single layer. Accordingly, there are problems such ... 10/13/05 - 20050224933 - Thermally enhanced component interposer: finger and net structures An IC package dissipates thermal energy using thermally and electrically conductive thermal fingers. The IC package includes a substrate material with a die pad area, which is suitable to support an integrated circuit. A plurality of solder ball pads is disposed on a first surface of the substrate material and ... 10/06/05 - 20050218487 - Method for manufacturing wiring substrate and method for manufacturing electronic device A method to deposit a metal layer only in a required portion, and to form wirings with a simple manufacture process. The method for manufacturing a wiring substrate includes the steps of: (a) forming a ground layer precursor having reactive groups including nitrogen atoms in first and second areas of ... 10/06/05 - 20050218486 - Semiconductor bga package having a segmented voltage plane and method of making A semiconductor device assembly and method of making the devices are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of ... 09/29/05 - 20050212104 - Semiconductor device By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which ... 09/22/05 - 20050205973 - Board-on-chip packages The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at ... 09/01/05 - 20050189629 - Method of manufacturing a semiconductor device A method for manufacturing a semiconductor device includes the steps of providing a semiconductor device of a surface mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be smaller than the main surface of the semiconductor chip, ... 07/14/05 - 20050151232 - Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of ... 06/30/05 - 20050139971 - Continuous molding method and molding apparatus for surface fastener The invention provides a molding method and molding apparatus, effective and cheap, for a surface fastener to be directly/indirectly bonded with/fit to an mounting object, capable of increasing the bonding strength or friction force regardless of the configuration of a bonding surface, wherein molten resin is discharged continuously from a ... 06/30/05 - 20050139970 - Leadless semiconductor package A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The lead frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a cavity serving as a chip disposal area ... 06/23/05 - 20050133893 - Lead frame structure with aperture or groove for flip chip in a leaded molded package A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes ... 06/23/05 - 20050133892 - Semiconductor device and method for the fabrication thereof Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one ... 06/16/05 - 20050127483 - Thin, thermally enhanced flip chip in a leaded molded package Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead ... 06/09/05 - 20050121756 - Dual gauge leadframe A leadframe (20) for a semiconductor device includes a first leadframe portion (12) having a perimeter that defines a cavity (16) and a plurality of leads (14) extending inwardly from the perimeter and a first thickness. A second leadframe portion (18) is attached to the first leadframe portion (16). The ... 06/02/05 - 20050116322 - Circuit module A circuit module of the present invention has leads serving as terminals for performing electrical input from, and output to exterior, a circuit device in which a first circuit element electrically connected to at least one of the leads is sealed with first sealing resin, a second circuit element fixed ... ### FreshPatents.com Support - Terms & Conditions |