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With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)

With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Lead Frame > With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)



Leadframe with lead of varying thickness
12/18/14 - 20140367838 - A leadframe that includes a die attachment pad and a lead having a bondwire attach portion with a thickness less than 50% of the thickness of an adjacent portion of the lead. Also a method of forming a leadframe includes forming a lead having a bond wire attach portion with...

A semiconductor package of a flipped mosfet
12/11/14 - 20140361418 - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the...

Power control device and preparation method thereof
12/11/14 - 20140361419 - A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to...

Hybrid packaging multi-chip semiconductor device and preparation method thereof
12/11/14 - 20140361420 - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on...

Lead frame based semiconductor die package
12/11/14 - 20140361421 - A lead frame based semiconductor die package includes a lead frame having a die pad that supports a semiconductor die and lead fingers that surround the die and die pad. The die is electrically connected to the lead fingers with bond wires. The die and bond wires are covered with...

Semiconductor device
12/11/14 - 20140361422 - In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing...

Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
12/11/14 - 20140361423 - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the...

Packaged semiconductor device
12/04/14 - 20140353808 - Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first bottom surface, the first electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the...

Semiconductor device and manufacturing method of semiconductor device
12/04/14 - 20140353809 - A technique capable of enhancing a reliability of a semiconductor device is provided. A semiconductor device has a die pad on which a semiconductor chip is mounted. The die pad is sealed with resin so that a lower surface located on an opposite side of an upper surface on which...

Multilevel leadframe
11/27/14 - 20140346656 - A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad...

Method of manufacturing semiconductor device and semiconductor device
11/13/14 - 20140332942 - Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically...

Barrel-plating quad flat no-lead (qfn) packaging structures and method for manufacturing the same
11/13/14 - 20140332943 - A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming...

Resin-encapsulated semiconductor device and its manufacturing method
11/13/14 - 20140332944 - A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30)...

Packaged ic having printed dielectric adhesive on die pad
11/06/14 - 20140327123 - A packaged integrated circuit (IC) includes a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto attached by a dielectric polymer material to the die pad. Bond wires are between...

Power transistor with heat dissipation and method therefore
11/06/14 - 20140327124 - A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact...

Quad flat no-lead (qfn) packaging structure and method for manufacturing the same
10/30/14 - 20140319664 - A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O...

Power semiconductor package
10/30/14 - 20140319665 - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using...

Lead frame and semiconductor package manufactured by using the same
10/30/14 - 20140319666 - The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one...

Chip and chip arrangement
10/16/14 - 20140306331 - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least...

Integrating multi-output power converters having vertically stacked semiconductor chips
10/16/14 - 20140306332 - A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first...

Cavity package with die attach pad
10/16/14 - 20140306333 - A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the...

Leadframe, semiconductor package including a leadframe and method for producing a leadframe
10/02/14 - 20140291824 - A lead frame includes a die pad and a lead finger with an inner portion which is configured to be electrically connected to contact pads of a die and with an outer portion which has an attach portion. The attach portion is configured to be soldered to an external solder...

Semiconductor device and semiconductor module
10/02/14 - 20140291825 - A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface of the die pad, wherein the lead frame excluding a bottom surface thereof and the semiconductor chip are sealed by a...

Semiconductor device manufacturing method and semiconductor device
10/02/14 - 20140291826 - A semiconductor device and a manufacturing method for a semiconductor device in which during QFP (quad flat package assembly) a wire passing over a bus bar and coupled to an inner lead is set at a loop height different from a second wire at a low loop height, and a...

Lead frame and semiconductor device
10/02/14 - 20140291827 - A lead frame includes an outer lead and a plating layer that covers a lower surface and side surfaces of the outer lead. The plating layer does not cover the upper surface of the outer lead. A frame base material is exposed from the plating layer at the upper surface...

Semiconductor device and method of manufacturing the same
10/02/14 - 20140291828 - A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the...

Semiconductor device having reinforced wire bonds to metal terminals
09/25/14 - 20140284779 - A method of assembling semiconductor devices includes connecting a bond wire between a bond pad on a top side surface of a semiconductor die having its bottom side surface attached to a package substrate and a bonded area within a metal terminal of the package substrate, where a bond is...

Method of manufacturing semiconductor device, and semiconductor device
09/25/14 - 20140284780 - Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of...

Semiconductor module and manufacturing method thereof
09/25/14 - 20140284781 - A first electrode of a first switching element is connected to a first electrode of a second switching element via a first lead frame. A second electrode of the first switching element is connected to an element of a snubber circuit via a second lead frame. A second electrode of...

Semiconductor device and method for manufacturing the same
09/25/14 - 20140284782 - A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106...

Semiconductor device with thick bottom metal and preparation method thereof
09/18/14 - 20140264802 - A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps...

Package device including an opening in a flexible substrate and methods of forming the same
09/18/14 - 20140264803 - Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or...

Stack die package
09/18/14 - 20140264804 - In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite...

Semiconductor package and fabrication method thereof
09/18/14 - 20140264805 - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with...

Semiconductor devices and methods of making the same
09/18/14 - 20140264806 - In one embodiment, methods for making semiconductor devices are disclosed....

Semiconductor device
09/18/14 - 20140264807 - Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached...

Chip carrier structure, chip package and method of manufacturing the same
09/11/14 - 20140252577 - Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material....

Balanced stress assembly for semiconductor devices
09/11/14 - 20140252578 - An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The...

3d-packages and methods for forming the same
09/11/14 - 20140252579 - A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die...

Lead frame, semiconductor package including the lead frame, and method of manufacturing the lead frame
09/11/14 - 20140252580 - There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver,...

Lead frame and substrate semiconductor package
09/11/14 - 20140252581 - A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of...

Lead frame and semiconductor device
09/11/14 - 20140252582 - A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from...

Semiconductor chip package
09/04/14 - 20140246766 - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the...

Semiconductor device and method of assembling same
09/04/14 - 20140246767 - A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the...

Ic package with stainless steel leadframe
08/28/14 - 20140239471 - Various aspects of the disclosure are directed to integrated circuit (IC) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and IC die encapsulation, with the stainless steel conducting signals/data between respective surfaces for...

Dual-flag stacked die package
08/28/14 - 20140239472 - In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control...

Wire bonding assembly and method
08/28/14 - 20140239473 - A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material....

Semiconductor packages with low stand-off interconnections between chips
08/21/14 - 20140231977 - A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface...

Semiconductor package with inner and outer leads
08/21/14 - 20140231978 - A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically...

Electronic device and package structure thereof
08/14/14 - 20140225241 - A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side...

Semiconductor packages and methods of packaging semiconductor devices
08/14/14 - 20140225242 - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on...

Semiconductor device
08/14/14 - 20140225243 - A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and...

Double-sided package
08/07/14 - 20140217566 - Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the...

Semiconductor device and manufacturing method of the same
08/07/14 - 20140217567 - A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of...

Semiconductor package with cantilever leads
08/07/14 - 20140217568 - A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and...

Chip arrangement and chip package
07/31/14 - 20140210061 - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled...

Leadframe-based semiconductor package having terminals on top and bottom surfaces
07/31/14 - 20140210062 - A semiconductor device (100) with a leadframe having first (310) and second (311) leads with central and peripheral ends, the central ends in a first horizontal plane (150). The first leads have peripheral ends (310b) in a second horizontal plane spaced (160) from the first plane and the second leads...

Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device
07/31/14 - 20140210063 - A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant....

Wire bonding method and structure
07/31/14 - 20140210064 - An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the...

Semiconductor package
07/31/14 - 20140210065 - A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member....

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
07/17/14 - 20140197526 - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the...

Chip arrangement and a method for manufacturing a chip arrangement
07/17/14 - 20140197527 - A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about...

Integrated circuit package and method of making
07/10/14 - 20140191380 - An integrated circuit (“IC”) device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s)...

Integrated circuit module with dual leadframe
07/10/14 - 20140191381 - An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting...

Circuit substrate, method of manufacturing circuit substrate, and electronic component
07/10/14 - 20140191382 - A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective...

Power device and method of packaging same
07/10/14 - 20140191383 - A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a...

Pre-encapsulated etching-then-plating lead frame structure with island and method for manufacturing the same
07/10/14 - 20140191384 - A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film...

Die package structure
07/03/14 - 20140183713 - The die package structure includes a die, and the pads on one side of the active surface of the die. The connecting terminal is disposed on one side of the packaged substrate region and is passed through the packaged substrate region. The external connecting terminal is disposed on another side...

Die package structure
07/03/14 - 20140183714 - A die packaged structure is provided, which includes a die having the pad disposed on one side of the active surface. A packaged substrate having a front surface and a back surface, and the connecting terminal disposed on one side of the packaged substrate region, and passed through the packaged...

Semiconductor device
07/03/14 - 20140183715 - According to the present invention, a semiconductor device having superior electrical conductivity is provided. The semiconductor device of the present invention is provided with a base material, a semiconductor element, and an adhesive layer that adheres the base material and the semiconductor element while interposed there between. In the adhesive...

Lead frame having a perimeter recess within periphery of component terminal
06/26/14 - 20140175627 - Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component...

Copper wire bonding structure in semiconductor device and fabrication method thereof
06/26/14 - 20140175628 - A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode....

Apparatus and methods for reducing impact of high rf loss plating
06/26/14 - 20140175629 - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to...

Semiconductor package with multiple conductive clips
06/26/14 - 20140175630 - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of...