FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents


Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Lead Frame > With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)

With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)

With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/16/14 - 20140306331 - Chip and chip arrangement
Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least...

10/16/14 - 20140306332 - Integrating multi-output power converters having vertically stacked semiconductor chips
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first...

10/16/14 - 20140306333 - Cavity package with die attach pad
A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the...

10/02/14 - 20140291824 - Leadframe, semiconductor package including a leadframe and method for producing a leadframe
A lead frame includes a die pad and a lead finger with an inner portion which is configured to be electrically connected to contact pads of a die and with an outer portion which has an attach portion. The attach portion is configured to be soldered to an external solder...

10/02/14 - 20140291825 - Semiconductor device and semiconductor module
A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface of the die pad, wherein the lead frame excluding a bottom surface thereof and the semiconductor chip are sealed by a...

10/02/14 - 20140291826 - Semiconductor device manufacturing method and semiconductor device
A semiconductor device and a manufacturing method for a semiconductor device in which during QFP (quad flat package assembly) a wire passing over a bus bar and coupled to an inner lead is set at a loop height different from a second wire at a low loop height, and a...

10/02/14 - 20140291827 - Lead frame and semiconductor device
A lead frame includes an outer lead and a plating layer that covers a lower surface and side surfaces of the outer lead. The plating layer does not cover the upper surface of the outer lead. A frame base material is exposed from the plating layer at the upper surface...

10/02/14 - 20140291828 - Semiconductor device and method of manufacturing the same
A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the...

09/25/14 - 20140284779 - Semiconductor device having reinforced wire bonds to metal terminals
A method of assembling semiconductor devices includes connecting a bond wire between a bond pad on a top side surface of a semiconductor die having its bottom side surface attached to a package substrate and a bonded area within a metal terminal of the package substrate, where a bond is...

09/25/14 - 20140284780 - Method of manufacturing semiconductor device, and semiconductor device
Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of...

09/25/14 - 20140284781 - Semiconductor module and manufacturing method thereof
A first electrode of a first switching element is connected to a first electrode of a second switching element via a first lead frame. A second electrode of the first switching element is connected to an element of a snubber circuit via a second lead frame. A second electrode of...

09/25/14 - 20140284782 - Semiconductor device and method for manufacturing the same
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106...

09/18/14 - 20140264802 - Semiconductor device with thick bottom metal and preparation method thereof
A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps...

09/18/14 - 20140264803 - Package device including an opening in a flexible substrate and methods of forming the same
Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or...

09/18/14 - 20140264804 - Stack die package
In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite...

09/18/14 - 20140264805 - Semiconductor package and fabrication method thereof
A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with...

09/18/14 - 20140264806 - Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed....

09/18/14 - 20140264807 - Semiconductor device
Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached...

09/11/14 - 20140252577 - Chip carrier structure, chip package and method of manufacturing the same
Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material....

09/11/14 - 20140252578 - Balanced stress assembly for semiconductor devices
An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The...

09/11/14 - 20140252579 - 3d-packages and methods for forming the same
A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die...

09/11/14 - 20140252580 - Lead frame, semiconductor package including the lead frame, and method of manufacturing the lead frame
There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver,...

09/11/14 - 20140252581 - Lead frame and substrate semiconductor package
A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of...

09/11/14 - 20140252582 - Lead frame and semiconductor device
A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from...

09/04/14 - 20140246766 - Semiconductor chip package
The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the...

09/04/14 - 20140246767 - Semiconductor device and method of assembling same
A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the...

08/28/14 - 20140239471 - Ic package with stainless steel leadframe
Various aspects of the disclosure are directed to integrated circuit (IC) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and IC die encapsulation, with the stainless steel conducting signals/data between respective surfaces for...

08/28/14 - 20140239472 - Dual-flag stacked die package
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control...

08/28/14 - 20140239473 - Wire bonding assembly and method
A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material....

08/21/14 - 20140231977 - Semiconductor packages with low stand-off interconnections between chips
A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface...

08/21/14 - 20140231978 - Semiconductor package with inner and outer leads
A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically...

08/14/14 - 20140225241 - Electronic device and package structure thereof
A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side...

08/14/14 - 20140225242 - Semiconductor packages and methods of packaging semiconductor devices
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on...

08/14/14 - 20140225243 - Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and...

08/07/14 - 20140217566 - Double-sided package
Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the...

08/07/14 - 20140217567 - Semiconductor device and manufacturing method of the same
A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of...

08/07/14 - 20140217568 - Semiconductor package with cantilever leads
A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and...

07/31/14 - 20140210061 - Chip arrangement and chip package
Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled...

07/31/14 - 20140210062 - Leadframe-based semiconductor package having terminals on top and bottom surfaces
A semiconductor device (100) with a leadframe having first (310) and second (311) leads with central and peripheral ends, the central ends in a first horizontal plane (150). The first leads have peripheral ends (310b) in a second horizontal plane spaced (160) from the first plane and the second leads...

07/31/14 - 20140210063 - Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device
A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant....

07/31/14 - 20140210064 - Wire bonding method and structure
An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the...

07/31/14 - 20140210065 - Semiconductor package
A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member....

07/17/14 - 20140197526 - Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the...

07/17/14 - 20140197527 - Chip arrangement and a method for manufacturing a chip arrangement
A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about...

07/10/14 - 20140191380 - Integrated circuit package and method of making
An integrated circuit (“IC”) device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s)...

07/10/14 - 20140191381 - Integrated circuit module with dual leadframe
An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting...

07/10/14 - 20140191382 - Circuit substrate, method of manufacturing circuit substrate, and electronic component
A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective...

07/10/14 - 20140191383 - Power device and method of packaging same
A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a...

07/10/14 - 20140191384 - Pre-encapsulated etching-then-plating lead frame structure with island and method for manufacturing the same
A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film...

07/03/14 - 20140183713 - Die package structure
The die package structure includes a die, and the pads on one side of the active surface of the die. The connecting terminal is disposed on one side of the packaged substrate region and is passed through the packaged substrate region. The external connecting terminal is disposed on another side...

07/03/14 - 20140183714 - Die package structure
A die packaged structure is provided, which includes a die having the pad disposed on one side of the active surface. A packaged substrate having a front surface and a back surface, and the connecting terminal disposed on one side of the packaged substrate region, and passed through the packaged...

07/03/14 - 20140183715 - Semiconductor device
According to the present invention, a semiconductor device having superior electrical conductivity is provided. The semiconductor device of the present invention is provided with a base material, a semiconductor element, and an adhesive layer that adheres the base material and the semiconductor element while interposed there between. In the adhesive...