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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Lead Frame > With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)

With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led)

With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

08/21/14 - 20140231977 - Semiconductor packages with low stand-off interconnections between chips
A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface...

08/21/14 - 20140231978 - Semiconductor package with inner and outer leads
A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically...

08/14/14 - 20140225241 - Electronic device and package structure thereof
A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side...

08/14/14 - 20140225242 - Semiconductor packages and methods of packaging semiconductor devices
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on...

08/14/14 - 20140225243 - Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and...

08/07/14 - 20140217566 - Double-sided package
Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the...

08/07/14 - 20140217567 - Semiconductor device and manufacturing method of the same
A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of...

08/07/14 - 20140217568 - Semiconductor package with cantilever leads
A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and...

07/31/14 - 20140210061 - Chip arrangement and chip package
Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled...

07/31/14 - 20140210062 - Leadframe-based semiconductor package having terminals on top and bottom surfaces
A semiconductor device (100) with a leadframe having first (310) and second (311) leads with central and peripheral ends, the central ends in a first horizontal plane (150). The first leads have peripheral ends (310b) in a second horizontal plane spaced (160) from the first plane and the second leads...

07/31/14 - 20140210063 - Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device
A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant....

07/31/14 - 20140210064 - Wire bonding method and structure
An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the...

07/31/14 - 20140210065 - Semiconductor package
A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member....

07/17/14 - 20140197526 - Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the...

07/17/14 - 20140197527 - Chip arrangement and a method for manufacturing a chip arrangement
A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about...

07/10/14 - 20140191380 - Integrated circuit package and method of making
An integrated circuit (“IC”) device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s)...

07/10/14 - 20140191381 - Integrated circuit module with dual leadframe
An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting...

07/10/14 - 20140191382 - Circuit substrate, method of manufacturing circuit substrate, and electronic component
A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective...

07/10/14 - 20140191383 - Power device and method of packaging same
A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a...

07/10/14 - 20140191384 - Pre-encapsulated etching-then-plating lead frame structure with island and method for manufacturing the same
A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film...

07/03/14 - 20140183713 - Die package structure
The die package structure includes a die, and the pads on one side of the active surface of the die. The connecting terminal is disposed on one side of the packaged substrate region and is passed through the packaged substrate region. The external connecting terminal is disposed on another side...

07/03/14 - 20140183714 - Die package structure
A die packaged structure is provided, which includes a die having the pad disposed on one side of the active surface. A packaged substrate having a front surface and a back surface, and the connecting terminal disposed on one side of the packaged substrate region, and passed through the packaged...

07/03/14 - 20140183715 - Semiconductor device
According to the present invention, a semiconductor device having superior electrical conductivity is provided. The semiconductor device of the present invention is provided with a base material, a semiconductor element, and an adhesive layer that adheres the base material and the semiconductor element while interposed there between. In the adhesive...

06/26/14 - 20140175627 - Lead frame having a perimeter recess within periphery of component terminal
Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component...

06/26/14 - 20140175628 - Copper wire bonding structure in semiconductor device and fabrication method thereof
A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode....

06/26/14 - 20140175629 - Apparatus and methods for reducing impact of high rf loss plating
To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to...

06/26/14 - 20140175630 - Semiconductor package with multiple conductive clips
One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of...

06/19/14 - 20140167236 - Integrated circuit packaging system with transferable trace lead frame
System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently...

06/19/14 - 20140167237 - Power module package
Disclosed herein is a power module package, including: a substrate; semiconductor chips mounted on one surface of the substrate; external connection terminals connected to one surface of the substrate; and a connecting member having one end contacting the semiconductor chips and the other end contacting the external connection terminals and...

06/19/14 - 20140167238 - Semiconductor die package and method for making the same
Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die....

06/19/14 - 20140167239 - Power module package
Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second...

06/19/14 - 20140167240 - Semiconductor device carrier and semiconductor package using the same
The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface....

06/12/14 - 20140159217 - Multichip package and fabrication method thereof
A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the...

06/12/14 - 20140159218 - Chip packaging structure of a plurality of assemblies
Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is...

06/12/14 - 20140159219 - Multi-component chip packaging structure
Disclosed herein are various chip packaging structures and arrangements. In one embodiment, a multiple-component chip packaging structure can include: (i) a first component arranged on a bottom layer; (ii) at least one second component arranged on the first component, where the at least one the second component is electrically connected...

06/12/14 - 20140159220 - Semiconductor device and method of manufacture thereof
A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled...

06/12/14 - 20140159221 - Lead frame, method for manufacturing lead frame and semiconductor device using same
Provided is a lead frame by which a die pad can be easily exposed when the lead frame is used for a semiconductor device. The lead frame has a die pad with an upper surface on which a semiconductor element is mounted. The lead frame is used for the semiconductor...

06/05/14 - 20140151865 - Semiconductor device packages providing enhanced exposed toe fillets
A mechanism is provided by optically inspectable surface mount bonding of no-leads packages is enhanced. Embodiments of the present invention use a lead frame within the no-leads package that provides a plated surface not only along the bottom of the package but also in a direction substantially parallel to the...

06/05/14 - 20140151866 - Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress
An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein...

06/05/14 - 20140151867 - Semiconductor package and method for fabricating base for semiconductor package
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure....

05/29/14 - 20140145319 - Semicondutor packages and methods of fabrication thereof
In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric...

05/29/14 - 20140145320 - Die package
An electronic device package including an electronic device within a block of insulating material, for example a QFN package. The paddle may be design to extend beyond the die to allow wirebonding between a region of the paddle and the die. Leads may be extended underneath the die and adhered...

05/22/14 - 20140138810 - Semiconductor device
A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip...

05/15/14 - 20140131848 - Land structure for semiconductor package and method therefor
In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the...

05/15/14 - 20140131849 - Stacked chip-on-board module with edge connector
A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the...

05/08/14 - 20140124912 - Semiconductor device and method of manufacturing the same
Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die...

05/01/14 - 20140117523 - Stacked dual-chip packaging structure and preparation method thereof
The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip...

05/01/14 - 20140117524 - Power semiconductor module and manufacturing method thereof
There are provided a power semiconductor module and a manufacturing method thereof, the power semiconductor module including: a lead frame; a base substrate including a circuit wiring formed on an insulating layer thereof; a plurality of power semiconductor devices disposed to contact the circuit wiring; and a multilayer substrate formed...

05/01/14 - 20140117525 - Power module package and method of manufacturing the same
Disclosed herein is a power module package including: a base substrate; a metal layer including a circuit pattern and a connection pad formed on the base substrate; a semiconductor device including a plurality of electrodes mounted on the circuit pattern of the metal layer; and a plurality of lead frames...

04/24/14 - 20140110829 - Module comprising a semiconductor chip
A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the...

04/17/14 - 20140103507 - Optical device package and system
Optical device packages and systems are disclosed. In one embodiment, a system may comprise first and second optical device packages. A respective first and second optical path length may be associated with the first and second optical device packages. The first and second optical path lengths may be adjusted differently....

04/17/14 - 20140103508 - Encapsulating package for an integrated circuit
An apparatus is provided. An integrated circuit or IC is secured to a package housing. The IC has an IC substrate and an epitaxial layer formed over the substrate and having an active region and an upper surface. The upper surface is substantially exposed, and bond pads are formed over...

04/17/14 - 20140103509 - Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening...

04/17/14 - 20140103510 - Semiconductor device and method of manufacturing the same
A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a...

04/17/14 - 20140103511 - Semiconductor device, semiconductor device storage method, semiconductor device manufacturing method, and semiconductor manufacturing apparatus
A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface...

04/17/14 - 20140103512 - Dual-leadframe multi-chip package
A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET....

04/17/14 - 20140103513 - Semiconductor device with lead terminals having portions thereof extending obliquely
A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting...

04/17/14 - 20140103514 - Power quad flat no-lead (pqfn) package having bootstrap diodes on a common integrated circuit (ic)
According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase inverter situated on a leadframe. The PQFN package further includes drivers situated on the leadframe and configured to drive the multi-phase inverter. The PQFN package also includes bootstrap diodes respectively coupled to the drivers. The...

04/17/14 - 20140103515 - Semiconductor device
In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic...