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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Lead Frame

Lead Frame

Lead Frame patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/23/14 - 20140312474 - Semiconductor package with wire bonding
A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire...

10/23/14 - 20140312475 - Die reuse in electrical circuits
A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each...

10/23/14 - 20140312476 - No-exposed-pad ball grid array (bga) packaging structures and method for manufacturing the same
A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality...

10/23/14 - 20140312477 - Lead and lead frame for power package
A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both...

10/16/14 - 20140306327 - Semiconductor device and method of manufacturing thereof
A semiconductor device includes a device carrier and a semiconductor chip attached to the device carrier. Further, the semiconductor device includes a lid having a recess. The lid includes a semiconductor material and is attached to the device carrier such that the semiconductor chip is accommodated in the recess....

10/16/14 - 20140306328 - Semiconductor device
The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The...

10/09/14 - 20140299977 - Semiconductor device
A semiconductor device includes: a lead frame; an IC element mounted on a main face of the lead frame; an inductor mounted on a back face of the lead frame; and a resin body configured to seal the lead frame, the IC element and the inductor, wherein the inductor and...

10/02/14 - 20140291822 - Integrated circuit package
An integrated circuit (“IC”) package including an IC assembly mounted on a leadframe and an encapsulant block covering the IC assembly and portions of the leadframe. The encapsulant block has a molded chamfered outer surface portion and the leadframe has a saw cut outer periphery....

09/25/14 - 20140284777 - Multi-chip semiconductor power device
A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic...

09/25/14 - 20140284778 - Methods and systems for selectively forming metal layers on lead frames after die attachment
Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed...

09/18/14 - 20140264789 - Semiconductor packages and methods of packaging semiconductor devices
Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the...

09/18/14 - 20140264790 - Chip package and method for manufacturing the same
Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one...

09/18/14 - 20140264791 - Direct external interconnect for embedded interconnect bridge package
An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the...

09/18/14 - 20140264792 - Semiconductor packages and methods of packaging semiconductor devices
Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within...

09/11/14 - 20140252571 - Wafer-level package mitigated undercut
A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the...

09/11/14 - 20140252572 - Structure and method for 3d ic package
Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive...

09/11/14 - 20140252573 - Semiconductor device and method of forming embedded conductive layer for power/ground planes in fo-ewlb
A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is...

09/11/14 - 20140252574 - Lead frame and semiconductor device
A lead frame of high quality which can endure direct bonding to the electrodes of a semiconductor element and a metal member, and a semiconductor device of high reliability which utilizing the lead frame. The lead frame includes a pair of lead frame portions which are arranged spaced apart from...

08/28/14 - 20140239466 - Electronic device
An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first...

08/28/14 - 20140239467 - Semiconductor device
A semiconductor device includes a lead frame, a semiconductor chip soldered to the lead frame, and a metal bar. The metal bar is arranged inside a solder layer so as to extend along one side of the semiconductor chip. When viewed in a stacking direction of the lead frame and...

08/28/14 - 20140239468 - Semiconductor device
An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and...

08/21/14 - 20140231975 - Semiconductor device
A semiconductor device includes an insulating circuit substrate mounted with at least one semiconductor element; a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing a periphery of the bottom surface portion; a lead molded integrally with the resin case...

08/14/14 - 20140225238 - Semiconductor device
A semiconductor device includes a metal substrate, semiconductor elements, wires, a control terminal, a main electrode terminal, a control substrate, a cover, a sealing resin, a case, and an insulator. The metal substrate includes a metal plate, an insulating layer formed on the top surface of the metal plate, and...

08/14/14 - 20140225239 - Resin-encapsulated semiconductor device and method of manufacturing the same
A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those...

08/07/14 - 20140217565 - Electrical connectivity of die to a host substrate
According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of...

07/31/14 - 20140210060 - Semiconductor device
Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing...

07/24/14 - 20140203418 - Lead frame and a method of manufacturing thereof
A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to...

07/24/14 - 20140203419 - Half-bridge package with a conductive clip
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes...

07/17/14 - 20140197523 - Chip arrangement and a method for forming a chip arrangement
A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed...

07/17/14 - 20140197524 - Die package structure
A die packaged structure includes a pad on the central region of the die. A packaged substrate with an opening disposed in the central region, and a connecting terminal is passed through the packaged substrate and disposed around the opening. An external connecting terminal is disposed on the four sides...

07/17/14 - 20140197525 - Power module
A power module configured to arrange a first electrode on a surface of which a first switching device is bonded, a second electrode on a surface of which a second switching device is bonded, and a third electrode by stacking the first electrode, the first switching device, the second electrode,...

07/03/14 - 20140183711 - Semiconductor device and method of making a semiconductor device
In accordance with an embodiment of the present invention, a semiconductor device has a substrate having a first surface and a second surface opposite the first surface. Also, the substrate has a first hole. A plurality of leads is disposed over the first surface of the substrate and a die...

06/26/14 - 20140175624 - Method for manufacturing a chip arrangement, and chip arrangement
A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the...

06/26/14 - 20140175625 - Semiconductor device including at least one element
A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive....

06/26/14 - 20140175626 - Integrated circuit package and method of manufacture
An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe. A shunt is located within the open space such that it is not in contact with any portion of the leadframe....

06/19/14 - 20140167233 - Semiconductor light-emitting device
A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a...

06/12/14 - 20140159212 - Stacked type power device module
The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated....

06/05/14 - 20140151862 - Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package
A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one...

05/22/14 - 20140138805 - System for no-lead integrated circuit packages without tape frame
A system has a leadframe strip and a plurality of integrated circuit dies are each encapsulated in an encapsulant. The encapsulant has a plurality of first cuts and a plurality of second cuts therein. A fixture holds the package in said plurality of first cuts while said plurality of second...

05/22/14 - 20140138806 - Power overlay structure with leadframe connections
A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection...

05/22/14 - 20140138807 - Power overlay structure with leadframe connections
A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection...

05/15/14 - 20140131842 - Axial semiconductor package
An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially...

05/15/14 - 20140131843 - Magnetically coupled galvanically isolated communication using lead frame
An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within encapsulation. The lead frame includes a first conductor having a first conductive loop disposed substantially within the encapsulation. The lead frame also includes a second conductor that is galvanically isolated...

05/15/14 - 20140131844 - System and method for an electronic package with a fail-open mechanism
A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a...

05/15/14 - 20140131845 - Semiconductor device
A semiconductor device includes a semiconductor element, a capacitor, a first resin, lead frames and a second resin. The first resin forms a resin molding which covers the semiconductor element and the capacitor. The lead frames are attached to two surfaces of the resin molding and are connected to the...

05/08/14 - 20140124909 - Semiconductor device
According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat...

05/01/14 - 20140117516 - Multiple die in a face down package
A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements...

05/01/14 - 20140117517 - Power quad flat no-lead (pqfn) package having control and driver circuits
According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control...

05/01/14 - 20140117518 - Control and driver circuits on a power quad flat no-lead (pqfn) leadframe
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe and respectively connected to a U-phase output strip and a W-phase output pad of the PQFN leadframe. The PQFN leadframe further includes a common integrated circuit (IC)...

04/17/14 - 20140103501 - Circuit board with twinned cu circuit layer and method for manufacturing the same
A circuit board with twinned Cu circuit layer and a method for manufacturing the same are disclosed, wherein the method comprises the following steps: (A) providing a substrate with a first circuit layer formed thereon, wherein the first circuit layer comprises a conductive pad; (B) forming a first dielectric layer...

04/17/14 - 20140103502 - Semiconductor device
A semiconductor device includes: a first semiconductor chip held on a substrate and including an expanded portion expanding outward from a side surface of a body of the first semiconductor chip; a first wire connecting the expanded portion of the first semiconductor chip to the substrate; and a second wire...