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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > With Means To Control Surface Effects > Insulating Coating > Multiple Layers

Multiple Layers

Multiple Layers patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264781 - Passivation layer for harsh environments and methods of fabrication thereof
A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al2O3) and a first layer...

09/11/14 - 20140252565 - Nucleation interface for high-k layer on germanium
A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition...

09/11/14 - 20140252566 - Silicon-on-dual plastic (sodp) technology and methods of manufacturing the same
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack...

09/11/14 - 20140252567 - Patterned silicon-on-plastic (sop) technology and methods of manufacturing the same
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive...

05/29/14 - 20140145313 - Method of making a semiconductor device using a bottom antireflective coating (barc) layer
This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the...

03/06/14 - 20140061869 - Electronic element including dielectric stack
An electronic element includes a substrate; a patterned first electrically conductive layer on the substrate; a patterned second electrically conductive layer on the substrate; and a dielectric stack on the substrate. A portion of the first electrically conductive layer and a portion of the second electrically conductive layer overlap each...

03/06/14 - 20140061870 - Semiconductor device and fabrication method
Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor...

03/06/14 - 20140061871 - Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second...

03/06/14 - 20140061872 - Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of...

02/27/14 - 20140054754 - Optically reactive masking
Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized....

02/27/14 - 20140054755 - Methods of forming semiconductor device structures, and related semiconductor device structures
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to...

02/27/14 - 20140054756 - Anti spacer process and semiconductor structure generated by the anti spacer process
An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa)...

02/20/14 - 20140048912 - Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an...

01/23/14 - 20140021589 - Semiconductor photocatalyst coated with graphitic carbon film and method of fabricating the same
A semiconductor of which a substance such as a semiconductor photocatalyst is uniformly coated on the surface thereof with a graphitic carbon film and a method of fabricating the same are disclosed. According to the inventive method, a graphitic carbon film having a thickness of 1 nm or less is...

01/02/14 - 20140001606 - Semiconductor devices and methods of forming the same
Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer....

12/05/13 - 20130320508 - Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first...

11/21/13 - 20130307126 - Semiconductor structure and process thereof
A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is...

11/07/13 - 20130292807 - Semiconductor device dielectric interface layer
Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a...

09/12/13 - 20130234301 - Patterned structure of semiconductor device and fabricating method thereof
A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on...

09/12/13 - 20130234302 - Semiconductor structure and fabrication method
A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist...

06/27/13 - 20130161798 - Graded density layer for formation of interconnect structures
Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface...

06/13/13 - 20130147021 - Multi-layer substrate structure and manufacturing method for the same
A method for manufacturing a multi-layer substrate structure such as a CSOI wafer structure (cavity-SOI, silicon-on-insulator) comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (302, 404),...

05/30/13 - 20130134563 - Electrical connection structure
A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less...

05/23/13 - 20130127023 - Method for producing a graphene sheet on a platinum silicide, structures obtained using said method and uses thereof
Applications: manufacture of micro- and nanoelectronic devices, micro- and nanoelectromechanical devices, etc....

02/14/13 - 20130037921 - Resist underlayer composition and process of producing integrated circuit devices using same
A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3....

01/31/13 - 20130026610 - Lithography method and device
Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with...

12/06/12 - 20120306058 - Method for blister-free passivation of a silicon surface
A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al2O3 layer on the surface, the Al2O3 layer having a thickness not exceeding about 15 nm; performing an outgassing process at a temperature in...

11/22/12 - 20120292748 - Methods and structures for forming integrated semiconductor structures
The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over...

11/08/12 - 20120280372 - Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of...

10/25/12 - 20120267766 - Resist underlayer composition and process of producing integrated circuit devices using the same
A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,...

08/30/12 - 20120217623 - Inter-level dielectric layer, semiconductor device having said inter-level dielectric layer and method for manufacturing the same
The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with...

07/05/12 - 20120168915 - Reliable interconnect integration scheme
Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values....

06/28/12 - 20120161296 - Multiple patterning using improved patternable low-k dielectric materials
A double patterned semiconductor structure is provided. The structure includes a first patterned and cured low-k structure located on a first portion of an antireflective coating, and a second patterned and cured low-k structure located on a second portion of the antireflective coating, wherein the second patterned and cured low-k...

06/14/12 - 20120146195 - Overlay vernier mask pattern, formation method thereof, semiconductor device including overlay vernier pattern, and formation method thereof
An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and...

05/03/12 - 20120104567 - Iiioxny on reo/si
An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A...

04/26/12 - 20120098107 - Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD)....

04/05/12 - 20120080779 - Ultra high selectivity doped amorphous carbon strippable hardmask development and integration
Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate...

03/29/12 - 20120074536 - Methods of manufacturing semiconductor devices and structures thereof
Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The...

03/15/12 - 20120061807 - Pitch multiplied mask patterns for isolated features
Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second...

02/09/12 - 20120032311 - Multi component dielectric layer
An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant...

12/15/11 - 20110304030 - Semiconductor device and manufacturing method thereof
A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality...

11/24/11 - 20110284996 - Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect...

08/25/11 - 20110204492 - Microelectronic structure including a low k dielectric and a method of controlling carbon distribution in the structure
Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low...

08/04/11 - 20110186970 - Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating...

08/04/11 - 20110186971 - Method of making dense, conformal, ultra-thin cap layers for nanoporous low-k ild by plasma assisted atomic layer deposition
Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous...

06/09/11 - 20110133313 - Hardmask materials
Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped...

05/26/11 - 20110121436 - Method for forming dual high-k metal gate using photoresist mask and structures thereof
Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to...

03/17/11 - 20110062560 - Bpsg film deposition with undoped capping
Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is...

02/24/11 - 20110042790 - Multiple patterning using improved patternable low-k dielectric materials
A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method...

12/16/10 - 20100314725 - Stress balance layer on semiconductor wafer backside
A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates...

09/30/10 - 20100244206 - Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial...