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Multiple Layers

Multiple Layers patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


With Means To Control Surface Effects > Insulating Coating > Multiple Layers



Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
11/27/14 - 20140346650 - The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD)....

Passivation layer for harsh environments and methods of fabrication thereof
09/18/14 - 20140264781 - A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al2O3) and a first layer...

Nucleation interface for high-k layer on germanium
09/11/14 - 20140252565 - A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition...

Silicon-on-dual plastic (sodp) technology and methods of manufacturing the same
09/11/14 - 20140252566 - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack...

Patterned silicon-on-plastic (sop) technology and methods of manufacturing the same
09/11/14 - 20140252567 - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive...

Method of making a semiconductor device using a bottom antireflective coating (barc) layer
05/29/14 - 20140145313 - This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the...

Electronic element including dielectric stack
03/06/14 - 20140061869 - An electronic element includes a substrate; a patterned first electrically conductive layer on the substrate; a patterned second electrically conductive layer on the substrate; and a dielectric stack on the substrate. A portion of the first electrically conductive layer and a portion of the second electrically conductive layer overlap each...

Semiconductor device and fabrication method
03/06/14 - 20140061870 - Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor...

Semiconductor device and method of manufacturing the same
03/06/14 - 20140061871 - A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second...

Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
03/06/14 - 20140061872 - To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of...

Optically reactive masking
02/27/14 - 20140054754 - Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized....

Methods of forming semiconductor device structures, and related semiconductor device structures
02/27/14 - 20140054755 - A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to...

Anti spacer process and semiconductor structure generated by the anti spacer process
02/27/14 - 20140054756 - An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa)...

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
02/20/14 - 20140048912 - The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an...

Semiconductor photocatalyst coated with graphitic carbon film and method of fabricating the same
01/23/14 - 20140021589 - A semiconductor of which a substance such as a semiconductor photocatalyst is uniformly coated on the surface thereof with a graphitic carbon film and a method of fabricating the same are disclosed. According to the inventive method, a graphitic carbon film having a thickness of 1 nm or less is...

Semiconductor devices and methods of forming the same
01/02/14 - 20140001606 - Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer....

Semiconductor device and method of manufacturing the same
12/05/13 - 20130320508 - A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first...

Semiconductor structure and process thereof
11/21/13 - 20130307126 - A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is...

Semiconductor device dielectric interface layer
11/07/13 - 20130292807 - Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a...

Patterned structure of semiconductor device and fabricating method thereof
09/12/13 - 20130234301 - A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on...

Semiconductor structure and fabrication method
09/12/13 - 20130234302 - A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist...

Graded density layer for formation of interconnect structures
06/27/13 - 20130161798 - Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface...

Multi-layer substrate structure and manufacturing method for the same
06/13/13 - 20130147021 - A method for manufacturing a multi-layer substrate structure such as a CSOI wafer structure (cavity-SOI, silicon-on-insulator) comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (302, 404),...

Electrical connection structure
05/30/13 - 20130134563 - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less...

Method for producing a graphene sheet on a platinum silicide, structures obtained using said method and uses thereof
05/23/13 - 20130127023 - Applications: manufacture of micro- and nanoelectronic devices, micro- and nanoelectromechanical devices, etc....

Resist underlayer composition and process of producing integrated circuit devices using same
02/14/13 - 20130037921 - A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3....

Lithography method and device
01/31/13 - 20130026610 - Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with...

Method for blister-free passivation of a silicon surface
12/06/12 - 20120306058 - A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al2O3 layer on the surface, the Al2O3 layer having a thickness not exceeding about 15 nm; performing an outgassing process at a temperature in...

Methods and structures for forming integrated semiconductor structures
11/22/12 - 20120292748 - The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over...

Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film
11/08/12 - 20120280372 - To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of...

Resist underlayer composition and process of producing integrated circuit devices using the same
10/25/12 - 20120267766 - A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,...

Inter-level dielectric layer, semiconductor device having said inter-level dielectric layer and method for manufacturing the same
08/30/12 - 20120217623 - The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with...

Reliable interconnect integration scheme
07/05/12 - 20120168915 - Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values....

Multiple patterning using improved patternable low-k dielectric materials
06/28/12 - 20120161296 - A double patterned semiconductor structure is provided. The structure includes a first patterned and cured low-k structure located on a first portion of an antireflective coating, and a second patterned and cured low-k structure located on a second portion of the antireflective coating, wherein the second patterned and cured low-k...

Overlay vernier mask pattern, formation method thereof, semiconductor device including overlay vernier pattern, and formation method thereof
06/14/12 - 20120146195 - An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and...

Iiioxny on reo/si
05/03/12 - 20120104567 - An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A...

Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
04/26/12 - 20120098107 - The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD)....

Ultra high selectivity doped amorphous carbon strippable hardmask development and integration
04/05/12 - 20120080779 - Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate...

Methods of manufacturing semiconductor devices and structures thereof
03/29/12 - 20120074536 - Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The...

Pitch multiplied mask patterns for isolated features
03/15/12 - 20120061807 - Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second...

Multi component dielectric layer
02/09/12 - 20120032311 - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant...

Semiconductor device and manufacturing method thereof
12/15/11 - 20110304030 - A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality...

Semiconductor device and method of manufacturing the same
11/24/11 - 20110284996 - In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect...

Microelectronic structure including a low k dielectric and a method of controlling carbon distribution in the structure
08/25/11 - 20110204492 - Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low...

Method for manufacturing a semiconductor device
08/04/11 - 20110186970 - A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating...

Method of making dense, conformal, ultra-thin cap layers for nanoporous low-k ild by plasma assisted atomic layer deposition
08/04/11 - 20110186971 - Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous...

Hardmask materials
06/09/11 - 20110133313 - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped...

Method for forming dual high-k metal gate using photoresist mask and structures thereof
05/26/11 - 20110121436 - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to...

Bpsg film deposition with undoped capping
03/17/11 - 20110062560 - Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is...

Multiple patterning using improved patternable low-k dielectric materials
02/24/11 - 20110042790 - A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method...

Stress balance layer on semiconductor wafer backside
12/16/10 - 20100314725 - A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates...

Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
09/30/10 - 20100244206 - A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial...

Method of forming openings in a semiconductor device and semiconductor device
08/05/10 - 20100193919 - A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the...

Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene
07/22/10 - 20100181655 - A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation...

Low cost fabrication of double box back gate silicon-on-insulator wafers
07/15/10 - 20100176495 - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of...

Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device
07/15/10 - 20100176496 - (where R1, R2 and R3 may be the same or different, at least one of R1, R2 and R3 represents a hydrogen atom and the others represent any one of an alkyl group, alkenyl group, cycloalkyl group and aryl group which are optionally substituted, and n is an integer of...

Dielectric separator layer
07/01/10 - 20100164074 - The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer....

Passivation structure and fabricating method thereof
06/24/10 - 20100155908 - A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality...

Apparatus for manufacturing silicon oxide thin film and method for forming the silicon oxide thin film
06/10/10 - 20100140756 - An object of the present invention is to provide a semiconductor thin film device which employs a silicon oxide thin film having an equivalent level of high insulating performance to those currently used in electronic devices, through a low-temperature printing process on a plastic substrate having plasticity or other types...

Film forming method for a semiconductor
05/13/10 - 20100117204 - The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention,...

Semiconductor device and method of forming semiconductor device
04/01/10 - 20100078773 - A semiconductor device includes a substrate, a semiconductor device structure over the substrate, an insulating film that covers the semiconductor device structure, and a stress-compensation film over the insulating film. The stress-compensation film has a first stress that compensates a second stress working to bend the substrate....

Semiconductor device and method for manufacturing the same
01/28/10 - 20100019357 - A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer...

Semiconductor device and method of manufacturing
01/28/10 - 20100019358 - A semiconductor device and method is provided that has an oxygen diffusion barrier layer between a high-k dielectric and BOX. The method includes depositing a diffusion barrier layer on a BOX layer and gate structure and etching a portion of the diffusion barrier layer from sidewalls of the gate structure....

Structure and method for reducing threshold voltage variation
12/03/09 - 20090294923 - A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage....

Hafnium lanthanide oxynitride films
12/03/09 - 20090294924 - Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium...

Mechanically robust metal/low-k interconnects
12/03/09 - 20090294925 - A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the...

Deep trench in a semiconductor structure
12/03/09 - 20090294926 - A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide...

Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device
10/01/09 - 20090243049 - Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount...

Advanced multilayer dielectric cap with improved mechanical and electrical properties
09/10/09 - 20090224374 - A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N...

Semiconductor device and method for fabricating the same
08/20/09 - 20090206454 - A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the...

Method for manufacturing semiconductor device and semiconductor device
07/02/09 - 20090166813 - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the...