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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Physical Configuration Of Semiconductor (e.g., Mesa, Bevel, Groove, Etc.) > With Thin Active Central Semiconductor Portion Surrounded By Thicker Inactive Shoulder (e.g., For Mechanical Support) With Thin Active Central Semiconductor Portion Surrounded By Thicker Inactive Shoulder (e.g., For Mechanical Support)With Thin Active Central Semiconductor Portion Surrounded By Thicker Inactive Shoulder (e.g., For Mechanical Support) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070252241 - Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is ... 08/09/07 - 20070181979 - Microelectromechanical semiconductor component with cavity structure and method for producing the same One aspect of the invention relates to a semiconductor component with cavity structure and a method for producing the same. The semiconductor component has an active semiconductor chip with the microelectromechanical structure and a wiring structure on its top side. The microelectromechanical structure is surrounded by walls of at least ... 08/09/07 - 20070181978 - Total ionizing dose suppression transistor architecture A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the ... 07/12/07 - 20070158787 - Heterogeneously integrated microsystem-on-a-chip A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ... 03/29/07 - 20070069336 - Seal ring corner design Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the ... 03/15/07 - 20070057348 - Microstructure and manufacturing method thereof A microstructure includes a substrate and a photoresist layer. The substrate has a surface, and the photoresist layer is disposed on the substrate. The photoresist layer has at least one recess, which has a sidewall, a depth and a width. An oblique angle of the sidewall is not less than ... 03/01/07 - 20070045778 - Wafer holder, heater unit used for wafer prober having the wafer holder, and wafer prober having the heater unit A wafer holder for a wafer prober, a heater unit including the same, and a wafer prober including the heater unit are provided in which deformation or breakage of a chuck top can be prevented and proper measurement can be realized even in repeated use. A wafer holder in the ... 11/30/06 - 20060267153 - Microstructure and manufacturing method of the same A microstructure which forms a micromachine is formed by using a silicon wafer as a mainstream, conventionally. In view of this, the invention provides a manufacturing method of a micromachine in which a microstructure is formed over an insulating substrate. The invention provides a micromachine including a layer containing polycrystalline ... 11/02/06 - 20060244105 - Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined ... 09/21/06 - 20060208343 - Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a silicon substrate using a Local Oxidation of Silicon (LOCOS) process, and a silicon membrane is bonded to the substrate. ... 09/14/06 - 20060202310 - Film or layer of semiconducting material, and process for producing the film or layer SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ≦ 20 nm in thickness, has an HF density of ≦ 0.1/cm2, and a surface roughness of 0.2 nm RMS. ... 08/17/06 - 20060180898 - Hybrid type semiconductor integrated circuit and method of manufacturing the same A hybrid type semiconductor integrated circuit includes a semiconductor active region provided in a first area of a substrate; an insulating region surrounding side surfaces of the semiconductor active region; a mechanical electrode provided in a second area adjacent to the first area and surrounded by a part of the ... 08/17/06 - 20060180897 - Silicon-based rf system and method of manufacturing the same A RF system which includes a silicon substrate formed with at least one via-hole filled with conductive material so that both sides of the silicon substrate are electrically connected with one another; at least one flat device formed on one side of the silicon substrate; and at least one RF ... 08/17/06 - 20060180896 - Sensor system Rather than increasing the mass of the structure, the structure in a sensor system suspends its substrate from some mechanical ground. Motion of the substrate relative to the mechanical ground thus provides the movement information. To those ends, the sensor system includes a base, a substrate, and a flexible member ... 06/22/06 - 20060131697 - Semiconductor methods and structures A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without ... 06/15/06 - 20060125058 - Semiconductor circuitry constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has ... 06/15/06 - 20060125057 - Method for the production of a composite sicoi-type substrate comprising an epitaxy stage from 1350° C. to obtain 6H or 4H polytype epitaxy (4) on a transferred thin 6H or 4H polytype layer (3) respectively, if the support (1) consists of Si. ... 04/27/06 - 20060087006 - Physical quantity sensor and manufacturing method therefor A physical quantity sensor includes a pair of physical quantity sensor chips that are inclined with respect to the bottom of an exterior mold package whose side surfaces are each inclined in a thickness direction by an angle ranging from 0° to 5° and are formed in proximity to the ... 04/13/06 - 20060076649 - Substrate for stressed systems and method of making same A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. ... 04/13/06 - 20060076648 - System and method for protecting microelectromechanical systems array using structurally reinforced back-plate Disclosed is an electronic device utilizing interferometric modulation and a package of the device. The packaged device includes a substrate, an interferometric modulation display array formed on the substrate, and a back-plate. The back-plate is placed over the display array with a gap between the back-plate and the display array. ... 03/16/06 - 20060055001 - Semiconductor device having multiple substrates A semiconductor device includes a first substrate including first, second and third layers; and a second substrate including fourth, fifth and sixth layers. The first substrate provides an electric device. The second substrate provides a physical quantity sensor. The first layer of the first substrate and the fourth layer of ... 02/23/06 - 20060038260 - Semiconductor wafer and method of manufacturing semiconductor device A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. ... 11/24/05 - 20050258514 - Microfabricated miniature grids A grid structure and method for manufacturing the same. The grid is used for gating a stream of charged particles in certain types of particle measurement instruments, such as ion mobility spectrometers and the like. The methods include various microfabrication techniques for etching and/or depositing grid structure materials on a ... 10/27/05 - 20050236693 - Wafer stabilization device and associated production method A stabilization device and method for stabilizing a workpiece such as a thin film wafer is presented. The thin wafer is fixed and oriented in planar fashion. The stabilization device is realized by a profiled ring which is arranged on the periphery of the wafer and is intimately connected thereto. ... 09/01/05 - 20050189621 - Processes for hermetically packaging wafer level microscopic structures A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material ... ### FreshPatents.com Support |