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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Integrated Circuit Structure With Electrically Isolated Components > Passive Components In Ics > Including Programmable Passive Component (e.g., Fuse) > Anti-fuse Anti-fuseAnti-fuse patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070257331 - Anti-fuse memory cell An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin ... 10/04/07 - 20070228513 - Probe-based memory Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory. ... 09/13/07 - 20070210415 - Anti-fuse and programming method of the same The invention is directed to an anti-fuse comprised of a substrate, a gate electrode, and a gate dielectric layer. The gate electrode is located on the substrate. The gate dielectric layer is placed between the gate electrode and the substrate. The method of programming the anti-fuse is accomplished by applying ... 09/06/07 - 20070205485 - Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed ... 07/26/07 - 20070170545 - Fuse region and method of fabricating the same In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the ... 06/28/07 - 20070145524 - Fpga structure provided with multi parallel structure and method for forming the same In an FPGA of a semiconductor device and a method of forming the FPGA, a first pattern having a voltage selectable conductivity is formed to connect first vias of the semiconductor device in parallel. ... 06/14/07 - 20070132060 - Electronic component The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on ... 06/14/07 - 20070132059 - Laser fuse with efficient heat dissipation A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse ... 05/31/07 - 20070120221 - Electronically programmable antifuse and circuits made therewith An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, ... 05/31/07 - 20070120220 - Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows ... 05/31/07 - 20070120219 - Conductive layer, manufacturing method of the same, and signal transmission substrate There is provided a method of manufacturing a conductive layer of in a signal transmission substrate. The method includes sewing conductive thread in sheet-like material having an insulating property so as to form one of a plurality of low resistance regions using the conductive thread in a high resistance region ... 03/29/07 - 20070069332 - Energy coupled superlattice structures for silicon based lasers and modulators A waveguide structure includes a SOI substrate. A core structure is formed on the SOI substrate comprising a plurality of multilayers having alternating or aperiodically distributed thin layers of either Si-rich oxide (SRO), Si-rich nitride (SRN) or Si-rich oxynitride (SRON). The multilayers are doped with a rare earth material so ... 03/08/07 - 20070052064 - Semiconductor device and programming method therefor A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the ... 02/08/07 - 20070029639 - Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the ... 01/25/07 - 20070018280 - Antifuse structure and system for closing thereof A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more ... 11/09/06 - 20060249809 - Buried bit line anti-fuse one-time-programmable nonvolatile memory An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P− doped regions. Another N+ doped region, functioning as a bit line, is positioned adjacent and between the two P− doped regions on the substrate. An anti-fuse is defined over the N+ doped region. Two insulator ... 11/02/06 - 20060244099 - Split-channel antifuse array architecture Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon ... 10/19/06 - 20060231922 - Gate dielectric antifuse circuit to protect a high-voltage transistor According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to ... 10/12/06 - 20060226509 - Antifuse element and electrically redundant antifuse array for controlled rupture location An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The ... 09/28/06 - 20060214261 - Anti-fuse circuit for improving reliability and anti-fusing method using the same An anti-fuse circuit includes an anti-fuse device and an electric field control unit. The anti-fuse device is formed having a MOS structure including a first junction, a second junction and a gate terminal. The electric field control unit performs a control operation so that an electric field is formed in ... 09/07/06 - 20060197181 - Semiconductor device, stacked structure, and manufacturing method An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to ... 09/07/06 - 20060197180 - Three-dimensional memory structure and manufacturing method thereof A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form ... 07/06/06 - 20060145292 - Antifuse having uniform dielectric thickness and method for fabricating the same Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an insulating layer on the underlying conductive layer; a lower metal ... 05/11/06 - 20060097345 - Gate dielectric antifuse circuits and methods for operating same A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a ... 04/13/06 - 20060076643 - Fin-type antifuse A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the ... 03/30/06 - 20060065946 - Multi-doped semiconductor e-fuse The present invention provides a multi-doped semiconductor e-fuse for use in an integrated circuit and a method of manufacture therefore. In one aspect, the semiconductor e-fuse 200 includes a semiconductor body 205 having a neck region 220 interposed a first portion 210 of the semiconductor body 205 and a second ... 02/16/06 - 20060033180 - Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in ... 02/02/06 - 20060022301 - Corrugation forming apparatus, corrugation forming method, and fuel cell metal separator formed by the corrugation forming method A corrugation forming apparatus includes, as forming members, a rack tool assembled to a slide table and a pinion tool which rotates with rotation of a shaft. The apparatus also includes, as a displacement synchronization mechanism, a feed rack integrally assembled to the table and a feed pinion gear in ... 01/12/06 - 20060006495 - Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices The invention is a chemically grown oxide layer which prevents dopant diffusion between semiconductor layers. The chemically grown oxide layer may be so thin that it does not form a barrier to electrical conduction, and thus may be formed within active devices such as diodes or bipolar transistors. Such a ... 12/08/05 - 20050269667 - Process for manufacturing integrated resistor and phase-change memory element including this resistor A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this ... 11/10/05 - 20050247997 - On-chip resistance monitor and diagnoses for electrical fuses A fuse resistance monitoring system is disclosed to comprise at least one non-regenerative sense amplifier; at least one fuse module having at least one fuse cell coupled to a first terminal of the sense amplifier; and a reference resistor coupled to a second terminal of the sense amplifier, wherein a ... 07/07/05 - 20050145983 - Structures and methods of anti-fuse formation in soi An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through ... 06/23/05 - 20050133884 - Electronically programmable antifuse and circuits made therewith An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, ... 06/23/05 - 20050133883 - Three-dimensional memory structure and manufacturing method thereof A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form ... 06/09/05 - 20050121743 - Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide A memory cell is formed of a semiconductor junction diode in series with an antifuse. The cell is programmed by rupture of the antifuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The suicide apparently provides a template for crystallization, improving crystallinity and conductivity ... 06/09/05 - 20050121742 - Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred ... ### FreshPatents.com Support |