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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Integrated Circuit Structure With Electrically Isolated Components > Including Dielectric Isolation Means

Including Dielectric Isolation Means

Including Dielectric Isolation Means patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/23/14 - 20140312455 - Patterns of a semiconductor device and method of manufacturing the same
A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a...

10/16/14 - 20140306317 - Finfet fin height control
Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin...

10/16/14 - 20140306318 - Trench formation method and a semiconductor structure thereof
In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about...

10/02/14 - 20140291799 - Semiconductor device including sti structure and fabrication method
Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching...

09/25/14 - 20140284759 - Semiconductor device and method of manufacturing the same
An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, the method includes providing trenches in an end terminal area of a substrate, the end terminal area surrounding an element area of the a substrate, the trenches surrounding the element area, filling a fluent...

09/18/14 - 20140264719 - Varied sti liners for isolation structures in image sensing devices
An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first...

09/18/14 - 20140264720 - Method and structure for nitrogen-doped shallow-trench isolation dielectric
An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top...

09/18/14 - 20140264721 - Isolation structure in a semiconductor device processes and structures
Substantially planar or even layers in semiconductor trenches allow for even distribution of subsequent layers in semiconductor processing and reduce divots in semiconductor device layers. A semiconductor device may include an isolation structure formed in a trench. The isolation structure may have a cover oxide layer and a base oxide...

09/18/14 - 20140264722 - Semiconductor device
A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the...

09/11/14 - 20140252533 - Insulating structure, a method of forming an insulating structure, and a chip scale isolator including such an insulating structure
A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region....

09/11/14 - 20140252534 - Method of making deep trench, and devices formed by the method
A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the...

09/11/14 - 20140252535 - Integrated passive device having improved linearity and isolation
Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric...

09/04/14 - 20140246751 - Integrated circuit using deep trench through silicon (dts)
An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than...

09/04/14 - 20140246752 - Segmented guard ring structures with electrically insulated gap structures and design structures thereof
Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes...

08/07/14 - 20140217544 - Methods of forming a transistor device on a bulk substrate and the resulting device
One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed...

07/31/14 - 20140210038 - Soi rf device and method for forming the same
A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at...

07/17/14 - 20140197516 - Integration of 3d stacked ic device with peripheral circuits
An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a...

07/10/14 - 20140191358 - Two-portion shallow-trench isolation
A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second...

06/26/14 - 20140175596 - Semiconductor substrate for photonic and electronic structures and method of manufacture
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second...

06/26/14 - 20140175597 - Trench with reduced silicon loss
An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on...

06/19/14 - 20140167208 - Chemical mechanical planarization process and structures
A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region....

06/19/14 - 20140167209 - Method of manufacturing a semiconductor device and a semiconductor workpiece
A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main...

06/19/14 - 20140167210 - Semiconductor structure and fabrication method
Various embodiments provide a semiconductor structure and fabrication method. An exemplary semiconductor structure can include a semiconductor substrate having an isolation trench formed in the semiconductor substrate. A first barrier layer can be disposed on a bottom surface and a sidewall of the isolation trench. A light absorption layer can...

06/19/14 - 20140167211 - Method for amnufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so...

06/05/14 - 20140151843 - Semiconductor device structures including metal oxide structures, and related methods of forming semiconductor device structures
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be...

05/29/14 - 20140145295 - Double density semiconductor fins and method of fabrication
Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically...

05/29/14 - 20140145296 - Semiconductor device with an edge termination structure having a closed vertical trench
A semiconductor device includes a semiconductor die having an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The semiconductor device further includes an edge termination structure having a closed vertical trench surrounding the active area. The edge termination structure...

05/15/14 - 20140131831 - Integrated ciruit including an fin-based diode and methods of its fabrication
A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top...

05/15/14 - 20140131832 - Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a...

05/01/14 - 20140117490 - Semiconductor device including esd protection device
A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well...

05/01/14 - 20140117491 - Semiconductor structure and fabrication method
Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each...

04/24/14 - 20140110817 - Sub-lithographic semiconductor structures with non-constant pitch
Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin...

04/17/14 - 20140103483 - Semiconductor device
A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming...

04/03/14 - 20140091425 - Semiconductor integrated circuit device
In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner,...

03/27/14 - 20140084411 - Semiconductor-on-insulator (soi) deep trench capacitor
Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped...

03/27/14 - 20140084412 - Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer...

03/20/14 - 20140077332 - Band engineered semiconductor device and method for manufacturing thereof
The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material...

03/13/14 - 20140070360 - Finfets with vertical fins and methods for forming the same
In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches...

03/06/14 - 20140061850 - Semiconductor device with buried bitline and method for fabricating the same
A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches,...

02/13/14 - 20140042586 - Silicon substrate and method of fabricating the same
There are provided a silicon substrate and a method of fabricating the same, the silicon substrate including: first and second silicon substrates having corresponding bonding surfaces; a silicon oxide film formed between the first and second silicon substrates and having at least one trench communicating with the outside; and a...

02/06/14 - 20140035093 - Integrated circuit interposer and method of manufacturing the same
Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single...

02/06/14 - 20140035094 - Semiconductor structure
One or more embodiments relate to a semiconductor structure, comprising: a silicon rubber layer; and a semiconductor layer overlying the silicon rubber layer....

01/30/14 - 20140027878 - Self-aligned trench over fin
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed...

01/16/14 - 20140015092 - Sealed shallow trench isolation region
A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the...

01/16/14 - 20140015093 - Charge breakdown avoidance for mim elements in soi base technology and method
A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over...

01/09/14 - 20140008756 - Deep trench heat sink
A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a...

01/09/14 - 20140008757 - Integrating through substrate vias from wafer backside layers of integrated circuits
A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed...

01/02/14 - 20140001596 - Sinker with a reduced width
The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion....

12/26/13 - 20130341754 - Shallow trench isolation structures
Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench...

12/26/13 - 20130341755 - Soi substrate, method for manufacturing soi substrate, and method for manufacturing semiconductor device
An insulating portion has a first region, a second region, and a third region in the stated order from the silicon portion side, the nitrogen concentration of the first region is lower than the nitrogen concentration of the second region and the oxygen concentration of the first region, the nitrogen...

12/26/13 - 20130341756 - Semiconductor on glass substrate with stiffening layer and process of making the same
A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the...