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Including Dielectric Isolation Means

Including Dielectric Isolation Means patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Integrated Circuit Structure With Electrically Isolated Components > Including Dielectric Isolation Means



Oxide definition (od) gradient reduced semiconductor device and method of making
04/30/15 - 20150115395 - A method of reducing an oxide definition (OD) density gradient in an integrated circuit (IC) semiconductor device having a placed layout and a set of design rule checking (DRC) rules associated with the placed layout. The method includes computing OD density in insertion regions from OD density information corresponding to...

Insulation structure formed in a semiconductor substrate and method for forming an insulation structure
04/30/15 - 20150115396 - A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a...

Semiconductor device including a wall oxide film and method for forming the same
04/23/15 - 20150108601 - A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region,...

Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion
04/16/15 - 20150102453 - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the...

Forming fins of different materials on the same substrate
04/16/15 - 20150102454 - A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer...

Method and apparatus for high yield contact integration scheme
04/09/15 - 20150097263 - A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming...

Diode string implementation for electrostatic discharge protection
04/09/15 - 20150097264 - A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes...

Semiconductor device and method of manufacturing the same
04/02/15 - 20150091127 - According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region...

Forming three dimensional isolation structures
04/02/15 - 20150091128 - A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then...

Semiconductor device and method of fabricating the same
03/26/15 - 20150084155 - A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible...

Overlay performance for a fin field effect transistor device
03/19/15 - 20150076653 - Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide...

Enlarged fin tip profile for fins of a field effect transistor (finfet) device
03/19/15 - 20150076654 - Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set...

Semiconductor memory device and method for manufacturing same
03/12/15 - 20150069569 - According to one embodiment, a semiconductor memory device includes: a first semiconductor region extending in a first direction; second semiconductor regions extending in a second direction crossing the first direction from the first semiconductor region and arranged in the first direction; and a first element isolation region provided between the...

Integrating a capacitor in an integrated circuit
03/05/15 - 20150061069 - In one aspect, an integrated circuit (IC) includes an isolation trench dividing the IC into a first section and a second section, an active electronic device disposed in the first section of the IC and a capacitor disposed in the second section of the IC and electrically isolated from the...

Semiconductor device
03/05/15 - 20150061070 - A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region,...

Multiple-threshold voltage devices and method of forming same
02/26/15 - 20150054120 - A method comprises growing a channel layer over a substrate, wherein the channel layer comprises a first channel region and a second channel region, and wherein the first channel region and the second channel region are separated by a first isolation region, depositing a hard mask layer over the channel...

Finfet formed over dielectric
02/26/15 - 20150054121 - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor...

Semiconductor structures with shallow trench isolations
02/19/15 - 20150048475 - A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed....

Semiconductor devices and methods of manufacture
02/19/15 - 20150048476 - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench...

Semiconductor device manufacturing method, semiconductor device, and display device
02/12/15 - 20150041947 - An objective of the present invention is to increase production efficiency of high-performance flexible semiconductor devices. A semiconductor device manufacturing method includes: a step of forming an insulating substrate (10) which is configured of glass substrates (11, 13) with a thermal expansion coefficient which approximates the thermal expansion coefficient of...

Semiconductor device including sti structure and method for forming the same
02/12/15 - 20150041948 - Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along...

Epitaxial structures and methods of forming the same
02/05/15 - 20150035113 - An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first...

Semiconductor device, a micro-electro-mechanical resonator and a method for manufacturing a semiconductor device
01/22/15 - 20150021734 - A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide....

Method of forming a shallow trench isolation structure
01/15/15 - 20150014807 - Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills...

Semiconductor structure and fabrication method thereof
01/15/15 - 20150014808 - A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently,...

Fin diode structure
01/15/15 - 20150014809 - A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well,...

Isolation trench through backside of substrate
01/08/15 - 20150008556 - Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a...

Semiconductor device
01/08/15 - 20150008557 - A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a...

Trench liner passivation for dark current improvement
01/01/15 - 20150001669 - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is...

Semiconductor structure and method of forming a harmonic-effect-suppression structure
01/01/15 - 20150001670 - A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate....

Electric field gap device and manufacturing method
01/01/15 - 20150001671 - Substrate material is oxidised around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidised substrate material area between the channels forms a tapered shape with a pointed tip at the top....

Stripe structures and fabrication method thereof
12/11/14 - 20140361399 - A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the...

Integrated circuits including finfet devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same
12/04/14 - 20140353795 - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent...

Shallow trench isolation
11/13/14 - 20140332920 - A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second...

Semiconductor devices having a trench isolation layer and methods of fabricating the same
11/13/14 - 20140332921 - Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating...

Patterns of a semiconductor device and method of manufacturing the same
10/23/14 - 20140312455 - A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a...

Finfet fin height control
10/16/14 - 20140306317 - Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin...

Trench formation method and a semiconductor structure thereof
10/16/14 - 20140306318 - In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about...

Semiconductor device including sti structure and fabrication method
10/02/14 - 20140291799 - Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching...

Semiconductor device and method of manufacturing the same
09/25/14 - 20140284759 - An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, the method includes providing trenches in an end terminal area of a substrate, the end terminal area surrounding an element area of the a substrate, the trenches surrounding the element area, filling a fluent...

Varied sti liners for isolation structures in image sensing devices
09/18/14 - 20140264719 - An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first...

Method and structure for nitrogen-doped shallow-trench isolation dielectric
09/18/14 - 20140264720 - An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top...

Isolation structure in a semiconductor device processes and structures
09/18/14 - 20140264721 - Substantially planar or even layers in semiconductor trenches allow for even distribution of subsequent layers in semiconductor processing and reduce divots in semiconductor device layers. A semiconductor device may include an isolation structure formed in a trench. The isolation structure may have a cover oxide layer and a base oxide...

Semiconductor device
09/18/14 - 20140264722 - A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the...

Insulating structure, a method of forming an insulating structure, and a chip scale isolator including such an insulating structure
09/11/14 - 20140252533 - A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region....

Method of making deep trench, and devices formed by the method
09/11/14 - 20140252534 - A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the...

Integrated passive device having improved linearity and isolation
09/11/14 - 20140252535 - Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric...

Integrated circuit using deep trench through silicon (dts)
09/04/14 - 20140246751 - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than...

Segmented guard ring structures with electrically insulated gap structures and design structures thereof
09/04/14 - 20140246752 - Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes...

Methods of forming a transistor device on a bulk substrate and the resulting device
08/07/14 - 20140217544 - One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed...

Soi rf device and method for forming the same
07/31/14 - 20140210038 - A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at...

Integration of 3d stacked ic device with peripheral circuits
07/17/14 - 20140197516 - An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a...

Two-portion shallow-trench isolation
07/10/14 - 20140191358 - A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second...

Semiconductor substrate for photonic and electronic structures and method of manufacture
06/26/14 - 20140175596 - A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second...

Trench with reduced silicon loss
06/26/14 - 20140175597 - An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on...

Chemical mechanical planarization process and structures
06/19/14 - 20140167208 - A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region....

Method of manufacturing a semiconductor device and a semiconductor workpiece
06/19/14 - 20140167209 - A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main...

Semiconductor structure and fabrication method
06/19/14 - 20140167210 - Various embodiments provide a semiconductor structure and fabrication method. An exemplary semiconductor structure can include a semiconductor substrate having an isolation trench formed in the semiconductor substrate. A first barrier layer can be disposed on a bottom surface and a sidewall of the isolation trench. A light absorption layer can...

Method for amnufacturing a semiconductor device
06/19/14 - 20140167211 - A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so...

Semiconductor device structures including metal oxide structures, and related methods of forming semiconductor device structures
06/05/14 - 20140151843 - Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be...

Double density semiconductor fins and method of fabrication
05/29/14 - 20140145295 - Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically...

Semiconductor device with an edge termination structure having a closed vertical trench
05/29/14 - 20140145296 - A semiconductor device includes a semiconductor die having an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The semiconductor device further includes an edge termination structure having a closed vertical trench surrounding the active area. The edge termination structure...

Integrated ciruit including an fin-based diode and methods of its fabrication
05/15/14 - 20140131831 - A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top...

Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
05/15/14 - 20140131832 - A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a...

Semiconductor device including esd protection device
05/01/14 - 20140117490 - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well...

Semiconductor structure and fabrication method
05/01/14 - 20140117491 - Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each...

Sub-lithographic semiconductor structures with non-constant pitch
04/24/14 - 20140110817 - Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin...

Semiconductor device
04/17/14 - 20140103483 - A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming...

Semiconductor integrated circuit device
04/03/14 - 20140091425 - In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner,...

Semiconductor-on-insulator (soi) deep trench capacitor
03/27/14 - 20140084411 - Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped...

Semiconductor structure with integrated passive structures
03/27/14 - 20140084412 - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer...