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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Integrated Circuit Structure With Electrically Isolated Components

Integrated Circuit Structure With Electrically Isolated Components

Integrated Circuit Structure With Electrically Isolated Components patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/23/14 - 20140312454 - Structure designs and methods for integrated circuit alignment
Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately...

10/09/14 - 20140299963 - Interposer device
An interposer device The invention relates to an interposer device comprising a doped silicon substrate (1) having an epitaxial layer (24) on a first side and two through vias (11, 12) extending from the first side to a second side opposite to the first side of the doped silicon substrate....

10/02/14 - 20140291798 - Semiconductor memory device
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction,...

09/25/14 - 20140284758 - Self-aligned bipolar junction transistors
Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and...

09/18/14 - 20140264715 - Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the...

09/18/14 - 20140264716 - Semiconductor wafer, semiconductor process and semiconductor package
The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die...

09/18/14 - 20140264717 - Method of fabricating a finfet device
A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a...

09/18/14 - 20140264718 - Nonvolatile semiconductor memory device and method of manufacturing the same
A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends...

08/14/14 - 20140225218 - Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems
Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of...

06/26/14 - 20140175594 - Active pad patterns for gate alignment marks
Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM...

06/26/14 - 20140175595 - Semiconductor device and method for manufacturing the same
The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed...

06/19/14 - 20140167206 - Shallow trench isolation structure and method of manufacture
A semiconductor device includes a substrate and a first and second plurality of stack structures arranged over the substrate. The first and second plurality of stack structures are separated by a gap. The substrate includes a first trench between the structures of the first plurality of stack structures, a second...

05/29/14 - 20140145293 - Integrated circuit having improved radiation immunity
An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions...

05/29/14 - 20140145294 - Wafer separation
A method is provided for separation of a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes. The lanes are located between the ICs and extend between a front-side of the metallization layers and a backside...

05/15/14 - 20140131829 - Isolation structures and methods of forming the same
A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first...

05/15/14 - 20140131830 - Solid state devices having fine pitch structures
In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and...

05/01/14 - 20140117488 - Pattern decomposition lithography techniques
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily...

05/01/14 - 20140117489 - Sub-second annealing lithography techniques
Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect...

04/24/14 - 20140110816 - Semiconductor devices
Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch...

04/17/14 - 20140103482 - Semiconductor device having vertical channels and method of manufacturing the same
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The...

03/20/14 - 20140077330 - Three-dimensional integrated circuit device using a wafer scale membrane
A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds...

03/20/14 - 20140077331 - Diode structures using fin field effect transistor processing and method of forming the same
A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into...

03/13/14 - 20140070357 - Soi device with embedded liner in box layer to limit sti recess
A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region,...

03/13/14 - 20140070358 - Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and...

03/13/14 - 20140070359 - Semiconductor memory array structure
A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the...

03/06/14 - 20140061849 - Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent...

02/20/14 - 20140048904 - Semiconductor device, integrated circuit and manufacturing method thereof
One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material...

02/13/14 - 20140042585 - System for designing a semiconductor device, device made, and method of using the system
This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on...

02/06/14 - 20140035091 - Electrostatic discharge protection circuit including a distributed diode string
An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated...

01/02/14 - 20140001595 - Layout architecture for performance improvement
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the...

12/26/13 - 20130341753 - Three-dimensional array structure for memory devices
A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include...

12/12/13 - 20130328155 - Generation of additional shapes on a photomask for a multiple exposure process
The disclosed aspects relate to controlling density of photomasks. One or more unprintable auxiliary patterns can be placed near a mask feature as well as onto a location of a feature of the main pattern. If a density is measured and is not within an acceptable density range, one or...

12/12/13 - 20130328156 - Design support method, recording medium storing design support program and semiconductor device
A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model...

11/28/13 - 20130313677 - Structure for picking up a collector and manufacturing method thereof
A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: a first polysilicon...

10/31/13 - 20130285190 - Layout of a mos array edge with density gradient smoothing
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature...

10/31/13 - 20130285191 - Power conversion apparatus
The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along...

10/31/13 - 20130285192 - Low noise memory array
A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face...

10/17/13 - 20130270670 - Semiconductor package with through silicon via interconnect
The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An...

10/10/13 - 20130264675 - Apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least...

10/03/13 - 20130256827 - Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The...

09/26/13 - 20130249045 - Semiconductor devices with stress relief layers and methods of manufacturing the same
A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer...

09/19/13 - 20130241025 - Electronic system having increased coupling by using horizontal and vertical communication channels
An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in...

09/05/13 - 20130228892 - Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the...

08/22/13 - 20130214379 - Photosensitive resin composition, photosensitive resin composition film, and semiconductor device using the photosensitive resin composition or photosensitive resin composition film
A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide...

08/22/13 - 20130214380 - Area and power saving standard cell methodology
A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by...

08/15/13 - 20130207225 - Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials....

07/18/13 - 20130181320 - Manufacturing techniques for workpieces with varying topographies
Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist...

07/11/13 - 20130175658 - Tone inversion with partial underlayer etch for semiconductor device formation
A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second...

07/04/13 - 20130168800 - Semiconductor device
Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer...

06/27/13 - 20130161781 - Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the...

06/13/13 - 20130147005 - Electroplating methods for fabricating integrated circuit devices and devices fabricated thereby
Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of...

06/13/13 - 20130147006 - Semiconductor memory device and method of fabricating the same
A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area,...