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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Integrated Circuit Structure With Electrically Isolated Components Integrated Circuit Structure With Electrically Isolated ComponentsIntegrated Circuit Structure With Electrically Isolated Components patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.12/13/07 - 20070284690 - Etch features with reduced line edge roughness A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the ... 12/06/07 - 20070278611 - Modified facet etch to prevent blown gate oxide and increase etch chamber life A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for ... 11/15/07 - 20070262410 - Semiconductor device and method for manufacturing A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and ... 11/01/07 - 20070252232 - Semiconductor device and method for manufacturing the same It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81≦x≦0.99, 0.04≦y≦0.25, 0≦z≦1) on a ... 10/25/07 - 20070246793 - Electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer and a process of forming the same A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. ... 10/25/07 - 20070246792 - Method for fabricating back end of the line structures with liner and seed materials A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has ... 10/18/07 - 20070241419 - Transistor and method with dual layer passivation Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device ... 10/04/07 - 20070228508 - Integrated-circuit chip with offset external pads and method for fabricating such a chip An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric ... 10/04/07 - 20070228506 - Composite capacitor and method for forming the same An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) ... 09/27/07 - 20070222025 - Termination for a superjunction device A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns. ... 09/27/07 - 20070222024 - Integrated circuit and production method An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate. ... 09/27/07 - 20070222023 - Integrated circuit having a semiconductor arrangement and method for producing it An integrated circuit having a semiconductor component arrangement and production method is disclosed. In one embodiment, an oxide layer region is provided as a protection against oxidation in the edge region on the surface region of an underlying semiconductor material region. ... 09/27/07 - 20070222021 - Shielded through-via A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal ... 09/27/07 - 20070222020 - Dram (dynamic random access memory) cells A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, ... 09/20/07 - 20070215974 - Semiconductor device and method of manufacturing the same According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film, ... 09/13/07 - 20070210406 - Semiconductor device and method of manufacturing the same A semiconductor device includes a first interlayer insulating film, a second interlayer insulating film formed on the first interlayer insulating film, a plug having a lower portion surrounded by the first interlayer insulating film and an upper portion projecting from the first interlayer insulating film and surrounded by the second ... 09/13/07 - 20070210403 - Isolation regions and their formation A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is ... 09/06/07 - 20070205483 - Mixed-scale electronic interface Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment ... 09/06/07 - 20070205482 - Novel structure and method for metal integration An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the ... 08/09/07 - 20070181965 - Chip element, manufacturing method thereof, and electronic device or equipment using same In a chip element having a substrate, an impedance element formed on the substrate, and a plurality of electrodes formed on the substrate to be connected to the impedance element, the substrate is formed of a low-permittivity material having a permittivity low enough to decrease the parasitic capacitance in a ... 07/26/07 - 20070170540 - Silicon-rich silicon nitrides as etch stops in mems manufature The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a ... 07/26/07 - 20070170539 - Semiconductor device and method for manufacturing the same The invention is directed to a method for manufacturing a field plate of a high voltage device. The field plate is located on a drift region of a substrate, wherein an isolation structure is located on the drift region. The method comprises steps of forming a first dielectric layer over ... 07/26/07 - 20070170538 - Process for the fabricating an electronic integrated circuit and electronic integrated circuit thus obtained An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed ... 07/19/07 - 20070164390 - Silicon nitride passivation layers having oxidized interface A method of forming a passivation film on a semiconductor substrate is provided and includes forming a first silicon nitride containing layer on the substrate, oxidizing the surface of the first silicon nitride containing layer, and forming a second silicon nitride containing layer on the oxidized surface of the first ... 06/28/07 - 20070145518 - Circuit board, semiconductor device, and manufacturing method of circuit board A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the ... 06/28/07 - 20070145515 - Metal electrical fuse structure An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a ... 06/21/07 - 20070138591 - Light modulator with a light-absorbing layer A spatial light modulator includes a first region and a second region. A light-absorbing layer contacts at least a portion of the second region. The light absorbing layer includes a first layer and a second layer, the second layer having a reflectivity less than about 75%. ... 06/14/07 - 20070132053 - Integrated circuit on corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges ... 05/31/07 - 20070120216 - Low cost bonding pad and method of fabricating same A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric ... 05/17/07 - 20070108548 - Optical scanner and method of fabricating the same An optical scanner and a fabricating method thereof are provided. The optical scanner includes a base substrate, a frame, a H-shaped stage, supporters, and a stage driving structure. An interconnection layer having a predetermined pattern is formed on the base substrate. The frame has a rectangular frame shape which is ... 05/10/07 - 20070102782 - Triple operation voltage device A triple operation voltage device including a first type substrate, a high voltage (HV) first type well, a second type well, a low voltage (LV) device well, and a middle voltage (MV) device well is provided. The HV first type well is disposed inside the first type substrate. The second ... 04/26/07 - 20070090483 - Systems, methods and devices relating to actuatably moveable machines Systems, methods and devices relating to actuatably movable machines and with methods of using and manufacturing the same. ... 04/19/07 - 20070085163 - Gallium nitride thin film on sapphire substrate having reduced bending deformation where Y is the curvature radius m, X is the thickness of the gallium nitride film, and Y0, A, and T are positive numbers. ... 04/19/07 - 20070085162 - Capping of copper structures in hydrophobic ild using aqueous electro-less bath Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein. ... 04/19/07 - 20070085161 - Integrated semiconductor temperature detection apparatus and method An integrated semiconductor apparatus (300)(such as, but not limited to, a radio frequency power device) is comprised of a plurality of active device cells (302, 303), a plurality of temperature detectors (304, 305), and a controller (308). The active device cells are preferably each comprised of a plurality of active ... 03/29/07 - 20070069325 - Multilayer substrate for digital tuner and multilayer substrate Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been ... 03/08/07 - 20070052059 - Structure for decreasing minimum feature size in an integrated circuit A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created ... 01/11/07 - 20070007615 - Devices containing multiple undercut profiles Devices including multiple undercut profiles in a single material are disclosed. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in ... 01/04/07 - 20070001257 - Anti-punch-through semiconductor device and manufacturing method thereof An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the ... 12/21/06 - 20060284277 - Semiconductor device including bit line formed using damascene technique and method of fabricating the same A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as ... 11/30/06 - 20060267130 - Semiconductor device including shallow trench isolation (sti) regions with a superlattice therebetween A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers ... 11/23/06 - 20060261434 - Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the ... 11/16/06 - 20060255425 - Low crosstalk substrate for mixed-signal integrated circuits An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled ... 11/16/06 - 20060255424 - Utilizing a protective plug to maintain the integrity of the ftp shrink hinge As robust hinge post structure for use with torsional hinged devices such as micromirrors and method of manufacturing is disclosed. The fabrication process uses a protective layer such as BARC on the bottom of the aperture used to form the hinge post structure to protect an oxide layer during an ... 11/09/06 - 20060249807 - Dielectric isolation type semiconductor device and manufacturing method therefor A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive ... 11/02/06 - 20060244092 - Semiconductor constructions The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion ... 10/05/06 - 20060220169 - Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide. Cavities are formed in the isolation oxide and filled with a conductive material, such a doped polysilicon. Doped regions may be formed in the substrate directly adjacent ... 10/05/06 - 20060220168 - Shielding high voltage integrated circuits Methods and apparatus are disclosed for protecting the electric field distribution of the high voltage semiconductor devices and of the high voltage junction terminating structures from the influences of overlaying interconnections. The proposed methods and apparatus prevent the breakdown voltage of the devices from decreasing. At the same time, circuit ... 10/05/06 - 20060220167 - Ic package with prefabricated film capacitor A method of fabricating an integrated circuit package, comprising prefabricating a film capacitor including forming a first conductive layer, depositing a dielectric layer on the first conductive layer, and depositing a second conductive layer on the dielectric layer; forming a substrate; and laminating the prefabricated film capacitor to the substrate. ... 09/28/06 - 20060214255 - Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operating regions, and the element isolating region is etched to a shallower ... 09/28/06 - 20060214254 - Semiconductor device and manufacturing method of the same To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element ... 09/28/06 - 20060214253 - Integrated dc/dc converter substrate connections Embodiments of the present invention provide an integrated circuit (IC) having an integrated DC-DC power converter therein. This IC is operable to support the distribution of combined power and data signals in a network environment such as an Ethernet network according to protocols such as the power over Ethernet (PoE) ... 08/31/06 - 20060192265 - System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated ... 07/20/06 - 20060157814 - Circuit structures and methods of forming circuit structures with minimal dielectric constant layers An apparatus including a contact point formed on a device layer of a circuit substrate or an interconnect layer on the substrate; a first dielectric material; and a different second polymerizable dielectric material on the substrate and separated from the device layer or the interconnect layer by the first dielectric ... 07/13/06 - 20060151850 - Method of forming a power amplifier In a bipolar junction transistor (BJT) process, according to the linearity of an implant dosage and the output characteristics of a power amplifier, the implant dosage in the poly-silicon layer is selected and controlled in order to form different power level silicon germanium (SiGe) based power amplifiers. Cost, complexity, and ... 06/29/06 - 20060138583 - Method and structure for implanting bonded substrates for electrical conductivity A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material ... 06/22/06 - 20060131687 - Method and structure for implanting bonded substrates for electrical conductivity A process for forming multi-layered substrates, e.g., silicon on silicon. The process includes providing a first substrate, which has a thickness of material to be removed. The thickness of material to be removed includes a first face region. The process includes joining the first face region of the first substrate ... 06/15/06 - 20060125042 - Electronic component and panel for producing the same One embodiment of the invention relates to an electronic component having stacked semiconductor chips, and to a panel for production of the component. In one case, the stack has a flat conductor structure with a chip island on which a stacked semiconductor chip is arranged, while a first semiconductor chip ... 06/01/06 - 20060113626 - Integrated circuit arrangement comprising isolating trenches and a field effect transistor, and associated production method A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. ... 05/18/06 - 20060102977 - Low temperature process for polysilazane oxidation/densification Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane ... 05/11/06 - 20060097339 - Integrated circuits including auxiliary resources In one embodiment, an integrated circuit chip includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, and an unused auxiliary resource that is tied to ground or to a supply voltage such that current does not flow through the resource and power is not dissipated by the ... 03/23/06 - 20060060934 - Method and structure for isolating substrate noise An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit region and a second circuit region. Two guard rings are ... 03/02/06 - 20060043521 - Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the ... 12/29/05 - 20050285217 - Semiconductor device and method for manufacturing the same A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of ... 10/20/05 - 20050230779 - Semiconductor device A semiconductor device is composed at least of a memory circuit part having capacitors and a peripheral circuit part for controlling the memory circuit part and has a first hydrogen barrier film of hydrogen resistance covering a region in which the capacitors are formed and a second hydrogen barrier film ... 09/29/05 - 20050212074 - Semiconductor device and method of manufacturing the same A trench (4) is formed in a semiconductor substrate (1), and then a plasma oxynitride film (5) is formed on a side wall surface and a bottom surface of the trench (4) at a temperature of approximately 300° C. to 650° C. At such a temperature, no outward diffusion of ... 09/22/05 - 20050205961 - Model-based insertion of irregular dummy features A semiconductor device includes an electric circuit, a first conductive feature coupled to the electric circuit, a dielectric material isolating the first conductive feature, and at least two second conductive features having irregular shapes, proximate to the first conductive feature and not electrically coupled to the electric circuit. ... 09/08/05 - 20050194657 - Electro-optical device and electronic apparatus To realize a high performance display at a low cost and a high mounting yield of the driving circuit. An electro-optical device according to the present invention comprises an element substrate having a plurality of pixels and a plurality of data lines electrically connected to the plurality of pixels, a ... 09/01/05 - 20050189605 - Integrated circuit logic with self compensating shapes An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length ... 09/01/05 - 20050189604 - Integrated circuit logic with self compensating block delays An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and ... 07/21/05 - 20050156270 - Semiconductor device and method of manufacturing same The present invention provides a semiconductor device which do not form parasitic transistors in device isolation regions and is capable of narrowing device-to-device intervals, and a method of manufacturing the semiconductor device. The method includes a step for anisotropically etching spots that serve as active regions of a sapphire substrate ... 07/14/05 - 20050151220 - Semiconductor device and cell A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals 151 and output terminals 152 for connecting the cell to another ... 07/07/05 - 20050145976 - Semiconductor package assembly and method for electrically isolating modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394. ... 06/23/05 - 20050133880 - Electrical through-plating of semiconductor chips A method for manufacturing a micromechanical component and a micromechanical component manufactured using this method are described, the micromechanical component having a first substrate, which in turn has at least one cavity and one printed conductor. At least a part of the printed conductor is applied to at least a ... 06/16/05 - 20050127467 - Semiconductor device and method of fabrication thereof, electronic module, and electronic instrument A semiconductor device includes a substrate on which are formed a first group and a second group of leads; and a semiconductor chip having a first group and a second group of electrodes, the first group and a second group of electrodes being arranged respectively on both sides of a ... 06/16/05 - 20050127466 - Wrap-around gate field effect transistor A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first ... 06/02/05 - 20050116312 - Semiconductor device with trench isolation structure and method for fabricating the same The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a ... ### FreshPatents.com Support |