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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 > Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride)

Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride)

Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264638 - Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer...

09/18/14 - 20140264639 - Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer...

09/11/14 - 20140252502 - Multilayer dielectric structures for semiconductor nano-devices
Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including...

09/11/14 - 20140252503 - Multi-plasma nitridation process for a gate dielectric
A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material...

09/04/14 - 20140246735 - Metal gate structure for semiconductor devices
Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a...

09/04/14 - 20140246736 - High-k film apparatus and method
Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine...

08/28/14 - 20140239418 - Semiconductor dielectric interface and gate stack
A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of...

08/28/14 - 20140239419 - Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed...

08/21/14 - 20140231931 - In-situ nitridation of gate dielectric for semiconductor devices
A semiconductor substructure with improved performance and a method of forming the same is described. The semiconductor substructure includes a dielectric film over a substrate, the dielectric film including at least one metal dielectric layer, at least one oxygen-donor layer, and at least one nitride-incorporation layer....

08/21/14 - 20140231932 - Methods and apparatus of metal gate transistors
Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a...

07/10/14 - 20140191339 - Semiconductor structures and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second...

06/26/14 - 20140175569 - Semiconductor device having a high-k gate dielectric layer
A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on...

06/19/14 - 20140167187 - N metal for finfet
An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a...

06/12/14 - 20140159170 - Semiconductor device dielectric interface layer
Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a...

06/05/14 - 20140151818 - Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative...

06/05/14 - 20140151819 - Semiconductor device having sige substrate, interfacial layer and high k dielectric layer
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si1-xGex substrate, wherein the x is greater than 0.4; a Si layer over the Si1-xGex substrate; and a gate structure disposed over the...

05/15/14 - 20140131817 - Gap-fill keyhole repair using printable dielectric material
Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly...

05/08/14 - 20140124876 - Metal gate structure for midgap semiconductor device and method of making same
A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a...

05/01/14 - 20140117465 - Ge-based nmos device and method for fabricating the same
The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron...

05/01/14 - 20140117466 - Replacement gate electrode with multi-thickness conductive metallic nitride layers
Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate...

04/17/14 - 20140103457 - Field effect transistor device having a hybrid metal gate stack
A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy...

04/17/14 - 20140103458 - Gate electrode having a capping layer
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed....

03/27/14 - 20140084389 - Method of manufacturing semiconductor device, substrate processing method and apparatus, non-transitory computer readable recording medium, and semiconductor device
Provided are a semiconductor device manufacturing method by which a semiconductor device in which a threshold voltage is suppressed from changing can be manufactured, a substrate processing method and apparatus, a non-transitory computer-readable recording medium, and the semiconductor device. The semiconductor device manufacturing method includes forming an amorphous first oxide...

03/13/14 - 20140070333 - Self aligned contact with improved robustness
A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the...

03/06/14 - 20140061822 - Substrate backside peeling control
Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the...

02/27/14 - 20140054725 - Transistor device and fabrication method
Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with...

02/27/14 - 20140054726 - Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device
There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor...

02/13/14 - 20140042559 - High-k layers, transistors, and fabrication method
A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The...

02/13/14 - 20140042560 - Multi-layer gate dielectric
A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant....

02/13/14 - 20140042561 - Replacement gate electrode with planar work function material layers
In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of...

02/06/14 - 20140035070 - Metal oxide semiconductor transistor
A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k...

12/19/13 - 20130334618 - Metal oxide semiconductor field effect transistor (mosfet) gate termination
A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion...

12/12/13 - 20130328137 - Modified high-k gate dielectric stack
A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second...

11/28/13 - 20130313656 - Methods of atomic layer deposition of hafnium oxide / erbium oxide bi-layer as advanced gate dielectrics
Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen...

11/28/13 - 20130313657 - Methods of forming fluorinated hafnium oxide gate dielectrics by atomic layer deposition
In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide...

11/28/13 - 20130313658 - High-k dielectric layer based semiconductor structures and fabrication process thereof
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also...

11/28/13 - 20130313659 - Method for producing high-purity lanthanum, high-purity lanthanum, sputtering target formed from high-purity lanthanum, and metal gate film having highy-purity lanthanum as main component
The present invention addresses the problem of providing a technique capable of efficiently and stably providing a method for producing high-purity lanthanum, the method characterized in that: a crude lanthanum oxide starting material having a purity of 2N-5N, excluding gas components, is used; the material is subjected to molten salt...

10/24/13 - 20130277765 - Semiconductor device including graded gate stack, related method and design structure
A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region....

10/24/13 - 20130277766 - Multiple high-k metal gate stacks in a field effect transistor
When forming sophisticated high-k metal gate electrode structures, the threshold voltage characteristics are adjusted on the basis of a well-established high-k dielectric material with an appropriate layer thickness, for instance by incorporating an appropriate metal species. Thereafter, further high-k dielectric materials may be deposited, typically with a greater dielectric constant,...

10/24/13 - 20130277767 - Etch stop layer formation in metal gate process
A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a...

10/10/13 - 20130264659 - Metal oxide protective layer for a semiconductor device
Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active...

09/12/13 - 20130234262 - Semiconductor device and fabrication method
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on...

09/05/13 - 20130228879 - Semiconductor device including sion gate dielectric with portions having different nitrogen concentrations
An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the...

08/29/13 - 20130221450 - Mems device and method of forming the same
A micro electro mechanical system (MEMS) device and a method of forming the same are provided. The MEMS device comprises a semiconductor substrate (100); a well region (110) formed in the semiconductor substrate (100); a source region(111), a drain region (112) and a channel region (113) formed in the well...

08/29/13 - 20130221451 - Mos transistors including sion gate dielectric with enhanced nitrogen concentration at its sidewalls
A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by...

08/15/13 - 20130207203 - Semiconductor device and manufacturing method thereof
Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET...

08/08/13 - 20130200472 - Semiconductor device and a method for manufacturing a semiconductor device
The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and...

07/25/13 - 20130187243 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has...

07/25/13 - 20130187244 - Programmable fets using vt-shift effect and methods of manufacture
Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to...

07/11/13 - 20130175642 - Scaling of metal gate with aluminum containing metal layer for threshold voltage shift
A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate...

06/27/13 - 20130161765 - Mis type semiconductor device and production method therefor
The present invention provides a MIS type semiconductor device having a ZrOxNy gate insulating film wherein threshold voltage is stable. In the MIS type semiconductor device with an operating voltage of 5 V or more, having a gate insulating film on a Si semiconductor layer and a gate electrode on...

06/27/13 - 20130161766 - Gate electrode having a capping layer
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed....