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Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride)

Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 > Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride)



Low-k dielectric sidewall spacer treatment
05/28/15 - 20150145073 - Systems and methods are provided for fabricating a semiconductor structure including sidewall spacers. An example semiconductor structure includes: a gate structure, a first sidewall spacer, and a second sidewall spacer. The gate structure is formed over a substrate. The first sidewall spacer is adjacent to the gate structure, a top...

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
05/21/15 - 20150137271 - One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of...

Dielectric nanocomposites and methods of making the same
05/21/15 - 20150137272 - Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a...

Gate insulating layer and method for forming the same
05/14/15 - 20150129989 - The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a...

Semiconductor devices and methods of manufacturing the same
04/30/15 - 20150115375 - A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed...

Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors
04/23/15 - 20150108589 - A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier...

Anisotropic dielectric material gate spacer for a field effect transistor
04/23/15 - 20150108590 - Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and...

Spacer formation with straight sidewall
04/16/15 - 20150102430 - Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the...

Mechanisms for forming gate dielectric layer
04/16/15 - 20150102431 - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer...

Semiconductor device and method for fabricating the same
03/12/15 - 20150069534 - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment;...

Semiconductor device with an angled sidewall gate stack
03/12/15 - 20150069535 - A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first...

P type mosfet and method for manufacturing the same
02/12/15 - 20150041925 - Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on...

Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
02/05/15 - 20150035086 - One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes...

Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
02/05/15 - 20150035087 - A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured...

Semiconductor structures
02/05/15 - 20150035088 - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second...

Iii-v semiconductor device with interfacial layer
01/29/15 - 20150028428 - A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same....

Semiconductor device with reduced defects
01/29/15 - 20150028429 - A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on...

Integrated circuits having a metal gate structure and methods for fabricating the same
01/22/15 - 20150021714 - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of...

Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
01/01/15 - 20150001644 - An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a...

Replacement metal gate transistor
12/25/14 - 20140374843 - A replacement metal gate transistor is described. Various examples provide a replacement metal gate transistor including a trench, a first sidewall and a second sidewall. A layer is disposed in the trench where the layer has a bottom section disposed on a bottom of the trench and sidewall sections disposed...

Self-aligned insulated film for high-k metal gate device
12/18/14 - 20140367802 - An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD)...

Semiconductor dielectric interface and gate stack
12/04/14 - 20140353771 - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least...

Enhancement-mode transistors with increased threshold voltage
11/27/14 - 20140346615 - A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate....

Transistor and semiconductor structure
11/27/14 - 20140346616 - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the...

Metal gate stack having tialcn as work function layer and/or blocking/wetting layer
10/30/14 - 20140319626 - A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The...

Semiconductor device
10/02/14 - 20140291775 - )...

Methods of atomic-layer deposition of hafnium oxide/erbium oxide bi-layer as advanced gate dielectrics
10/02/14 - 20140291776 - Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen...

Buffer layer on semiconductor devices
10/02/14 - 20140291777 - A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a...

Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
09/18/14 - 20140264638 - A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer...

Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
09/18/14 - 20140264639 - A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer...

Multilayer dielectric structures for semiconductor nano-devices
09/11/14 - 20140252502 - Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including...

Multi-plasma nitridation process for a gate dielectric
09/11/14 - 20140252503 - A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material...

Metal gate structure for semiconductor devices
09/04/14 - 20140246735 - Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a...

High-k film apparatus and method
09/04/14 - 20140246736 - Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine...

Semiconductor dielectric interface and gate stack
08/28/14 - 20140239418 - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of...

Semiconductor device and method of manufacturing the same
08/28/14 - 20140239419 - A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed...

In-situ nitridation of gate dielectric for semiconductor devices
08/21/14 - 20140231931 - A semiconductor substructure with improved performance and a method of forming the same is described. The semiconductor substructure includes a dielectric film over a substrate, the dielectric film including at least one metal dielectric layer, at least one oxygen-donor layer, and at least one nitride-incorporation layer....

Methods and apparatus of metal gate transistors
08/21/14 - 20140231932 - Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a...

Semiconductor structures and fabrication method thereof
07/10/14 - 20140191339 - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second...

Semiconductor device having a high-k gate dielectric layer
06/26/14 - 20140175569 - A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on...

N metal for finfet
06/19/14 - 20140167187 - An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a...

Semiconductor device dielectric interface layer
06/12/14 - 20140159170 - Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a...

Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
06/05/14 - 20140151818 - One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative...

Semiconductor device having sige substrate, interfacial layer and high k dielectric layer
06/05/14 - 20140151819 - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si1-xGex substrate, wherein the x is greater than 0.4; a Si layer over the Si1-xGex substrate; and a gate structure disposed over the...

Gap-fill keyhole repair using printable dielectric material
05/15/14 - 20140131817 - Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly...

Metal gate structure for midgap semiconductor device and method of making same
05/08/14 - 20140124876 - A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a...

Ge-based nmos device and method for fabricating the same
05/01/14 - 20140117465 - The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron...

Replacement gate electrode with multi-thickness conductive metallic nitride layers
05/01/14 - 20140117466 - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate...

Field effect transistor device having a hybrid metal gate stack
04/17/14 - 20140103457 - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy...

Gate electrode having a capping layer
04/17/14 - 20140103458 - A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed....

Method of manufacturing semiconductor device, substrate processing method and apparatus, non-transitory computer readable recording medium, and semiconductor device
03/27/14 - 20140084389 - Provided are a semiconductor device manufacturing method by which a semiconductor device in which a threshold voltage is suppressed from changing can be manufactured, a substrate processing method and apparatus, a non-transitory computer-readable recording medium, and the semiconductor device. The semiconductor device manufacturing method includes forming an amorphous first oxide...

Self aligned contact with improved robustness
03/13/14 - 20140070333 - A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the...

Substrate backside peeling control
03/06/14 - 20140061822 - Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the...

Transistor device and fabrication method
02/27/14 - 20140054725 - Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with...

Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device
02/27/14 - 20140054726 - There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor...

High-k layers, transistors, and fabrication method
02/13/14 - 20140042559 - A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The...

Multi-layer gate dielectric
02/13/14 - 20140042560 - A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant....

Replacement gate electrode with planar work function material layers
02/13/14 - 20140042561 - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of...

Metal oxide semiconductor transistor
02/06/14 - 20140035070 - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k...

Metal oxide semiconductor field effect transistor (mosfet) gate termination
12/19/13 - 20130334618 - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion...

Modified high-k gate dielectric stack
12/12/13 - 20130328137 - A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second...

Methods of atomic layer deposition of hafnium oxide / erbium oxide bi-layer as advanced gate dielectrics
11/28/13 - 20130313656 - Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen...

Methods of forming fluorinated hafnium oxide gate dielectrics by atomic layer deposition
11/28/13 - 20130313657 - In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide...

High-k dielectric layer based semiconductor structures and fabrication process thereof
11/28/13 - 20130313658 - A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also...

Method for producing high-purity lanthanum, high-purity lanthanum, sputtering target formed from high-purity lanthanum, and metal gate film having highy-purity lanthanum as main component
11/28/13 - 20130313659 - The present invention addresses the problem of providing a technique capable of efficiently and stably providing a method for producing high-purity lanthanum, the method characterized in that: a crude lanthanum oxide starting material having a purity of 2N-5N, excluding gas components, is used; the material is subjected to molten salt...

Semiconductor device including graded gate stack, related method and design structure
10/24/13 - 20130277765 - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region....

Multiple high-k metal gate stacks in a field effect transistor
10/24/13 - 20130277766 - When forming sophisticated high-k metal gate electrode structures, the threshold voltage characteristics are adjusted on the basis of a well-established high-k dielectric material with an appropriate layer thickness, for instance by incorporating an appropriate metal species. Thereafter, further high-k dielectric materials may be deposited, typically with a greater dielectric constant,...

Etch stop layer formation in metal gate process
10/24/13 - 20130277767 - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a...

Metal oxide protective layer for a semiconductor device
10/10/13 - 20130264659 - Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active...

Semiconductor device and fabrication method
09/12/13 - 20130234262 - A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on...

Semiconductor device including sion gate dielectric with portions having different nitrogen concentrations
09/05/13 - 20130228879 - An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the...

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