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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2

Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2

Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/17/14 - 20140197498 - Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the...

07/17/14 - 20140197499 - Self aligned contact formation
The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One...

07/03/14 - 20140183664 - Fullerene-based capacitor electrode
A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps...

06/26/14 - 20140175566 - Converting a high dielectric spacer to a low dielectric spacer
A dielectric constant of spacer material in a transistor is changed from a high-κ dielectric material to a low-κ dielectric material. The process uses oxidation treatments to enable the transformation of the high-κ dielectric material to a low-κ dielectric material....

06/26/14 - 20140175567 - Method of depositing films with narrow-band conductive properties
Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently...

06/26/14 - 20140175568 - Replacement source/drain finfet fabrication
A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a...

06/12/14 - 20140159166 - Preventing fin erosion and limiting epi overburden in finfet structures by composite hardmask
A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate...

06/12/14 - 20140159167 - Preventing fin erosion and limiting epi overburden in finfet structures by composite hardmask
A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate...

06/12/14 - 20140159168 - Deep depleted channel mosfet with minimized dopant fluctuation and diffusion levels
CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming...

06/12/14 - 20140159169 - Recessing and capping of gate structures with varying metal compositions
A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over...

06/05/14 - 20140151817 - Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and...

05/29/14 - 20140145274 - Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third...

05/22/14 - 20140138781 - Dielectric equivalent thickness and capacitance scaling for semiconductor devices
A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen...

05/08/14 - 20140124874 - Metal-gate mos transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain....

05/08/14 - 20140124875 - Metal gate structure with device gain and yield improvement
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN...

05/01/14 - 20140117462 - Bulk finfet with punchthrough stopper region and method of fabrication
An improved bulk FinFET with a punchthrough stopper region, and method of fabrication are disclosed. The dopants used to form the punchthrough stopper are supplied from a shallow trench isolation liner. An anneal diffuses the dopants from the shallow trench isolation liner into the bulk substrate and lower portion of...

05/01/14 - 20140117463 - Gate structure and manufacturing method thereof
A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching...

05/01/14 - 20140117464 - Fin-last replacement metal gate finfet
FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is...

04/24/14 - 20140110798 - Methods of forming a semiconductor device with low-k spacers and the resulting device
One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a...

04/17/14 - 20140103455 - Fet devices with oxide spacers
Transistors including oxide spacers and methods of forming the same. Embodiments include planar FETs including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers. Other embodiments include finFETs...

04/17/14 - 20140103456 - Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a...

04/10/14 - 20140097504 - Method for depositing a low-diffusion tialn layer and insulated gate comprising such a layer
A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to...

04/10/14 - 20140097505 - Semiconductor device having nitride layers
According to one embodiment, a second nitride semiconductor layer is provided on a first nitride semiconductor layer and has a band gap wider than that of the first nitride semiconductor layer. A third nitride semiconductor layer is provided above the second nitride semiconductor layer. A fourth nitride semiconductor layer is...

04/10/14 - 20140097506 - Fin field effect transistor, and method of forming the same
The description relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface. The FinFET further...

03/27/14 - 20140084387 - Non-planar iii-v field effect transistors with conformal metal gate electrode & nitrogen doping of gate dielectric interface
A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the...

03/27/14 - 20140084388 - Semiconductor device and method for producing the same
According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so...

03/20/14 - 20140077313 - Transistor device and fabrication method
Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k...

03/13/14 - 20140070332 - Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin...

02/27/14 - 20140054724 - Aligned gate-all-around structure
Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel...

02/20/14 - 20140048891 - Pmos transistors and fabrication method
A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The...

02/13/14 - 20140042558 - Method of fabrication of semiconductor device
The invention relates to a method of fabricating a semiconductor device, the method including: providing a stacked semiconductor structure having a substrate, a buffer layer and one or more device layers; depositing a layer of AlSb on one or more regions of the upper surface of the stacked structure; and...

02/06/14 - 20140035068 - Transistor having replacement metal gate and process for fabricating the same
A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the...

02/06/14 - 20140035069 - Field effect transistor having a trough channel
The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure;...

01/30/14 - 20140027863 - Merged fin finfet with (100) sidewall surfaces and method of making same
A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite...

01/30/14 - 20140027864 - Semiconductor devices and methods for manufacturing the same
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and...

01/30/14 - 20140027865 - Mosfet gate and source/drain contact metallization
A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals....

01/02/14 - 20140001573 - Scavenging metal stack for a high-k gate dielectric
A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The...

01/02/14 - 20140001574 - Improved silicide formation and associated devices
Improved silicide formation and associated devices are disclosed. An exemplary semiconductor device includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region, and a gate structure disposed on a portion of the fin structure, the...

12/12/13 - 20130328135 - Preventing fully silicided formation in high-k metal gate processing
A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein...

12/12/13 - 20130328136 - Structure and method for forming programmable high-k/metal gate memory device
A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second...

11/21/13 - 20130307092 - Semiconductor device and method of manufacturing the same
A semiconductor device includes a gate electrode which is formed on a substrate, and contains Al and Zr, a gate insulating film which is formed to cover at least the upper surface of the gate electrode, and contains Al and Zr, and an insulator layer formed on the substrate to...

11/14/13 - 20130299921 - Method for protecting a gate structure during contact formation
Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region...

11/07/13 - 20130292782 - Memory device having a dielectric containing dysprosium doped hafnium oxide
The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can...

10/31/13 - 20130285159 - Method for etching gate stack
A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack...

10/24/13 - 20130277764 - Etch stop layer formation in metal gate process
A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a...

10/17/13 - 20130270655 - Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin...

10/17/13 - 20130270656 - Replacement gate structures for semiconductor devices
The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having...

10/10/13 - 20130264658 - Reduced s/d contact resistance of iii-v mosfet using low temperature metal-induced crystallilzation of n+ ge
Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the...

10/03/13 - 20130256812 - Method for reducing interfacial layer thickness for high-k and metal gate stack
A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further...

09/26/13 - 20130249021 - Variation resistant metal-oxide-semiconductor field effect transistor (mosfet)
Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the...

09/19/13 - 20130241007 - Use of band edge gate metals as source drain contacts
A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while...

09/19/13 - 20130241008 - Use of band edge gate metals as source drain contacts
A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The...

09/19/13 - 20130241009 - Semiconductor device
A memory cell region comprises a first interlayer insulating film having a bit contact hole, a contact plug formed of a first conductor film embedded in the bit contact hole, and a second conductor film which is stacked on the first interlayer insulating film to constitute a bit line connected...

09/19/13 - 20130241010 - Production method for high-purity lanthanum, high-purity lanthanum, sputtering target composed of high-purity lanthanum, and metal gate film containing high-purity lanthanum as main component
A method for producing high-purity lanthanum having a purity of 4N or more excluding rare earth elements other than lanthanum and gas components, wherein lanthanum having a purity of 4N or more is produced by reducing, with distilled calcium, a lanthanum fluoride starting material that has a purity of 4N...