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Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2

Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2



Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry
05/21/15 - 20150137270 - A transistor device includes a gate electrode structure. The gate electrode structure includes a high-k gate insulation layer, a metal-containing first electrode material positioned above the high-k gate insulation layer, and a second electrode material positioned above the metal-containing first electrode material. The high-k gate insulation layer has a length...

Reduced resistance finfet device with late spacer self aligned contact
05/14/15 - 20150129988 - Embodiments include a method of fabricating a reduced resistance finFET device comprising providing a fin in a semiconductor substrate. A dummy gate is formed over a portion of the fin such that the dummy gate does not initiate selective epitaxy. A source/drain region is formed on the fin such that...

Crystalline multiple-nanosheet iii-v channel fets
05/07/15 - 20150123215 - A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and...

Merged fin finfet with (100) sidewall surfaces and method of making same
04/16/15 - 20150102428 - A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite...

Semiconductor device structures and methods of forming semiconductor structures
04/16/15 - 20150102429 - A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane...

Simplified gate-first hkmg manufacturing flow
04/09/15 - 20150097252 - When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain...

Continuous tuning of erbium silicide metal gate effective work function via a pvd nanolaminate approach for mosfet applications
04/02/15 - 20150091105 - Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties,...

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
03/12/15 - 20150069531 - A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge...

Methods of forming finfet semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices
03/12/15 - 20150069532 - One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure...

Semiconductor device having metal gate and manufacturing method thereof
03/12/15 - 20150069533 - A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate...

Semiconductor structure and method of forming the same
03/05/15 - 20150061041 - A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer...

Mos transistors and fabrication method thereof
02/05/15 - 20150035083 - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; forming a metal gate structure; and forming a source region and a drain region. The method also includes forming a contact-etch-stop layer; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal...

Mos transistors and fabrication method thereof
02/05/15 - 20150035084 - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method...

Doped high-k dielectrics and methods for forming the same
02/05/15 - 20150035085 - Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the...

Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
01/01/15 - 20150001643 - Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric...

Metal gate transistor and method for forming the same
12/11/14 - 20140361384 - Various embodiments provide metal gate transistors and methods for forming the same. In an exemplary method, a substrate having a top surface and a back surface can be provided. A dummy gate can be formed on the top surface. A first interlayer dielectric layer can be formed on the top...

Semiconductor device with oxygen-containing metal gates
11/20/14 - 20140339652 - A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side...

Semiconductor device and method for manufacturing the same
11/13/14 - 20140332907 - A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects,...

Field-effect transistor and fabricating method thereof
11/06/14 - 20140327093 - A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed...

Contact structure employing a self-aligned gate cap
10/23/14 - 20140312433 - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized...

Finfet device with a graphene gate electrode and methods of forming same
10/23/14 - 20140312434 - One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the...

Semiconductor device and method for manufacturing the same
10/02/14 - 20140291774 - A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a...

Replacement metal gate with mulitiple titanium nitride laters
09/04/14 - 20140246734 - A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers...

Semiconductor device having electrode and manufacturing method thereof
08/28/14 - 20140239417 - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric...

Atomic layer deposition of hafnium or zirconium alloy films
08/21/14 - 20140231930 - Provided are methods of depositing hafnium or zirconium containing metal alloy films. Certain methods comprise sequentially exposing a substrate surface to alternating flows of an organometallic precursor and a reductant comprising M(BH4)4 to produce a metal alloy film on the substrate surface, wherein M is selected from hafnium and zirconium,...

Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
07/17/14 - 20140197498 - Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the...

Self aligned contact formation
07/17/14 - 20140197499 - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One...

Fullerene-based capacitor electrode
07/03/14 - 20140183664 - A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps...

Converting a high dielectric spacer to a low dielectric spacer
06/26/14 - 20140175566 - A dielectric constant of spacer material in a transistor is changed from a high-κ dielectric material to a low-κ dielectric material. The process uses oxidation treatments to enable the transformation of the high-κ dielectric material to a low-κ dielectric material....

Method of depositing films with narrow-band conductive properties
06/26/14 - 20140175567 - Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently...

Replacement source/drain finfet fabrication
06/26/14 - 20140175568 - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a...

Preventing fin erosion and limiting epi overburden in finfet structures by composite hardmask
06/12/14 - 20140159166 - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate...

Preventing fin erosion and limiting epi overburden in finfet structures by composite hardmask
06/12/14 - 20140159167 - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate...

Deep depleted channel mosfet with minimized dopant fluctuation and diffusion levels
06/12/14 - 20140159168 - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming...

Recessing and capping of gate structures with varying metal compositions
06/12/14 - 20140159169 - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over...

Self-aligned contacts
06/05/14 - 20140151817 - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and...

Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
05/29/14 - 20140145274 - One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third...

Dielectric equivalent thickness and capacitance scaling for semiconductor devices
05/22/14 - 20140138781 - A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen...

Metal-gate mos transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
05/08/14 - 20140124874 - The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain....

Metal gate structure with device gain and yield improvement
05/08/14 - 20140124875 - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN...

Bulk finfet with punchthrough stopper region and method of fabrication
05/01/14 - 20140117462 - An improved bulk FinFET with a punchthrough stopper region, and method of fabrication are disclosed. The dopants used to form the punchthrough stopper are supplied from a shallow trench isolation liner. An anneal diffuses the dopants from the shallow trench isolation liner into the bulk substrate and lower portion of...

Gate structure and manufacturing method thereof
05/01/14 - 20140117463 - A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching...

Fin-last replacement metal gate finfet
05/01/14 - 20140117464 - FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is...

Methods of forming a semiconductor device with low-k spacers and the resulting device
04/24/14 - 20140110798 - One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a...

Fet devices with oxide spacers
04/17/14 - 20140103455 - Transistors including oxide spacers and methods of forming the same. Embodiments include planar FETs including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers. Other embodiments include finFETs...

Field effect transistor with narrow bandgap source and drain regions and method of fabrication
04/17/14 - 20140103456 - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a...

Method for depositing a low-diffusion tialn layer and insulated gate comprising such a layer
04/10/14 - 20140097504 - A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to...

Semiconductor device having nitride layers
04/10/14 - 20140097505 - According to one embodiment, a second nitride semiconductor layer is provided on a first nitride semiconductor layer and has a band gap wider than that of the first nitride semiconductor layer. A third nitride semiconductor layer is provided above the second nitride semiconductor layer. A fourth nitride semiconductor layer is...

Fin field effect transistor, and method of forming the same
04/10/14 - 20140097506 - The description relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface. The FinFET further...

Non-planar iii-v field effect transistors with conformal metal gate electrode & nitrogen doping of gate dielectric interface
03/27/14 - 20140084387 - A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the...

Semiconductor device and method for producing the same
03/27/14 - 20140084388 - According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so...

Transistor device and fabrication method
03/20/14 - 20140077313 - Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k...

Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
03/13/14 - 20140070332 - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin...

Aligned gate-all-around structure
02/27/14 - 20140054724 - Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel...

Pmos transistors and fabrication method
02/20/14 - 20140048891 - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The...

Method of fabrication of semiconductor device
02/13/14 - 20140042558 - The invention relates to a method of fabricating a semiconductor device, the method including: providing a stacked semiconductor structure having a substrate, a buffer layer and one or more device layers; depositing a layer of AlSb on one or more regions of the upper surface of the stacked structure; and...

Transistor having replacement metal gate and process for fabricating the same
02/06/14 - 20140035068 - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the...

Field effect transistor having a trough channel
02/06/14 - 20140035069 - The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure;...

Merged fin finfet with (100) sidewall surfaces and method of making same
01/30/14 - 20140027863 - A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite...

Semiconductor devices and methods for manufacturing the same
01/30/14 - 20140027864 - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and...

Mosfet gate and source/drain contact metallization
01/30/14 - 20140027865 - A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals....

Scavenging metal stack for a high-k gate dielectric
01/02/14 - 20140001573 - A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The...

Improved silicide formation and associated devices
01/02/14 - 20140001574 - Improved silicide formation and associated devices are disclosed. An exemplary semiconductor device includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region, and a gate structure disposed on a portion of the fin structure, the...

Preventing fully silicided formation in high-k metal gate processing
12/12/13 - 20130328135 - A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein...

Structure and method for forming programmable high-k/metal gate memory device
12/12/13 - 20130328136 - A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second...

Semiconductor device and method of manufacturing the same
11/21/13 - 20130307092 - A semiconductor device includes a gate electrode which is formed on a substrate, and contains Al and Zr, a gate insulating film which is formed to cover at least the upper surface of the gate electrode, and contains Al and Zr, and an insulator layer formed on the substrate to...

Method for protecting a gate structure during contact formation
11/14/13 - 20130299921 - Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region...

Memory device having a dielectric containing dysprosium doped hafnium oxide
11/07/13 - 20130292782 - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can...

Method for etching gate stack
10/31/13 - 20130285159 - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack...

Etch stop layer formation in metal gate process
10/24/13 - 20130277764 - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a...

Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
10/17/13 - 20130270655 - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin...

Replacement gate structures for semiconductor devices
10/17/13 - 20130270656 - The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having...