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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit > With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet)With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/10/08 - 20080006886 - Semiconductor device manufactured using a non-contact implant metrology A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An ... 11/15/07 - 20070262397 - Nanoscale fet A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. ... 11/15/07 - 20070262396 - Transistors having v-shape source/drain metal contacts A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and ... 11/08/07 - 20070257325 - Tri-gate device with conformal pvd workfunction metal on its three-dimensional body and fabrication method thereof A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional ... 10/18/07 - 20070241414 - Semiconductor device and manufacturing process therefor This invention relates to a semiconductor device having a beam made of a semiconductor to which strain is introduced by deflection, and a current is permitted to flow in the beam. ... 10/11/07 - 20070235819 - Semiconductor device and method for manufacturing the same There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor ... 10/11/07 - 20070235818 - Dual-plane complementary metal oxide semiconductor Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. ... 10/04/07 - 20070228494 - Electronic card with protection against aerial discharge An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to ... 10/04/07 - 20070228491 - Tunneling transistor with sublithographic channel Disclosed herein are vertical tunneling transistors with gates that surround transistor bodies that have a width dimension less than a photolithographic dimension. These thin tunneling transistors with surrounding gates are used to obtain low sub-threshold leakage. Various embodiments provide sublithographic bodies by growing a crystalline nanofin from an amorphous structure ... 10/04/07 - 20070228490 - Charge balance techniques for power devices A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a ... 09/27/07 - 20070222001 - Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of ... 09/06/07 - 20070205471 - Integrated circuit with multi-length output transistor segments A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the ... 08/30/07 - 20070200183 - Power semiconductor component with a drift zone and a high-dielectric compensation zone and method for producing a compensation zone A power semiconductor component includes a drift zone in a semiconductor body, a component junction and a compensation zone. The component junction is disposed between the drift zone and a further component zone, which is configured such that when a blocking voltage is applied to the component junction, a space ... 08/23/07 - 20070194393 - Electronic device containing semiconductor polymers and corresponding manufacturing process Described herein is an electronic device provided with an electrode and a region of polymeric material set in contact with the electrode. The electrode has a polysilicon region and a silicide region, which coats the polysilicon region and is arranged, as interface, between the polysilicon region and the region of ... 08/16/07 - 20070187780 - High frequency transistor layout for low source drain capacitance An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in ... 08/02/07 - 20070176245 - Fin fet and method of fabricating same A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the ... 07/26/07 - 20070170524 - Esd protection device for high performance ic The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps ... 07/26/07 - 20070170522 - Semiconductor device and method for fabricating the same The semiconductor device includes an active region, a recess, a Fin-type channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation ... 07/26/07 - 20070170521 - Method and structure to process thick and thin fins and variable fin to fin spacing Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form ... 07/19/07 - 20070164373 - Mos transistor with elevated source and drain structures and method of fabrication thereof A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In ... 07/19/07 - 20070164372 - Systems and methods for forming additional metal routing in semiconductor devices Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing ... 07/12/07 - 20070158764 - Electronic device including a fin-type transistor structure and a process for forming the electronic device An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin ... 07/12/07 - 20070158763 - Semiconductor transistors with expanded top portions of gates A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed ... 07/12/07 - 20070158762 - Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is ... 06/14/07 - 20070132039 - Method and structure for strained finfet devices A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device. ... 06/14/07 - 20070132038 - Embedded stressor structure and process An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide ... 06/07/07 - 20070126066 - Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, the semiconductor circuit includes a plurality of semiconductor cells. Each semiconductor cell ... 05/31/07 - 20070120202 - Semiconductor integrated circuit device and method of testing the same Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the ... 05/31/07 - 20070120201 - Semiconductor device having super junction mos transistor and method for manufacturing the same A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface ... 05/31/07 - 20070120200 - Mos transistor having double gate and manufacturing method thereof There are provided a MOS transistor having a double gate and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a first gate embedded in the insulating layer, in which the top surface of the first gate is exposed, a first gate ... 05/17/07 - 20070108537 - Corner dominated trigate field effect transistor Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order ... 05/17/07 - 20070108536 - Quasi self-aligned source/drain finfet process A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins ... 05/10/07 - 20070102773 - Semiconductor device and method of manufacturing same A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided on the major surface of the semiconductor layer, ... 05/10/07 - 20070102772 - Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between ... 05/10/07 - 20070102771 - Metal oxide semiconductor device The invention is directed to a gate conductive layer, wherein the gate conductive layer straddles over an isolation region and an active region in the isolation region. The gate conductive layer comprises a first portion and a second portion. The first portion is located over the active region and at ... 04/26/07 - 20070090468 - Semiconductor device with silicon-film fins and method of manufacturing the same A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device ... 04/19/07 - 20070085153 - Voltage controlled oscillator with a multiple gate transistor and method therefor A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of ... 04/19/07 - 20070085152 - Reduced area dynamic random access memory (dram) cell and method for fabricating the same A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of ... 04/12/07 - 20070080410 - Method of forming transistor having recess channel in semiconductor memory, and structure thereof Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing a partial surface of the ... 04/12/07 - 20070080409 - Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate mosfet device and method of manufacture thereof A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a ... 03/29/07 - 20070069308 - Ldmos device and method for manufacturing the same Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides ... 02/15/07 - 20070034972 - Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. ... 02/15/07 - 20070034971 - Chevron cmos trigate structure Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs ... 02/08/07 - 20070029624 - Fin-type field effect transistor Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and ... 02/08/07 - 20070029623 - Dual-gate field effect transistor A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running ... 02/01/07 - 20070023846 - Transistor In a first aspect, there is provided a field effect transistor comprising a gate having a modified shape having sharply defined geometric patterns or indents of a dimension that creates de Broglie wave interference. According to a second aspect of the present invention, there is provided a spin transistor comprising ... 01/04/07 - 20070001237 - Segmented channel mos transistor By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges ... 12/28/06 - 20060289946 - Method and apparatus for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ... 12/21/06 - 20060284269 - Method for forming raised structures by controlled selective epitaxial growth of facet using spacer Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film ... 12/07/06 - 20060273408 - Semiconductor device A semiconductor device includes a substrate, and a gate electrode on the substrate via a gate insulating film. The gate insulating film includes a base interface layer on the substrate, metal silicate film on the base interface layer and containing a metal, oxygen, and silicon, and a nitrogen-containing metal silicate ... 11/30/06 - 20060267112 - Semiconductor device and manufacturing method of the same A semiconductor device includes a first device region including a plurality of source regions and a plurality of drain regions of first conductivity type transistors, a plurality of loop-shaped gate electrode regions of the first conductivity type transistors, a second device region including a plurality of source regions and a ... 11/30/06 - 20060267111 - Double-gate fets (field effect transistors) A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back ... 11/30/06 - 20060267110 - Multi-transistor layout capable of saving area A multi-transistor layout capable of saving area includes a substrate; a common drain comprising four sides formed over the substrate; four gates formed over the four sides of the common drain; and four sources formed over outer sides of the four gates corresponding to the common drain. ... 11/23/06 - 20060261419 - Method for fabricating a nanoelement field effect transistor with surrounded gate structure The invention relates to a method for the production of a nanoelement field effect transistor, a nanoelement field effect transistor and a nanoelement arrangement. According to the method for the production of a nanoelement field effect transistor, a nanoelement is formed, a first and a second source-/drain area is coupled ... 11/16/06 - 20060255414 - Method and apparatus for fabricating a carbon nanotube transistor having unipolar characteristics A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least ... 11/09/06 - 20060249799 - Concurrent fin-fet and thick body device fabrication An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the ... 10/19/06 - 20060231907 - Semiconductor device with finfet and method of fabricating the same A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in ... 10/19/06 - 20060231906 - Structure for measuring gate misalignment and measuring method thereof Provided are an improved structure for measuring gate misalignment and a measuring method thereof. The structure includes an active region and a device isolation region, a first gate group including a plurality of gates extending in one direction at one side of the active region, widths of the gates being ... 10/12/06 - 20060226497 - Vertical nanotransistor, method for producing the same and memory assembly A vertical nano-transistor having a source contact, a drain contact, a gate region and a semiconductor cylindrical channel region between the source contact and the drain contact, the cylindrical channel region being embedded in a flexible insulating substrate and in the upper section of the channel region, in such a ... 09/28/06 - 20060214240 - Semiconductor device A semiconductor device 1 is a vertical MOSFET, and includes a plurality of unit cells 10 and a gate electrode 20. Each unit cell 10 includes a back-gate region 12 formed in the semiconductor substrate and a source region 14 formed in the semiconductor substrate so as to adjacently surround ... 09/28/06 - 20060214239 - Transistor, method for manufacturing thereof, substrate for an electrooptical device Aspects of the invention can provide a transistor that can include a supporting substrate, a semiconductor film formed on an underlying insulating film provided on the supporting substrate and including a channel region and source and drain regions, and a gate electrode provided above the channel region. The semiconductor film ... 09/28/06 - 20060214238 - Multi-gate enhancement mode rf switch and bias arrangement Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) ... 09/21/06 - 20060208324 - Linear device A linear MISFET is resilient, flexible and capable of being fabricated into an integrated circuit in an arbitrary shape. Typically a structure includes a source region and drain region arranged in parallel. However, since a channel length of the MISFET for determining the electric characteristics thereof is determined by a ... 09/07/06 - 20060197163 - Semiconductor device and method for manufacturing semiconductor device A semiconductor device comprising: a semiconductor layer having a film formation face in a side wall, the side wall being film-formed with epitaxial-growth; a gate electrode arranged on the side wall of the semiconductor layer; a source layer arranged in one side of the gate electrode, the source layer being ... 08/31/06 - 20060192256 - High-voltage power semiconductor device A semiconductor device, such as a metal-oxide semiconductor field-effect transistor, includes a semiconductor substrate, a drift layer formed on the substrate, a first and a second source region, and a JFET region defined between the first and the second source regions. The JFET region may have a short width and/or ... 08/24/06 - 20060186485 - Nand-type flash memory devices and fabrication methods thereof In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the ... 08/24/06 - 20060186484 - Field effect transistor with narrow bandgap source and drain regions and method of fabrication A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a ... 08/10/06 - 20060175669 - Semiconductor device including finfet having metal gate electrode and fabricating method thereof Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface ... 08/03/06 - 20060170067 - Electronic device, semiconductor device and manufacturing method thereof The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the ... 08/03/06 - 20060170066 - Hybrid-fet and its application as sram A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region ... 07/27/06 - 20060163673 - Method and structure for providing tuned leakage current in cmos integrated circuits A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer ... 07/20/06 - 20060157804 - Field effect transistor and method for manufacturing the same A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stripe-shaped opening is formed. Via the opening, an undoped GaN ... 06/29/06 - 20060138565 - Power metal oxide semiconductor transistor layout with lower output resistance and high current limit A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, ... 06/22/06 - 20060131669 - Thin film transistor for imaging system An annular thin film transistor includes an annular source electrode disposed above the layer of the semiconductor material, a drain electrode disposed above the layer of the semiconductor material within the annular source electrode, and an active channel between the drain electrode and the annular source electrode, wherein a surface ... 06/22/06 - 20060131668 - Methods and systems for improved current sharing between parallel power semiconductors in power converters Methods and systems for current sharing between power semiconductors in an assembly are provided. The power semiconductor assembly includes a plurality of power semiconductors, each comprising at least one output conductor, the plurality of output conductors are electrically coupled together in parallel, an output bus network configured to transpose the ... 06/15/06 - 20060125025 - Vertical field effect transistor and method for fabricating the same A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region where electric carriers are transported; a lower electrode, connected to the bottom of the active region and functioning as one of source and drain regions; an upper electrode, connected to ... 05/25/06 - 20060108650 - Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. ... 05/11/06 - 20060097330 - Asymmetrical layout structure for esd protection A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias ... 05/11/06 - 20060097329 - Fin device with capacitor integrated under gate electrode A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and ... 05/04/06 - 20060091482 - Metal oxide semiconductor (mos) transistors having a recessed gate electrode and methods of fabricating the same A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. ... 05/04/06 - 20060091481 - Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of ... 05/04/06 - 20060091480 - Lateral double diffused mos transistors The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In ... 04/27/06 - 20060086991 - Semiconductor component and method for producing the same A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centres (80A, 80B) in the semiconductor body (100) for the recombination of ... 03/30/06 - 20060065937 - Short channel effect of mos devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at ... 03/16/06 - 20060054978 - Multiple dielectric finfet structure and method Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics ... 03/09/06 - 20060049469 - Integrated semiconductor circuit comprising a transistor and a strip conductor An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode ... 03/09/06 - 20060049468 - Interconnection architecture and method of assessing interconnection architecture A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected. ... 03/02/06 - 20060043502 - Structure and method to fabricate finfet devices There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce ... 03/02/06 - 20060043501 - Nitride semiconductor device In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) ... 03/02/06 - 20060043500 - Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying ... 03/02/06 - 20060043499 - Bi-directional double nmos switch A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved ... 02/23/06 - 20060038241 - Semiconductor device and method of manufacturing the same A semiconductor device comprising a semiconductor substrate having a recess whose depth is not more than 6 nm, a source region and a drain region which are formed in a surface region of the semiconductor substrate so as to sandwich the recess, each of the source region and the drain ... 02/16/06 - 20060033171 - Efficient transistor structure An integrated circuit comprises a first source, a first drain and a first gate that is arranged between the first source and the first drain. A first body is arranged in the first source. An edge of the first body is substantially aligned with the first gate. ... 02/16/06 - 20060033170 - Transistor arrangement A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, ... 02/09/06 - 20060027881 - Process for producing a layer arrangement, and layer arrangement for use as a dual-gate field-effect transistor A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating ... 01/26/06 - 20060017119 - Multi-gate transistor and method of fabricating multi-gate transistor A multi-gate transistor and a method of fabricating the multi-gate transistor may involve forming an active pattern with a multi-channel region, in which a channel region is provided on at least two surfaces of the active pattern. An interconnect may be connected to an interconnect region of the active pattern ... 01/19/06 - 20060011993 - Junction interconnection structures An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of ... 01/12/06 - 20060006480 - Semiconductor integrated circuit device Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting ... 01/05/06 - 20060001110 - Lateral trench mosfet In a lateral trench MOSFET in which a channel width is increased while an element area is not increased to attain reduction in an ON resistance, a source layer (004) and a drain layer (005) are formed in the vicinity of both ends of a trench (008) through multi-directional ion ... 01/05/06 - 20060001109 - High mobility tri-gate devices and methods of fabrication A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a ... 12/22/05 - 20050280103 - Strained-semiconductor-on-insulator finfet device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 12/22/05 - 20050280102 - Field effect transistor and method for manufacturing the same A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed ... 12/22/05 - 20050280101 - Laterally diffused mos transistor having n+ source contact to n-doped substrate Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate. ... 12/15/05 - 20050275043 - Novel semiconductor device design An integrated circuit having small layout area and a method of forming the same are provided. A slant contact is formed by shifting a portion of a contact a distance less than a whole dimension of the contact along the direction shifted. By using slant contacts, the optical proximity effect ... 12/15/05 - 20050275042 - Semiconductor device including a field effect transistor and method of forming thereof A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate ... 12/08/05 - 20050269647 - Flip chip fet device In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be ... 12/01/05 - 20050263832 - Multiple-gate mosfet device with lithography independent silicon body thickness and methods for fabricating the same Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are ... 12/01/05 - 20050263831 - Hybrid planar and finfet cmos devices The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single ... 11/03/05 - 20050242406 - Nonplanar device with stress incorporation layer and method of fabrication A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed ... 10/27/05 - 20050236677 - Semiconductor device layout and channeling implant process A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the ... 10/13/05 - 20050224895 - Semiconductor memory device and manufacturing method thereof The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive ... 10/06/05 - 20050218461 - Integrating device An integrated device using an element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape is provided. A plurality of elements in which a circuit element is formed continuously or intermittently in the longitudinal direction, or a plurality of elements in which ... 09/29/05 - 20050212063 - Thin-film transistor formed on insulating substrate There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part ... 09/29/05 - 20050212062 - Light collector for an led array A light collector for an LED array is provided. The light collector includes a transparent main body having a first portion and a second portion opposite to each other. The first portion has at least one first semi-cylinder and the second portion has a plurality of second semi-cylinders, and the ... 09/22/05 - 20050205945 - Field effect transistor and method of manufacturing same A field effect transistor (FET) and related manufacturing method are disclosed, wherein an active region of a semi-conductor substrate is embossed by a first trench structure. A second trench structure and filling shallow trench insulator laterally defines the active region. Sidewalls of the trenches forming the first trench structure descend ... 09/22/05 - 20050205944 - Multiple dielectric finfet structure and method Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics ... 08/25/05 - 20050184350 - High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor for a standard power supply voltage of the IC or LSI or by utilizing it's process technique. In order to increase an operating voltage of a field effect ... 08/25/05 - 20050184349 - High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures ... 08/25/05 - 20050184348 - Semiconductor device gate structure and method of forming the same A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, ... 08/25/05 - 20050184347 - Semiconductor device and method of evaluating the same The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate form) formed inside the ... 08/18/05 - 20050179096 - Complimentary nitride transistors vertical and common drain A semiconductor device and a method for manufacturing the device are disclosed in which the semiconductor device includes ohmic contacts on different planes and the method for manufacturing the device includes etching a semiconductor stack of different conductivity semiconductor layers in successive steps to create a first opening of a ... 08/11/05 - 20050173768 - Fin fet structure A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving ... 08/11/05 - 20050173767 - Multiplier A multiplier includes NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively, and the voltage value of a constant voltage source (9) and the voltage value of another constant voltage source (12) are set equal ... 07/21/05 - 20050156251 - Semiconductor power module A semiconductor power module includes a filter element made of a magnetic material that can be exchanged as required, while providing a package having a compact size. The power module can be used for a power conversion device for providing power conversion of DC power or AC power by switching ... 07/07/05 - 20050145954 - Structures and methods for making strained mosfets A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few ... 06/09/05 - 20050121732 - Active semiconductor component with an optimized surface area A semiconductor component in which the active junctions extend along at least one cylinder perpendicular to the main surfaces of a semiconductor chip substantially across the entire thickness thereof, said cylinder(s) having a cross-section with an undulated closed curve shape. ... 06/02/05 - 20050116305 - Thin film transistor A thin film transistor according to the present invention may include a gate insulating layer; and a lower pattern placed below the gate insulating layer to contact therewith and having an edge with a taper angle of at most about 80°. With this design, dielectric strength of the gate insulating ... ### FreshPatents.com Support |