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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit > With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet)

With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet)

With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/10/14 - 20140097503 - Memory cell array with semiconductor selection device for multiple memory cells
A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first...

04/03/14 - 20140091401 - Power semiconductor housing with redundant functionality
In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact;...

03/27/14 - 20140084383 - Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of...

03/27/14 - 20140084384 - Semiconductor devices and methods of fabricating the same
A semiconductor device includes a plurality of gate structures on a substrate, the plurality of gate structures including a gate metal pattern and delimiting air gaps formed therebetween, an insulating layer on the plurality of gate structures, and a porous insulating layer between the plurality of gate structures and the...

03/20/14 - 20140077311 - Lateral/vertical semiconductor device
A lateral semiconductor device and/or design including a space-charge generating layer and electrode located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in...

03/13/14 - 20140070328 - Semiconductor device and method of fabricating the same
Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a...

03/13/14 - 20140070329 - Wireless module with active and passive components
A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may...

03/06/14 - 20140061820 - Bulk finfet with controlled fin height and high-k liner
A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second...

03/06/14 - 20140061821 - Electronic device and semiconductor device
Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor...

02/27/14 - 20140054721 - Semiconductor devices and methods of fabricating the same
A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the...

02/27/14 - 20140054722 - Finfet cell architecture with power traces
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate,...

02/27/14 - 20140054723 - Isolation structures for finfet semiconductor devices
One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation...

02/20/14 - 20140048890 - Semiconductor memory device and method of manufacturing the same
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in...

02/13/14 - 20140042553 - Profile pre-shaping for replacement poly gate interlayer dielectric
Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the...

02/13/14 - 20140042554 - Semiconductor device and method for fabricating the same
A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming...

02/13/14 - 20140042555 - Semiconductor device having semiconductor pillar
Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including...

02/13/14 - 20140042556 - Fin field effect transistor devices with self-aligned source and drain regions
Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided. The field effect transistor device includes a source region; a drain region; a plurality of fins connecting the source region and the drain region, the...

02/13/14 - 20140042557 - Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the...

02/06/14 - 20140035066 - Non-planar fet and manufacturing method thereof
The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate...

01/30/14 - 20140027860 - Self-aligned 3-d epitaxial structures for mos device fabrication
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a...

01/30/14 - 20140027861 - Integrated circuit and display device including the same
An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an...

01/30/14 - 20140027862 - Rf cmos transistor design
An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and...

01/09/14 - 20140008733 - Drain extended mos device for bulk finfet technology
Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin...

01/09/14 - 20140008734 - Multi-gate fets and methods for forming the same
A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer...

01/09/14 - 20140008735 - Semiconductor device and fabrication process thereof
A disclosed semiconductor device includes a semiconductor substrate including a first area, a gate electrode formed over the first area of the semiconductor substrate, a first active region formed in the first area of the semiconductor substrate at a lateral side of the gate electrode, a first silicide layer formed...

01/02/14 - 20140001572 - Through gate fin isolation
Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and...

12/26/13 - 20130341733 - Plural differential pair employing finfet structure
A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas....

12/19/13 - 20130334613 - N-channel and p-channel end-to-end finfet cell architecture
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The...

12/19/13 - 20130334614 - Structure and method for finfet device
The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active...

12/19/13 - 20130334615 - Finfets and the methods for forming the same
A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend...

12/19/13 - 20130334616 - Reliable contacts
A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region...

12/12/13 - 20130328134 - Method and apparatus for improving gate contact
A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein...

12/05/13 - 20130320460 - Semiconductor device having fin structure and method of manufacturing the same
In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent...

12/05/13 - 20130320461 - Semiconductor device and method of fabricating the same
A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A...

11/21/13 - 20130307087 - Method for forming a self-aligned contact opening by a lateral etch
A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the...

11/21/13 - 20130307088 - Metal gate finfet device and method of fabricating thereof
A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height...

11/21/13 - 20130307089 - Self-aligned iii-v mosfet fabrication with in-situ iii-v epitaxy and in-situ metal epitaxy and contact formation
A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions....

11/14/13 - 20130299917 - Static random access memory (sram) cell and method for forming same
An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down...

10/31/13 - 20130285157 - Semiconductor structure and method for manufacturing the same
A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with...

10/24/13 - 20130277760 - Dummy finfet structure and method of making same
A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality...

10/24/13 - 20130277761 - Motor control multilayer circuit board
A motor control multilayer printed wiring board includes: a multilayer printed wiring board having a plurality of laminated conductor layers; an upper-row FET connected to the conductor layers and configured to control a motor; a lower-row FET connected to the conductor layers and arranged at a location at which the...

10/17/13 - 20130270652 - Apparatus for finfets
A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation...

10/17/13 - 20130270653 - Non-uniform semiconductor device active area pattern formation
In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of...

10/03/13 - 20130256809 - Electrical-free dummy gate
The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has...

10/03/13 - 20130256810 - Semiconductor device and method for manufacturing the same
The present invention discloses a semiconductor device, which comprises: a first epitaxial layer on a substrate; a second epitaxial layer on the first epitaxial layer, wherein a MOSFET is formed in an active region of the second epitaxial layer; and an inverted-T shaped STI formed in the first epitaxial layer...

10/03/13 - 20130256811 - Electrically conductive lines and integrated circuitry comprising a line of recessed access devices
A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material....

09/26/13 - 20130249018 - Semiconductor chip and semiconductor arrangement
One aspect of the invention relates to a semiconductor chip with a semiconductor body. The semiconductor body has an inner region and a ring-shaped outer region. An electronic structure is monolithically integrated in the inner region and has a controllable first semiconductor component with a first load path and a...

09/19/13 - 20130241005 - Method of manufacturing semiconductor device
A semiconductor device includes first, second and isolation regions; a first insulating film and gate electrode formed over the first region; a second insulating film and gate electrode formed over the second region; a first sidewall formed on a side of the first gate electrode and a second sidewall formed...

09/12/13 - 20130234259 - Semiconductor device and method of manufacturing the same
A semiconductor device and method where a side wall insulating layer, extending perpendicular from a top surface of a semiconductor substrate, is prevented from contacting the semiconductor substrate by a barrier layer formed at an interface between the semiconductor substrate and the insulating layer....

09/12/13 - 20130234260 - Interconnect structure for improved time dependent dielectric breakdown
The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical...

09/05/13 - 20130228875 - Apparatus and method for finfets
A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped...

09/05/13 - 20130228876 - Finfet design with ldd extensions
System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin...

09/05/13 - 20130228877 - Semiconductor device having plural standard cells
Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the...