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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit > Matrix Or Array Of Field Effect Transistors (e.g., Array Of Fets Only Some Of Which Are Completed, Or Structure For Mask Programmed Read-only Memory (rom)) Matrix Or Array Of Field Effect Transistors (e.g., Array Of Fets Only Some Of Which Are Completed, Or Structure For Mask Programmed Read-only Memory (rom))Matrix Or Array Of Field Effect Transistors (e.g., Array Of Fets Only Some Of Which Are Completed, Or Structure For Mask Programmed Read-only Memory (rom)) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/10/08 - 20080006885 - Semiconductor integrated circuit device and method of manufacturing A semiconductor integrated circuit device comprises an insulated-gate field-effect transistor, the insulated-gate field-effect transistor comprising a device isolation insulating film that is provided to extend from an inside of a semiconductor substrate and to project from an upper surface of the semiconductor substrate, and defines a device region on the ... 12/20/07 - 20070290274 - Nonvolatile semiconductor memory device including memory cells formed to have double-layered gate electrodes A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of ... 10/18/07 - 20070241413 - Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures ... 09/20/07 - 20070215954 - Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon ... 08/16/07 - 20070187779 - Semiconductor device and fabricating method thereof A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer ... 08/16/07 - 20070187778 - Shallow trench isolation structure for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed ... 07/26/07 - 20070170520 - Three-dimensional memory cells The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield. ... 06/28/07 - 20070145494 - Semiconductor device and method for manufacturing the same Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. ... 06/21/07 - 20070138576 - Non-volatile semiconductor memory and method for manufacturing a non-volatile semiconductor memory An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second ... 05/10/07 - 20070102770 - Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a ... 05/03/07 - 20070096222 - Low voltage nanovolatile memory cell with electrically transparent control gate An EEPROM having a charge storage element, i.e., a floating gate, in the substrate adjacent to vertically separated source and drain electrodes. An electrically transparent poly control gate allows relatively low voltages to be used for program, erase, and read operations when a plurality of similar devices are arranged in ... 04/26/07 - 20070090467 - Semiconductor substrate with multiple crystallographic orientations A semiconductor structure and its method for fabrication include a first surface semiconductor layer of a first crystallographic orientation located upon a dielectric surface of a substrate. Located laterally separated upon the dielectric surface from the first surface semiconductor layer is a stack layer. The stack layer includes a buried ... 04/19/07 - 20070085150 - Non-volatile semiconductor memory device and method of manufacturing the same A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion ... 04/05/07 - 20070075381 - Semiconductor memory device and method of production The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are ... 03/22/07 - 20070063291 - Semiconductor device with dummy electrode A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the ... 03/08/07 - 20070052040 - Transistor with contoured channel and method for making the same A transistor structure such as a FinFET is formed in a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches in the semiconductor substrate. First and second source/drain regions are arranged along the upper surface of the surface contour, with a ... 02/22/07 - 20070040226 - Cascode circuit A cascode circuit in which two field effect transistors “FET”) are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the ... 01/25/07 - 20070018256 - Semiconductor memory device and method for generating rom data pattern By simplifying the shape of memory cell diffused mask patterns, the patterns are formed stably and the yield of a semiconductor memory device is improved. Adjacent 2-bit memory cell transistors are formed with one diffused mask pattern, the diffused mask patterns are arranged on a memory cell array, and metal ... 12/28/06 - 20060289944 - Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are ... 12/28/06 - 20060289943 - Memory A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality ... 12/21/06 - 20060284268 - Semiconductor integrated circuit device A control gate includes a first conductive film formed in contact with an inter-gate insulating film and a second conductive film electrically connected to the first conductive film. An inter-level insulating film which insulates first and second stacked gate structures from each other. The inter-level insulating film includes a first ... 12/21/06 - 20060284267 - Flash memory and fabrication method thereof A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The ... 12/07/06 - 20060273405 - Semiconductor device and method for patterning In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from ... 12/07/06 - 20060273404 - Tft charge storage memory cell having high-mobility corrugated channel A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing ... 11/23/06 - 20060261418 - Memory cell with double bb implant A buried bitline (BB) may be formed in at least two separate implantation steps, in addition to a pocket implant step. The pocket implant has a first width (W1) and a first depth (D1); the first BB implant has a second width (W2) defined by first sidewall spacers and a ... 09/14/06 - 20060202285 - Semiconductor device, semiconductor element and method for producing same A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the ... 09/14/06 - 20060202284 - Nonvolatile memory Source diffusion layers and drain diffusion layers are alternately formed in lateral device forming regions separated by device isolation regions. Control gate electrodes are formed on both sides of each source diffusion layer through gate ONO films interposed therebetween. Gate electrodes are formed over their corresponding side surfaces of the ... 08/24/06 - 20060186483 - Phase change memory devices employing cell diodes and methods of fabricating the same Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the ... 08/24/06 - 20060186482 - Shared contacts for mosfet devices In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is ... 08/17/06 - 20060180876 - High density stepped, non-planar nitride read only memory A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The ... 08/03/06 - 20060170064 - Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to ... 08/03/06 - 20060170063 - Semiconductor memory device and corresponding programming method A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second ... 07/20/06 - 20060157801 - Nonvolatile semiconductor memory device and method for manufacturing the same A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of ... 07/13/06 - 20060151841 - Pillar nonvolatile memory layout methodology A pillar nonvolatile memory layout methodology includes an arrangement of multiple pillar transistors spaced at intervals on a chip; surrounded in sequence by a SiO2 layer, a floating gate, a dielectric, and a control gate; a separation layer being formed between any two abutted pillar transistors; one up two surfaces ... 07/06/06 - 20060145272 - Mask rom and fabricating method thereof A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced. ... 06/29/06 - 20060138564 - Electrical node of transistor and method of forming the same According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of ... 06/29/06 - 20060138563 - Nand flash memory device A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor ... 06/15/06 - 20060125024 - Semiconductor device and a method of manufacturing the same To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This ... 05/25/06 - 20060108646 - Nrom semiconductor memory device and fabrication method This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside ... 05/18/06 - 20060102967 - Semiconductor integrated circuit A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch ... 05/18/06 - 20060102966 - Printable non-volatile passive memory element and method of making thereof Passive memory devices comprising a support having at least one conductive surface or surface layer and having on at least one side of the support a passive memory element, the passive memory element comprising a first electrode system, an insulating system and a second electrode system, wherein the first electrode ... 05/18/06 - 20060102965 - Semiconductor device There is provided a semiconductor device which includes a projecting semiconductor layer provided on a substrate and having a first side surface and a second side surface opposed to the first side surface, a first gate insulating film provided on the semiconductor layer, a first gate electrode provided on the ... 04/20/06 - 20060081945 - Method for making an array of multi-bit rom cells with each cell having bi-directional read A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the ... 04/20/06 - 20060081944 - Scrambling method to reduce wordline coupling noise A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) ... 03/23/06 - 20060060927 - Nonvolatile semiconductor memory and manufacturing method for the same The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics ... 03/16/06 - 20060054977 - Charge storage memory cell A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may ... 03/16/06 - 20060054976 - Charge-trapping semiconductor memory device Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above ... 01/19/06 - 20060011991 - Non-volatile semiconductor memory device and method of manufacturing the same A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion ... 12/29/05 - 20050285209 - Semiconductor memory device A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer. ... 12/15/05 - 20050275041 - Semiconductor device and its manufacturing method A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film ... 12/15/05 - 20050275040 - Back gate finfet sram A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a ... 12/08/05 - 20050269646 - Memory A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal ... 11/17/05 - 20050253202 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a plurality of memory cell transistors and select gate transistors both formed in a memory cell region of the semiconductor substrate, and a transistor formed in a peripheral circuit region of the substrate and having a high breakdown voltage. Each select gate transistor ... 11/03/05 - 20050242404 - Misalignment-tolerant multiplexing/demultiplexing architectures This disclosure relates to misalignment-tolerant multiplexing/demultiplexing architectures. One architecture enables communication with a conductive-structure array having a narrow spacing and pitch. Another architecture can comprise address elements having a width substantially identical to that of conductive-structures with which each of these address elements is capable of communicating. Another architecture can ... 10/20/05 - 20050230764 - Method for forming 1 tram cell and structure formed thereby A single transistor random access memory cell has an MOS well, a transfer gate of the transistor and a storage capacitor having a storage node in the well that becomes an inversion layer at a threshold voltage near zero. The inversion layer diffuses to an inversion region beneath the transfer ... 10/13/05 - 20050224894 - Semiconductor integrated circuit device A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of ... 10/13/05 - 20050224893 - Semiconductor memroy device with a stacked gate including a floating gate and a control gate and method of manufacturing the same A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a ... 10/13/05 - 20050224892 - Method and structure in the manufacture of mask read only memory A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, ... 10/06/05 - 20050218460 - Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first ... 09/29/05 - 20050212059 - Memory device with quantum dot and method for manufacturing the same Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device comprises a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval; a memory cell which is ... 09/22/05 - 20050205943 - Memory and method of fabricating the same A memory capable of reducing the memory cell size is provided. This memory comprises a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell ... 09/08/05 - 20050194648 - Semiconductor device including a transistor having low threshold voltage and high breakdown voltage A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate ... 08/18/05 - 20050179095 - Non-volatile memory cell A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first ... 08/04/05 - 20050167759 - Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an ... 08/04/05 - 20050167758 - Semiconductor memory device having self-aligned contacts and method of fabricating the same A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns ... 07/14/05 - 20050151206 - Transistor structure with a curved channel, memory cell and memory cell array for drams, and methods for fabricating a dram A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length Leff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends ... 07/14/05 - 20050151205 - Nonvolatile semiconductor memory device This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each ... 06/30/05 - 20050139935 - Contactless flash memory array A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating layer is removed to form ... 06/23/05 - 20050133875 - Three-dimensional memory cells and peripheral circuits The present invention discloses several preferred mask-programmable 3-D memory (3D-MPROM) structures, including pillar-shaped 3D-MPROM, natural-junction 3D-MPROM, interleaved 3D-MPROM, and separate 3D-MPROM. The present invention also makes further improvements to its peripheral circuits. The use of sense-amplifier can significantly lower the leakage-current requirement on the 3D-ROM memory cell. Self-timing can improve ... 06/16/05 - 20050127456 - Semiconductor device and method of fabricating the same A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a ... 06/16/05 - 20050127455 - Transistor array and active-matrix substrate A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, ... 06/16/05 - 20050127454 - Contactless mask programmable rom A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory ... 06/02/05 - 20050116304 - Semiconductor device and manufacturing method thereof In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal ... ### FreshPatents.com Support |