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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit > Combined With Bipolar Transistor Combined With Bipolar TransistorCombined With Bipolar Transistor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/04/07 - 20070228489 - Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body ... 08/09/07 - 20070181952 - Band gap circuit Provided is a band gap constant-voltage circuit which is configured by combining a PMOS transistor, an NMOS transistor, a bipolar transistor, and a resistor, and is capable of preventing an output voltage from being stabilized at 0 V immediately after power supply fluctuation. According to the band gap constant-voltage circuit ... 06/07/07 - 20070126064 - Transistor structure with high input impedance and high current capability and manufacturing process thereof An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to ... 04/19/07 - 20070085148 - Trench igbt for highly capacitive loads An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less ... 03/01/07 - 20070045751 - Bulk resistance control technique The present invention provides a MOS transistor device for providing ESD protection comprising at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one isolation gate formed in ... 11/09/06 - 20060249797 - Semiconductor device and manufacturing method thereof On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a ... 08/31/06 - 20060192253 - Semiconductor device, electrode member and electrode member fabrication method A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an ... 04/13/06 - 20060076629 - Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material A semiconductor structure includes a trench formed in an epitaxial layer that overlies a semiconductor substrate, the sides of the trench being lined with an oxide layer. The trench is filled with a conductive material, e.g., a metal or heavily-doped polysilicon, and the conductive is in contact with the substrate ... 03/30/06 - 20060065936 - Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for ... 11/24/05 - 20050258496 - Integrated circuit including a high voltage bipolar device and low voltage devices An integrated circuit includes a high voltage NPN bipolar transistor and a low voltage device. The NPN bipolar transistor includes a lightly doped p-well as the base region of the transistor while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a ... 11/10/05 - 20050247982 - Transistor constructions and electronic devices The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. ... 09/29/05 - 20050212057 - Semiconductor device and manufacturing method thereof A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface ... 09/22/05 - 20050205941 - Heat resistant ohmic electrode and method of manufacturing the same An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an insulating film formed on the surface of the SiC substrate, a contact hole opened through the insulating film, to expose ... 07/07/05 - 20050145953 - Heterojunction bicmos integrated circuits and method therefor A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in ... ### FreshPatents.com Support |