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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit > Complementary Insulated Gate Field Effect Transistors Complementary Insulated Gate Field Effect TransistorsComplementary Insulated Gate Field Effect Transistors patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/24/08 - 20080017930 - Dual work function metal gate structure and related method of manufacture A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine. ... 01/10/08 - 20080006880 - Method and apparatus for mobility enhancement in a semiconductor device A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide ... 12/20/07 - 20070290270 - Performance and area scalable cell architecture technology An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at ... 12/06/07 - 20070278588 - Semiconductor device and method for manufacturing the same A semiconductor device manufacturing method has forming a gate insulation film on a silicon substrate having an nMOS transistor region and a pMOS transistor region, forming a first metal film on the gate insulation film and thereby forming a gate electrode of the nMOS transistor, removing the first metal film ... 12/06/07 - 20070278587 - Semiconductor device and manufacturing method thereof This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of ... 12/06/07 - 20070278586 - Cmos structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon ... 11/08/07 - 20070257321 - Semiconductor structure and fabrication thereof A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and ... 11/08/07 - 20070257320 - Semiconductor device and manufacturing method thereof A semiconductor device is provided with a first MISFET including a first gate insulating film including a HfAlO film formed over a semiconductor substrate and a first gate electrode, including a nickel silicide film, formed over the first gate insulating film. An aluminum concentration of the HfAlO film on a ... 11/01/07 - 20070252218 - Semiconductor device A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on ... 11/01/07 - 20070252216 - Semiconductor device and a method of manufacturing such a semiconductor device A semiconductor device, specifically a Complementary Metal Oxide Semiconductor (CMOS) device, has a substrate on which are formed first and second field effect transistors. Each of the field effect transistors comprises a source-drain region, a channel of either an n-type or a p-type conductivity semiconductor material formed on the substrate, ... 11/01/07 - 20070252215 - Hybrid orientation soi substrates, and method for forming the same The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with ... 11/01/07 - 20070252214 - Cmos structures and methods using self-aligned dual stressed layers A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact ... 10/11/07 - 20070235813 - Electronic device and a process for forming the electronic device A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second ... 10/04/07 - 20070228484 - Structure and method of integrating compound and elemental semiconductors for high-performance cmos A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such ... 10/04/07 - 20070228480 - Cmos device having pmos and nmos transistors with different gate structures A CMOS device has PMOS and NMOS transistors with different gate structures overlying a semiconductor device. A first gate structure overlying the PMOS device region has a first gate dielectric layer overlying the semiconductor substrate, and a first gate conductor overlying the first gate dielectric layer. A second gate device ... 10/04/07 - 20070228479 - Protection against charging damage in hybrid orientation transistors A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator ... 09/20/07 - 20070215951 - Semiconductor devices having silicided electrodes The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins ... 09/20/07 - 20070215950 - Semiconductor device and manufacturing method thereof A manufacturing method of a semiconductor device according to an embodiment of this invention, includes: forming a gate dielectric film on a substrate and forming a gate electrode layer for a P-type FET on the gate dielectric film, ranging from a P-type FET region to a N-type FET region; in ... 09/13/07 - 20070210389 - Semiconductor constructions, and methods of forming semiconductor constructions The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes ... 08/30/07 - 20070200179 - Strain enhanced cmos architecture with amorphous carbon film and fabrication method of forming the same A strain enhanced CMOS device using amorphous carbon films and fabrication methods of forming the same. The amorphous carbon (a-C) film, such as fluorinated amorphous carbon (a-C:F), is formed of a tensile film or a compressive film to act a stress capping film on the pMOS device region or the ... 08/23/07 - 20070194388 - Semiconductor device having internal stress film A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the NMISFET, a tensile stress is generated ... 08/23/07 - 20070194387 - Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed ... 08/16/07 - 20070187774 - Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a ... 08/16/07 - 20070187773 - Structure and method to induce strain in a semiconductor device channel with stressed film under the gate A semiconductor device is provided with a stressed channel region, where the stress film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surrounds the channel region, and may apply ... 08/16/07 - 20070187772 - Ald of amorphous lanthanide doped tiox films The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium ... 08/16/07 - 20070187769 - Ultra-thin logic and backgated ultra-thin sram Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor ... 08/02/07 - 20070176242 - Semiconductor devices having different gate dielectrics and methods for manufacturing the same A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, ... 07/26/07 - 20070170513 - Semiconductor device and manufacturing method thereof A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and ... 07/19/07 - 20070164367 - Cmos gates with solid-solution alloy tunable work functions Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode is tunable by controlling the selection of the metals or the relative proportion of the metals ... 07/19/07 - 20070164366 - Mitigation of gate oxide thinning in dual gate cmos process technology Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick oxide in an active area where low voltage transistors are formed. Due to fabrication conditions, the thin gate ... 07/19/07 - 20070164365 - Single stress liner for migration stability and speed A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory ... 07/12/07 - 20070158752 - Sram array and analog fet with dual-strain layers Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer ... 07/05/07 - 20070152277 - Mos field-effect transistor and manufacturing method thereof To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved, ... 07/05/07 - 20070152276 - High performance cmos circuits, and methods for fabricating the same The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a ... 06/21/07 - 20070138568 - Semiconductor device, its manufacturing method and electronic apparatus thereof The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide ... 06/21/07 - 20070138567 - Semiconductor device including a semiconductor substrate formed with a shallow impurity region, and a fabrication method for the same A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diffusing the impurity ions, depositing an interlayer insulator film on the isolation regions, the ... 06/21/07 - 20070138566 - Semiconductor device and manufacturing method of the same A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed ... 06/21/07 - 20070138565 - Extreme high mobility cmos logic A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. ... 06/21/07 - 20070138564 - Double anneal with improved reliability for dual contact etch stop liner scheme A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in ... 06/21/07 - 20070138563 - Dual metal gate self-aligned integration A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method ... 06/14/07 - 20070132032 - Selective stress relaxation of contact etch stop layer through layout design A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen ... 06/07/07 - 20070126063 - Semiconductor device and semiconductor device manufacturing method A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller ... 06/07/07 - 20070126062 - Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with ... 05/31/07 - 20070120197 - Method and structure for enhancing both nmosfet and pmosfet performance wth a stressed film A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or ... 05/31/07 - 20070120196 - Prevention of latch-up among p-type semiconductor devices This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first N-type region, wherein one or more P-type metal-oxide-semiconductor (PMOS) devices are disposed therein, a second N-type region adjacent to the first N-type region, wherein one or more PMOS devices are also disposed ... 05/31/07 - 20070120195 - Cmos circuits incorporating passive elements of low contact resistance, and methods of forming same The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end ... 05/17/07 - 20070108530 - Semiconductor device and method for manufacturing the same A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on ... 05/10/07 - 20070102768 - Semiconductor device and a method of manufacturing the same A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which ... 05/03/07 - 20070096218 - Eeprom array with well contacts A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The ... 05/03/07 - 20070096217 - Mos transistors having inverted t-shaped gate electrodes and fabrication methods thereof MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has ... 04/26/07 - 20070090465 - Semiconductor device and method for manufacturing the same In a semiconductor device having a first MIS transistor on a semiconductor substrate, the first MIS transistor includes a p-type semiconductor layer, a first gate insulating film, a first gate electrode, a first sidewall insulting film including at least a first sidewall, an n-type extension diffusion layer, and an n-type ... 04/26/07 - 20070090464 - Power circuit package and fabrication method A power circuit package includes a base including a substrate, a plurality of interconnect circuit layers over the substrate with each including a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the substrate electrical ... 04/26/07 - 20070090463 - Semiconductor devices with multiple heat sinks A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of ... 04/26/07 - 20070090462 - Silicided regions for nmos and pmos devices A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, ... 04/12/07 - 20070080406 - Cmos device with zero soft error rate A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to ... 03/29/07 - 20070069306 - Apparatus and method for improving drive-strength and leakage of deep submicron mos transistors An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased ... 03/29/07 - 20070069305 - Single-event-effect tolerant soi-based inverter, nand element, nor element, semiconductor memory device and data latch circuit Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected ... 03/29/07 - 20070069304 - Semiconductor device and method for fabricating the same A semiconductor device includes: a first element region and a second element region formed on a substrate to be adjacent to each other with an isolation region interposed therebetween; a first gate insulating film formed on the first element region; a second gate insulating film formed on the second element ... 03/29/07 - 20070069303 - Semiconductor device and method of fabricating the same According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second ... 03/29/07 - 20070069302 - Method of fabricating cmos devices having a single work function gate electrode by band gap engineering and article made thereby A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. ... 03/22/07 - 20070063288 - Semiconductor device A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region ... 03/08/07 - 20070052037 - Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A semiconductor device includes a first transistor and a second transistor. The first transistor comprises at least one first gate electrode including a first metal layer. The second transistor comprises at least one second gate electrode including the first metal layer. ... 03/08/07 - 20070052036 - Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having a first gate electrode comprising a first thickness, and an NMOS transistor having a first gate electrode comprising a second thickness, wherein the first thickness is greater than the second ... 03/08/07 - 20070052035 - Method and apparatus for reducing optical crosstalk in cmos image sensors An image sensor in which the metal interconnects are coated with an anti-reflective coating is disclosed. The top, bottom and sides of the metal interconnects may be coated to reduce reflection from all directions. The thickness of the coating is chosen to suppress reflection of light of certain wavelengths incident ... 03/01/07 - 20070045748 - Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently ... 02/22/07 - 20070040225 - High performance mosfet comprising a stressed gate metal silicide layer and method of fabricating the same The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an ... 02/15/07 - 20070034968 - Semiconductor integrated circuit device and a method of manufacturing the same In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as ... 02/15/07 - 20070034967 - Metal gate mosfet by full semiconductor metal alloy conversion A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to ... 02/15/07 - 20070034966 - Dual gate cmos semiconductor devices and methods of fabricating such devices Disclosed are dual gate CMOS devices and methods for fabricating such devices. The dual gate structures are produced by forming a first gate electrode having first conductive stack on transistors of a first channel type and forming a second gate electrode having a second conductive stack on transistors of a ... 02/15/07 - 20070034965 - Cmos image sensor having drive transistor with increased gate surface area and method of manufacturing the same A CMOS image sensor cell includes a semiconductor active region of first conductivity type having a surface thereon and a P-N junction photodiode in the active region. A drive transistor is also provided in the semiconductor active region. The drive transistor has a gate electrode that is configured to receive ... 02/15/07 - 20070034964 - Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one ... 02/15/07 - 20070034963 - Semiconductor device with close stress liner film and method of manufacturing the same Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall spacers may be removed, or substantially reduced in width, prior to forming the stress liners. This may be performed ... 02/08/07 - 20070029620 - Low-cost high-performance planar back-gate cmos A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method ... 02/01/07 - 20070023843 - Semiconductor device and a method of manufacturing the same A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on ... 02/01/07 - 20070023842 - Semiconductor devices having different gate dielectric layers and methods of manufacturing the same A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The ... 01/25/07 - 20070018253 - Memory cell and manufacturing methods A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate, a first memory device array on the semiconductor substrate, and a logic circuit on the semiconductor substrate. Substantially all gates of at least one type of PMOS and NMOS devices in the ... 01/25/07 - 20070018252 - Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same The present invention relates to semiconductor devices that comprise at least one n-channel field effect transistor (n-FET) and/or at least one p-channel field effect transistor (p-FET). The n-FET contains a source region and a drain region with a tensilely stressed metal silicide surface layer, which applies tensile stress to the ... 01/18/07 - 20070013006 - Apparatus and method of manufacture for integrated circuit and cmos device including epitaxially grown dielectric on silicon carbide An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric ... 01/11/07 - 20070007602 - Semiconductor device which has mos structure and method of manufacturing the same The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The ... 01/04/07 - 20070001234 - Systems and methods for reducing ir-drop noise The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) ... 01/04/07 - 20070001233 - Technique for forming contact insulation layers and silicide regions with different characteristics A technique is provided that enables the formation of metal silicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt silicide having a reduced distance to the channel region of an ... 12/28/06 - 20060289940 - Fin fet cmos device, method of manufacturing the same, and memory including fin fet cmos device A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed ... 12/21/06 - 20060284262 - Semiconductor wafer having different impurity concentrations in respective regions A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate ... 12/21/06 - 20060284261 - Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first ... 12/14/06 - 20060278934 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a second conduction type MOS transistor having a gate electrode provided in a second trench formed in the insulation ... 12/14/06 - 20060278933 - Semiconductor device and manufacturing method thereof A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate, ... 12/07/06 - 20060273401 - Manufacturing method of cmos type semiconductor device, and cmos type semiconductor device The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, ... 11/30/06 - 20060267103 - Semiconductor device, method for fabricating the semiconductor device and method for designing the semiconductor device The semiconductor device comprises a semiconductor substrate 10 of a first conduction type, a first well 32a of the first conduction type formed in the semiconductor substrate 10, a second well 32b of a second conduction type formed in the semiconductor substrate 10, and an impurity layer 14 of the ... 11/23/06 - 20060261416 - Semiconductor device and method of manufacturing the same The present invention provides a semiconductor device including an N channel MIS type transistor and a P channel MIS type transistor. The semiconductor device includes a first inter-layer film formed on the NMIS transistor and having a tensile stress, and a second inter-layer film formed on the first inter-layer film ... 11/09/06 - 20060249794 - Method to remove spacer after salicidation to enhance contact etch stop liner stress on mos An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The ... 10/19/06 - 20060231901 - Semiconductor device A semiconductor device comprising an n-channel region and a p-channel region formed on a common substrate, both channel regions having a source and a drain, the device further comprising a gate electrode common to both channel regions and spaced from the substrate by an area of non-polarising dielectric material arranged ... 10/12/06 - 20060226494 - Tungsten plug drain extension A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a second conductivity type is formed in the voltage sustaining layer opposite the ... 10/12/06 - 20060226493 - High performance pfet header in hybrid orientation technology for leakage reduction in digital cmos vlsi designs Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance ... 10/12/06 - 20060226492 - Semiconductor device featuring an arched structure strained semiconductor layer A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the ... 10/12/06 - 20060226491 - Inverted multilayer semiconductor device assembly An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has ... 10/05/06 - 20060220139 - Semiconductor device and fabrication process thereof A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side ... 09/21/06 - 20060208319 - Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical misfet and a vertical misfet, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with ... 09/21/06 - 20060208318 - Mos field effect semiconductor device and method for fabricating the same A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen concentration. As a result, a high-performance CMOS field effect semiconductor device having the n-type gate electrode and the p-type ... 09/21/06 - 20060208317 - Layout structure of semiconductor cells A layout structure of semiconductor cells is described. The layout structure includes multiple semiconductor cells, wherein at least one pair of cells has an overlap member part between them, so that the area of the pair of cells is smaller than the sum of respective areas of the two cells. ... 09/14/06 - 20060202279 - Thin germanium oxynitride gate dielectric for germanium-based devices A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed ... 09/14/06 - 20060202278 - Semiconductor integrated circuit and cmos transistor A p-channel MOS transistor includes first and second SiGe mixed crystal regions formed epitaxially to a silicon substrate at respective outer sides of sidewall insulation films of a gate electrode so as to fill respective trenches formed in source and drain diffusion regions of p-type respectively, wherein the p-channel MOS ... 09/14/06 - 20060202277 - Semiconductor devices with rotated substrates and methods of manufacture thereof Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by ... 09/07/06 - 20060197161 - Semiconductor device and semiconductor integrated circuit device In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is ... 08/24/06 - 20060186480 - Charge-trapping memory device and method for production A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the ... 08/17/06 - 20060180869 - Primitive cell that is robust against esd A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a ... 08/17/06 - 20060180868 - Structure and method for improved diode ideality A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with ... 08/03/06 - 20060170058 - Amorphous carbon contact film for contact hole etch process A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon ... 07/27/06 - 20060163663 - Metal gate engineering for surface p-channel devices A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in ... 07/27/06 - 20060163662 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second ... 07/27/06 - 20060163661 - Selective doping and thermal annealing method for forming a gate electrode pair with different work functions A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically ... 07/20/06 - 20060157797 - Insulated gate field-effect transistor and a method of manufacturing the same The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type ... 07/20/06 - 20060157796 - Semiconductor device having dual gate electrode and related method of formation A dual gate electrode semiconductor device and related method of formation are disclosed. The semiconductor device comprises a first gate electrode made of a metal silicide layer and a second gate electrode made of a metal layer, wherein the metal suicide is formed from the same metal as the metal ... 07/20/06 - 20060157795 - Structure and method to optimize strain in cmosfets A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N ... 07/13/06 - 20060151837 - In situ doped embedded sige extension and source/drain for enhanced pfet performance Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained ... 07/06/06 - 20060145266 - Semiconductor integrated circuit A semiconductor integrated circuit, whose MOS transistors' layout structure is determined in consideration of the size of a device active region in a gate length direction, in which each transistor is formed. When stresses coming from the device isolation region, etc. are taken into account, for a circuit whose current ... 07/06/06 - 20060145265 - Cmos semiconductor device While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120. ... 07/06/06 - 20060145264 - Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has ... 06/29/06 - 20060138553 - Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of ... 06/29/06 - 20060138552 - Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of ... 06/29/06 - 20060138551 - Semiconductor device, manufacturing method thereof, and cmos integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the ... 06/29/06 - 20060138550 - Semiconductor device with multiple gate dielectric layers and method for fabricating the same Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer ... 06/22/06 - 20060131660 - Semiconductor storage device and semiconductor integrated circuit A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a ... 06/22/06 - 20060131659 - Cmos transistor structure including film having reduced stress by exposure to atomic oxygen A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress ... 06/22/06 - 20060131658 - Mos device, cmos device, and fabricating method thereof A MOS or CMOS device includes a substrate with an active area, a gate oxide layer on the substrate, a gate on the gate oxide layer, first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide layer, spacers formed outside the second sidewalls, and a salicide ... 06/22/06 - 20060131657 - Semiconductor integrated circuit device and method for the same In a surface region of a semiconductor substrate, an element isolation region for isolating the substrate into a plurality of element regions is formed. In each of the plurality of element regions, a pair of trenches, which are formed apart from each other and each have a bottom surface and ... 06/22/06 - 20060131656 - Cmos semiconductor devices having elevated source and drain regions and methods of fabricating the same A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region ... 06/22/06 - 20060131655 - Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to ... 06/15/06 - 20060125021 - Methods of forming sram constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active ... 06/15/06 - 20060125020 - Cmos image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same are disclosed, in which an incidence of void formation is reduced or prevented, to improve characteristics of the image sensor. The CMOS image sensor includes a plurality of photodiode areas in a semiconductor substrate at constant intervals, a dielectric ... 06/15/06 - 20060125019 - Gate defined schottky diode A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to ... 06/15/06 - 20060125018 - Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. ... 06/08/06 - 20060118880 - Semiconductor device including field-effect transistor A semiconductor device includes a semiconductor region, source and drain regions, gate insulating film, and gate electrode. The semiconductor region has a plane orientation of (001). The source and drain regions are formed away from each other in the semiconductor region, and a channel region is formed in the semiconductor ... 06/08/06 - 20060118879 - Cmos transistor and method of manufacture thereof A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon ... 06/08/06 - 20060118878 - Cmos device with selectively formed and backfilled semiconductor substrate areas to improve device performance An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically ... 06/01/06 - 20060113606 - Semiconductor integrated circuit device and method of manufacturing the same The invention provides a CMOS integrated circuit capable of carrying out an operation at a comparatively high supply voltage, comprising a first MOS type transistor having a drain profile to come in contact with a gate through a low concentration region having an impurity concentration which is equal to or ... 05/18/06 - 20060102959 - Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern ... 05/04/06 - 20060091473 - Semiconductor device, manufacturing method thereof, and cmos integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the ... 05/04/06 - 20060091472 - Sram array and analog fet with dual-strain layers Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer ... 05/04/06 - 20060091471 - Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation ... 05/04/06 - 20060091470 - Nonvolatile semiconductor memory device with twin-well A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a ... 04/27/06 - 20060086988 - Semiconductor integrated circuit and fabrication method thereof A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step ... 04/27/06 - 20060086987 - Method for manufacturing a semiconductor device with reduced floating body effect A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated ... 04/20/06 - 20060081937 - Laterally diffused metal oxide semiconductor device and method of forming the same A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region ... 04/13/06 - 20060076627 - Ultra shallow junction formation by epitaxial interface limited diffusion A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is ... 04/06/06 - 20060071282 - Semiconductor device and manufacturing method thereof A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film. ... 03/30/06 - 20060065935 - Patterned backside stress engineering for transistor performance optimization Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance. ... 03/23/06 - 20060060925 - Semiconductor device structure with active regions having different surface directions and methods Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a ... 03/02/06 - 20060043494 - Semiconductor device and method of manufacturing semiconductor device A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between ... 03/02/06 - 20060043493 - Semiconductor device and method for fabricating the same A semiconductor device includes: a first gate insulating film formed on a first nMOS transistor region in a semiconductor substrate; a second gate insulating film formed on a first pMOS transistor region in the substrate; a third gate insulating film formed on a second nMOS transistor region in the substrate; ... 02/23/06 - 20060038239 - Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions a p-type MIS transistor comprising a pair of source/drain regions formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film and having a first ... 02/23/06 - 20060038238 - Integrated circuit incorporating higher voltage devices and low voltage devices therein An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a transistor having a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region ... 02/23/06 - 20060038237 - Integrated circuit incorporating higher voltage devices and low voltage devices therein An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch ... 02/16/06 - 20060033167 - Reduced-step cmos processes for low-cost radio frequency identification devices Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular ... 02/09/06 - 20060027876 - Cmos device with improved performance and method of fabricating the same A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first ... 02/02/06 - 20060022279 - Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying ... 02/02/06 - 20060022278 - Method and structure for a low voltage cmos integrated circuit incorporating higher-voltage devices A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, ... 02/02/06 - 20060022277 - Planarizing a semiconductor structure to form replacement metal gates A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop. ... 01/26/06 - 20060017113 - High transconductance and drive current high voltage mos transistors A composite MOS transistor (100) includes a first MOS sub-transistor (105) having a first gate dielectric thickness (106), and a second MOS sub-transistor (155) in series connection with the first MOS sub-transistor having a second gate dielectric thickness (107). The second gate dielectric thickness (107) is substantially thicker than the ... 01/26/06 - 20060017112 - Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped ... 01/19/06 - 20060011989 - Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of ... 01/19/06 - 20060011988 - Integrated circuit with multiple spacer insulating region widths An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors ... 01/19/06 - 20060011987 - Method for fabricating a p-type shallow junction using diatomic arsenic The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the ... 01/19/06 - 20060011986 - Semiconductor device and method for manufacturing the same A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to ... 01/19/06 - 20060011985 - Asymmetric hetero-doped high-voltage mosfet (ah2mos) An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a ... 01/12/06 - 20060006474 - Semiconductor device In an active region a pair of source/drain regions of an nMOS transistor is provided. Between the paired source/drain regions the semiconductor substrate has a region provided with a gate electrode layer with a gate oxide film interposed. The gate electrode layer extends on both the active region and an ... 01/05/06 - 20060001106 - Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples. ... 12/29/05 - 20050285206 - Semiconductor device and manufacturing method thereof The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is comprised of metal silicide containing Ni, metal with a work function lower than that of Ni, and Si, and a gate electrode of a ... 12/29/05 - 20050285205 - Semiconductor device A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which connects the p-type MIS transistor and the n-type MIS transistor and ... 12/22/05 - 20050280096 - Split source rf mosfet device An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and ... 12/22/05 - 20050280095 - Semiconductor device and manufacturing method thereof The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a ... 12/15/05 - 20050275035 - Gate electrode architecture for improved work function tuning and method of manufacture A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin ... 12/15/05 - 20050275034 - A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance Disclosed is a method and structure where a first spacer is formed and an NFET is implanted, and then a second spacer is formed and a PFET is implanted. A dry nitride etch is then performed which selectively removes the second spacer, stopping selectively on an etch stop. This all ... 12/08/05 - 20050269644 - Forming integrated circuits with replacement metal gate electrodes In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of ... 12/01/05 - 20050263826 - Complementary transistors having different source and drain extension spacing controlled by different spacer sizes Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers ... 12/01/05 - 20050263825 - Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and ... 12/01/05 - 20050263824 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device, comprising: a gate electrode formed on a substrate via a gate insulating film by using a first silicide film; diffusion layers formed in a surface portion of said substrate so as to be positioned at two ends of a ... 11/24/05 - 20050258492 - Low-voltage single-layer polysilicon eeprom memory cell The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A ... 11/24/05 - 20050258491 - Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the ... 11/10/05 - 20050247981 - Memory device having shielded access lines An apparatus including, in one embodiment, a plurality of transistors each formed by: (1) at least a portion of one of a plurality of doped regions formed in a substrate; and (2) at least a portion of one of a plurality of first conductors each extending over one of the ... 11/03/05 - 20050242402 - Semiconductor device and its manufacture method The present invention relates to a semiconductor device which comprises a plug layer which is embedded in a window penetrating an inter-layer insulation film, and flattened by using a chemical mechanical polishing, a titanium Ti film which is deposited to extend from the inter-layer insulation film to the plug layer, ... 10/27/05 - 20050236675 - Semiconductor device and manufacturing method thereof To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate ... 10/13/05 - 20050224889 - Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor ... 09/29/05 - 20050212055 - Field effect transistor An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, ... 09/22/05 - 20050205938 - Semiconductor device and method of manufacture the same A semiconductor device comprises a p-type semiconductor region provided in a semiconductor substrate, an n-type semiconductor region provided in the semiconductor substrate and being in contact with the p-type semiconductor region, an n-type source region and an n-type drain region between which the p-type semiconductor region is sandwiched, a p-type ... 09/15/05 - 20050199965 - Semiconductor device and method for manufacturing semiconductor device A semiconductor device comprising: a semiconductor layer formed on a dielectric; a gate electrode formed on the semiconductor layer; a compound metal layer disposed on a source side in a manner to contact a body region of the semiconductor layer; and an impurity diffusion layer disposed on a drain side ... 09/15/05 - 20050199964 - Cmos circuit including double-insulated-gate field-effect transistors It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ... 09/15/05 - 20050199963 - Semiconductor device and manufacturing method therefor An element isolation dielectric film is formed around device regions in a silicon substrate. The device regions are an n-type diffusion region, a p-type diffusion region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric ... 09/01/05 - 20050189596 - Manufacturing method of the semiconductor device and the semiconductor device A method to impede the constitution of the area wherein the silicide film that is defying to form on a gate electrode. Form an element isolation film, and then a gate dielectric film in a P-channel and an N-channel transistor forming region respectively. Then form a semiconductor film that constructs ... 08/11/05 - 20050173766 - Semiconductor memory and manufacturing method thereof In a semiconductor memory, and a manufacturing method thereof, the semiconductor memory includes a gate stack structure formed on a semiconductor substrate, first and second impurity regions formed adjacent each side of the gate stack structure on the semiconductor substrate, the first and second impurity regions having a channel region ... 08/04/05 - 20050167757 - Semiconductor device in which occurence of slips is suppressed A substrate contains dissolved oxygen at a concentration of not more than 8×1017 atoms/cm3 and an impurity which is used as an acceptor or donor at a concentration of not more than 1×1015 atoms/cm3. In the substrate, an oxygen precipitation layer used to suppress occurrence of a slip starting from ... 08/04/05 - 20050167756 - Laterally diffused metal oxide semiconductor device and method of forming the same A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region ... 07/28/05 - 20050161745 - Cmos device, method for fabricating the same and method for generating mask data An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a ... 07/14/05 - 20050151202 - Semiconductor device having a retrograde dopant profile in a channel region An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in ... 07/07/05 - 20050145950 - Method and structure for improved mosfets using poly/silicide gate height control A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a ... 06/30/05 - 20050139930 - Strained dislocation-free channels for cmos and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a ... 06/30/05 - 20050139929 - Transistor design and layout for performance improvement with strain The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a f |