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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit Insulated Gate Field Effect Transistor In Integrated CircuitInsulated Gate Field Effect Transistor In Integrated Circuit patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/10/08 - 20080006879 - Semiconductor integrated circuit device Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high ... 12/27/07 - 20070296042 - Field-effect transistor structures with gate electrodes with a metal layer Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along ... 12/20/07 - 20070290269 - Device with gates configured in loop structures A device includes a substrate, a first gate, a second gate, and a third gate. The substrate has a first active region and a second active region. The first gate is configured in a first loop structure around the first active region. The second gate is configured in a second ... 12/13/07 - 20070284669 - Method and structure to process thick and thin fins and variable fin to fin spacing Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form ... 11/29/07 - 20070272985 - Stagger memory cell array A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of ... 11/15/07 - 20070262390 - Insulated gate semiconductor device Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad ... 11/08/07 - 20070257319 - Integrating high performance and low power multi-gate devices A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width ... 11/08/07 - 20070257318 - Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device manufactured by the method Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked ... 08/16/07 - 20070187768 - Nano-enabled memory devices and anisotropic charge carrying arrays Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the ... 08/16/07 - 20070187767 - Semiconductor device including misfet A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a source/drain layer, and a germanide layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain layer is formed on both sides of ... 08/16/07 - 20070187766 - High voltage semiconductor device utilizing a deep trench structure A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the ... 07/19/07 - 20070164364 - Semiconductor device using sige for substrate and method for fabricating the same A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third ... 07/12/07 - 20070158751 - Semiconductor device and fabrication method thereof In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. ... 06/28/07 - 20070145487 - Multigate device with recessed strain regions Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device. ... 06/21/07 - 20070138562 - Coaxial through chip connection An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically ... 06/21/07 - 20070138561 - Semiconductor device, a manufacturing method thereof, and an evaluation method of the semiconductor device A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated ... 06/14/07 - 20070132031 - Semiconductor device having stressors and method for forming N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in ... 06/07/07 - 20070126061 - Structure for and method of using a four terminal hybrid silicon/organic field effect sensor device A four terminal field effect device comprises a silicon field effect device with a silicon N-type semiconductor channel and an N+ source and drain region. An insulator is deposited over the N-type semiconductor channel. An organic semiconductor material is deposited over the insulator gate forming a organic semiconductor channel and ... 05/31/07 - 20070120194 - Semiconductor device and a method of manufacturing the same A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as ... 05/24/07 - 20070114614 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and ... 05/24/07 - 20070114613 - Programmable nanotube interconnect Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. ... 05/17/07 - 20070108529 - Strained gate electrodes in semiconductor devices Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an ... 05/10/07 - 20070102767 - Method of forming dual gate dielectric layer A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second ... 05/10/07 - 20070102766 - Semiconductor transistors with contact holes close to gates A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the ... 05/03/07 - 20070096216 - Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. The process includes configuring the circuit components to perform an electrical function of ... 05/03/07 - 20070096215 - Transistor with dielectric stressor elements A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, ... 04/19/07 - 20070085145 - High voltage transistor with improved driving current A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side boundary of the first doped region underlies part ... 04/12/07 - 20070080405 - Semiconductor device and method for fabricating the same A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent ... 03/29/07 - 20070069301 - Power transistor A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are connected in parallel and disposed in the semiconductor body such that the plurality of nanotubes are electrically insulated ... 03/29/07 - 20070069300 - Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater ... 03/22/07 - 20070063287 - Semiconductor device To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of ... 03/15/07 - 20070057328 - Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area ... 02/22/07 - 20070040224 - Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the ... 02/22/07 - 20070040223 - Lateral undercut of metal gate in soi device Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate. ... 02/15/07 - 20070034962 - Transistor and method of manufacturing the same In a transistor and a method of manufacturing the transistor, the transistor includes a dummy structure enclosing source/drain structures and channel structures. Thus, a gate electrode of the transistor may be efficiently formed over the channel structures. In addition, the source/drain structure may not grow exceedingly in an epitaxial growth ... 02/08/07 - 20070029619 - Semiconductor devices having a recessed active edge and methods of fabricating the same A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region ... 02/08/07 - 20070029618 - Dual-gate device and method A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor ... 02/01/07 - 20070023841 - Transistor and method for forming the same Disclosed are a transistor and a method for forming the same. The present transistor comprises: a groove formed in a semiconductor substrate; a couple of first sidewall spacers formed in inner sidewalls of the groove, protruding over the substrate; a gate electrode formed between the first sidewall spacers; a gate ... 01/25/07 - 20070018251 - Semiconductor device and method for fabricating the same In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region ... 01/25/07 - 20070018250 - High-voltage diodes formed in advanced power integrated circuit devices A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided. ... 01/25/07 - 20070018249 - Extended drain metal oxide semiconductor transistor and manufacturing method thereof A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source region is formed in a first ... 01/18/07 - 20070013005 - Semiconductor device and method for manufacturing the same A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the ... 01/18/07 - 20070013004 - Tarp loading structure and method for using same A building structure for covering a large object with a cover comprising: multiple frames, each frame being part of a building structure); at least one motor suspended from at least one of said plurality of frames and connected to one or more spools; and an arm lifting structure suspended from ... 01/18/07 - 20070013003 - N-ary mask-programmable memory The present invention discloses an N-ary mask-programmable memory (N-MPM). N-MPM cells can have N cell-states, with N>2. N-MPM cells could be geometry-defined, junction-defined, or both. Based on an nF-opening process (n≧1), partial-contacts with feature size<1F can be implemented with an nF-opening mask with feature size≧1F. N can be a non-integral ... 01/11/07 - 20070007601 - Vertical mosfet sram cell A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch ... 01/11/07 - 20070007600 - Mos transistor and method of manufacturing the same Example embodiments of the present invention relate to a metal oxide semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. A MOS transistor may include a substrate, a semiconductor pattern, a gate insulation layer and/or source-drain regions. The substrate may include an active region and/or a field region. ... 01/04/07 - 20070001232 - Integrated circuit on corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges ... 01/04/07 - 20070001231 - Material systems for dielectrics and metal electrodes A structure having a dielectric layer that includes a dielectric material comprising a first metal nitride, and an electrode layer disposed over the dielectric layer, the electrode layer comprising a second metal nitride, with the first metal nitride and the second metal nitride having at least one metal in common. ... 12/28/06 - 20060289939 - Array substrate and display device having the same An LCD display device in which the gate lines are controlled by a gate circuit part that outputs gate signals to the gate lines. A first signal wiring is formed adjacent to the gate circuit part and transmits a starting signal, which initiates an operation of the gate circuit part, ... 12/21/06 - 20060284260 - Vertical diode formation in soi application A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first ... 12/14/06 - 20060278932 - Secure electrically programmable fuse The present invention provides electrically-programmable fuse structures having radiation inhibitive properties for preventing non-destructive security breaches by radiation imaging techniques such as X-ray imaging, without adversely effecting fuse programmability, and methods of designing the same. ... 12/07/06 - 20060273400 - High voltage analog switch ics and ultrasound imaging systems using same A MOSFET including a JFET resistor resultant between a drain region and a channel region caused by depletion of current carriers. Since most of the drain-source voltage is imposed on the JFET resistor, the voltage imposed on a channel region is reduced to prevent concentration of an electric field therein. ... 11/23/06 - 20060261415 - Method to chemically remove metal impurities from polycide gate sidewalls An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure ... 11/16/06 - 20060255412 - Enhanced access devices using selective epitaxial silicon over the channel region during the formation of a semiconductor device and systems including same A method used during fabrication of a semiconductor device comprises providing a semiconductor wafer comprising at lease one source region, at least one drain region, and at least one channel region. A mask is formed to cover the source region and the drain region, and which leaves the channel region ... 10/19/06 - 20060231900 - Semiconductor device having fine contacts and method of fabricating the same A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, ... 10/19/06 - 20060231899 - Hybrid bulk-soi 6t-sram cell for improved cell stability and performance The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first ... 09/21/06 - 20060208316 - High performance tunneling-biased mosfet and a process for its manufacture A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies ... 09/14/06 - 20060202276 - Semiconductor device and method of making semiconductor devices A semiconductor device includes a semiconductor substrate in which an insulating layer is formed in a part of an region, a semiconductor layer is formed by epitaxial growth and located on the insulating layer, a first gate electrode is formed at the sidewall of the semiconductor layer, first source and ... 08/24/06 - 20060186479 - Semiconductor memory device having local etch stopper and method of manufacturing the same A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate ... 08/24/06 - 20060186478 - Method for optimising transistor performance in integrated circuits A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent ... 08/17/06 - 20060180867 - Field effect transistor and method of fabricating the same Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of ... 08/17/06 - 20060180866 - Structure and method for manufacturing strained finfet A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively ... 07/20/06 - 20060157794 - Non-planar mos structure with a strained channel region An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate ... 07/20/06 - 20060157793 - Mos field effect transistor and manufacture method therefor A method of manufacturing an MOS field effect transistor which reduces a leak current between a source and a drain, thereby reducing power consumption in a standby mode, so that the power consumption can be reduced without impairing the fast operation of the transistor circuit. The method includes the steps ... 06/29/06 - 20060138549 - High-voltage transistor and fabricating method thereof A high-voltage transistor having a low on-resistance and fabricating method thereof are provided. The high-voltage transistor includes a substrate; a shallow-trench isolation layer provided to an upper part of the substrate to a prescribed depth to define an active area; an extended drain region enclosing the shallow-trench isolation layer; a ... 06/29/06 - 20060138548 - Strained silicon, gate engineered fermi-fets A field effect transistor includes a strained silicon channel in a substrate, source/drain regions in the substrate at opposite ends of the strained silicon channel, a gate insulating layer on the strained silicon channel, and a gate on the gate insulating layer. The doping of the strained silicon channel, the ... 06/01/06 - 20060113605 - Hybrid fin field-effect transistor structures and related methods Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. ... 06/01/06 - 20060113604 - Methods for reduced circuit area and improved gate length control Semiconductor devices (102) are presented along with fabrication methods (202) therefor, in which a conductive contact structure (116b) is formed with a lower contact surface (116c) having a lateral contact dimension (152), where the contact structure (116b) is at least partially coupled with a contact landing surface of a polysilicon ... 06/01/06 - 20060113603 - Hybrid semiconductor-on-insulator structures and related methods Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. ... 06/01/06 - 20060113602 - Mos circuit arrangement A MOS circuit arrangement includes a silicon substrate, a semiconductor device, a field oxide layer, and a poly-protective layer. The silicon substrate has a conductive doping incorporated therein, wherein the semiconductor device is electrically connected with the silicon substrate. The field oxide layer is formed on the silicon substrate at ... 05/25/06 - 20060108640 - Semiconductor integrated circuit A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed ... 05/25/06 - 20060108639 - Transistor, method of manufacturing transistor, and method of operating transistor A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially ... 05/18/06 - 20060102958 - Systems and methods for voltage distribution via multiple epitaxial layers Systems and methods for voltage distribution via multiple epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises a wafer substrate of a connectivity type. A first epitaxial layer of a connectivity type is disposed upon a second epitaxial layer of an opposite connectivity ... 05/18/06 - 20060102957 - Ser immune cell structure A semiconductor chip is provided, which includes a memory device formed in a deep NWELL region. The memory device includes a memory cell. The memory cell includes a first storage node and a second storage node. The memory cell also includes a first resistor and a second resistor electrically connected ... 05/11/06 - 20060097325 - One-time programmable read only memory and operating method thereof A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode ... 05/04/06 - 20060091469 - Dual-gate structure and method of fabricating integrated circuits having dual-gate structures A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K ... 05/04/06 - 20060091468 - Top and sidewall bridged interconnect structure and method An interconnect structure and its method for fabrication each employ an interconnect formed over and adjacent an active region of a semiconductor substrate. A gate electrode is also formed over the active region. Spacer layers are formed adjoining the interconnect and the gate electrode. A spacer layer adjoining the interconnect ... 05/04/06 - 20060091467 - Resonant tunneling device using metal oxide semiconductor processing An embodiment of the present invention is a technique to fabricate a semiconductor device having low off state leakage current. A gate structure of a first device is formed on a substrate layer having a hardmask. A channel is formed underneath the gate structure having a width to support the ... 04/06/06 - 20060071281 - Integrated circuit and method for manufacturing A semiconductor structure, fluid ejection device, and methods for manufacturing the same are provided, such that a contact to a substrate is formed from a conductive layer. ... 03/02/06 - 20060043492 - Ruthenium gate for a lanthanide oxide dielectric layer A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic devices. The lanthanide oxide dielectric layer is formed by depositing lanthanum by atomic layer deposition onto a substrate ... 02/23/06 - 20060038236 - Semiconductor device A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a ... 02/23/06 - 20060038235 - Semiconductor device A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within ... 02/23/06 - 20060038234 - Memory cell structure An SRAM device includes an SRAM cell in a deep NWELL region in a substrate. PWELL regions in the SRAM cell occupy less than about 65% of the cell area of the SRAM cell. A ratio of a longer side of a cell area of the SRAM cell to a ... 02/16/06 - 20060033166 - Electronic devices having partially elevated source/drain structures and related methods Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second ... 02/16/06 - 20060033165 - Mosfet structure with multiple self-aligned silicide contacts A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface ... 02/09/06 - 20060027875 - Semiconductor device with gate space of positive slope and fabrication method thereof Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between ... 02/02/06 - 20060022276 - Methods of forming semiconductor devices including a resistor in a resistor region and devices so formed Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices ... 01/26/06 - 20060017111 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so that the gate electrode is buried therein, a contact hole formed in the interlayer insulating film so as to ... 01/12/06 - 20060006473 - Integrated circuit hierarchical design system, integrated circuit hierarchical design program and integrated circuit hierarchical design method An integrated circuit hierarchical design system for optimizing a circuit locating between flip-flops included in a lower layer through a higher layer among layers forming an integrated circuit, which shifts a layer section as a boundary between the higher layer and the lower layer that locates on the circuit to ... 01/05/06 - 20060001105 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that ... 01/05/06 - 20060001104 - Semiconductor device having sti with nitride liner A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of ... 01/05/06 - 20060001103 - Interconnect structure in integrated circuits A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths. ... 01/05/06 - 20060001102 - Drain-extended mos transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon ... 12/29/05 - 20050285204 - Semiconductor device including a multi-channel fin field effect transistor and method of fabricating the same In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active ... 12/29/05 - 20050285203 - Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side ... 12/29/05 - 20050285202 - Structure and method to improve sram stability without increasing cell area or off current An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress ... 12/22/05 - 20050280094 - Nrom flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on ... 12/15/05 - 20050275033 - Schottky barrier source/drain n-mosfet using ytterbium silicide A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium ... 12/01/05 - 20050263823 - Phase-change memory device having a barrier layer and manufacturing method A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a ... 11/03/05 - 20050242401 - Wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on ... 10/20/05 - 20050230760 - Methods for selective deposition to improve selectivity Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area ... 10/20/05 - 20050230759 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a semiconductor substrate containing Si as a main component, and an active element formed on the semiconductor substrate and including an insulating metal silicide thin film formed on the semiconductor substrate, dangling bonds of Si of the semiconductor substrate being terminated by the insulating metal silicide ... 10/20/05 - 20050230758 - Transistor well bias scheme A method of reducing the operating voltage level of a MOS transistor formed in a well, comprising drawing a current from the well and thereby forward biasing the well, while the well potential is allowed to vary according to inherent transistor characteristics. ... 10/13/05 - 20050224888 - Integrated circuit array Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which ... 10/13/05 - 20050224887 - Semiconductor device for power mos transistor module A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the ... 10/13/05 - 20050224886 - Semiconductor device having a laterally modulated gate workfunction and method of fabrication A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric ... 10/13/05 - 20050224885 - Multipurpose metal fill The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured ... 10/06/05 - 20050218458 - Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the ... 10/06/05 - 20050218457 - Mosfet for an open-drain circuit and semiconductor integrated circuit device employing it In a conventional N-channel MOSFET for an open-drain circuit, when a positive static electric charge is applied to its drain, there is no route by way of which to discharge the static electric charge, resulting in a rather low static withstand voltage. To overcome this, according to the invention, an ... 10/06/05 - 20050218456 - Electronic element including ferroelectric substance film and method of manufacturing the same A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property of the ferroelectric substance film formed through epitaxial growth with reference ... 10/06/05 - 20050218455 - Low noise and high performance lsi device, layout and manufacturing method In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be ... 09/29/05 - 20050212054 - Semiconductor device and method of manufacturing the same The semiconductor device includes a memory cell which has a SRAM structure including a pair of drive transistors where the gate electrode of one of the pair of drive transistors is connected to the drain of the other of the pair of drive transistors via a node interconnect on which ... 09/15/05 - 20050199962 - Semiconductor device and method for fabricating the same A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11b is formed ... 09/15/05 - 20050199961 - Semiconductor device One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx wherein each A is selected from the group of Ga, In, each B is selected from the group of Ge, Sn, Pb, each O is atomic oxygen, ... 09/15/05 - 20050199960 - Semiconductor device One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium. ... 09/15/05 - 20050199959 - Semiconductor device A semiconductor device can include a channel including a zinc-indium oxide film. ... 09/15/05 - 20050199958 - Method for selectively stressing mosfets to improve charge carrier mobility A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress ... 09/01/05 - 20050189595 - Semiconductor device comprising transistor pair isolated by trench isolation A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region ... 08/18/05 - 20050179091 - Semiconductor device and its manufacturing method A semiconductor device and a method of manufacturing the semiconductor device are disclosed. A semiconductor device of one of several disclosed embodiments comprises a semiconductor layer having a source region and a drain region, and a gate insulating film provided on the semiconductor layer between the source region and the ... 08/18/05 - 20050179090 - Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, an isolation film that is provided in one principal surface of the semiconductor substrate, wiring that is arranged on the isolation film, a diffusion layer that is formed inside the semiconductor substrate and located in the vicinity of the isolation film, and an ... 08/04/05 - 20050167755 - Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include ... 08/04/05 - 20050167754 - Semiconductor device and method of manufacturing the same A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to ... 07/28/05 - 20050161744 - Radiation hardened mos structure A radiation hardened MOS structure is integrated on a semiconductor substrate. The structure includes a MOS transistor realized in an active area surrounded by an isolation layer. The MOS transistor includes a channel region delimited by opposed source and drain regions of a first type of conductivity and a gate ... 07/14/05 - 20050151201 - Process for production of soi substrate and process for production of semiconductor device A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor ... 07/07/05 - 20050145949 - Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth ... 06/30/05 - 20050139927 - Field insulator fet device and fabrication method thereof A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial ... 06/16/05 - 20050127448 - Area efficient asymmetric cellular cmos array A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered. ... 06/09/05 - 20050121726 - Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45 a having a lightly doped source region 42a and a heavily doped source region 44a, ad rain region 45b having a lightly doped drain region 42b and a heavily doped drain region ... ### FreshPatents.com Support |