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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Field Effect Transistor In Integrated Circuit

Insulated Gate Field Effect Transistor In Integrated Circuit

Insulated Gate Field Effect Transistor In Integrated Circuit patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/17/14 - 20140103440 - I-shaped gate electrode for improved sub-threshold mosfet performance
Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is...

04/17/14 - 20140103441 - Semiconductor device and method of fabricating the same
A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench....

04/17/14 - 20140103442 - Semiconductor device, method of forming semiconductor device, and data processing system
A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the...

04/17/14 - 20140103443 - Semiconductor device having metal gate and manufacturing method thereof
A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer...

04/17/14 - 20140103444 - Semiconductor device with a dislocation structure and method of forming the same
A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on...

04/10/14 - 20140097496 - Guard rings on fin structures
A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of...

04/10/14 - 20140097497 - Spacer design to prevent trapped electrons
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could...

04/10/14 - 20140097498 - Open source power quad flat no-lead (pqfn) leadframe
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is...

04/10/14 - 20140097499 - Semiconductor structures
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch...

04/03/14 - 20140091394 - Multi-gate field effect transistor (fet) including isolated fin body
Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including...

04/03/14 - 20140091395 - Transistor
A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the...

04/03/14 - 20140091396 - Pass gate, semiconductor memory, and semiconductor device
According to one embodiment, a pass gate provided between a data holding unit of an SRAM cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second...

03/27/14 - 20140084374 - Cell design
One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate...

03/27/14 - 20140084375 - Semiconductor devices having back side bonding structures
Semiconductor devices are provided including an internal circuit on a front side of a substrate, the substrate defining a through-silicon via (TSV) structure extending vertically therein; a back side insulating layer on a back side of the substrate; and a back side bonding structure on the back side insulating layer....

03/27/14 - 20140084376 - Semiconductor device comprising a dummy well
Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At...

03/20/14 - 20140077304 - Airgap structure and method of manufacturing thereof
A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having...

03/20/14 - 20140077305 - Gate contact structure over active gate and method to fabricate same
Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed...

03/20/14 - 20140077306 - Semiconductor device layout reducing imbalance in characteristics of paired transistors
In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have...

03/20/14 - 20140077307 - Semiconductor device
A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the...

03/13/14 - 20140070320 - Integrated circuits with selective gate electrode recess
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of...

03/13/14 - 20140070321 - Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. One method includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region....

03/13/14 - 20140070322 - Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a...

03/13/14 - 20140070323 - Semiconductor arrangement with a load, a sense and a start-up transistor
A semiconductor arrangement includes a semiconductor body with a first active region, a second active region and an isolation region arranged between the first and the second active regions. At least one source region and at least one body region of a first transistor are integrated in the first active...

03/13/14 - 20140070324 - Semiconductor device with contact hole and manufacturing method thereof
A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each...

03/13/14 - 20140070325 - Semiconductor device and method for fabricating the same
A semiconductor device includes a first interface film on a first area of a substrate, the first interface film including a first growth interface film and a second growth interface film on a lower portion of the first growth interface film, a first dielectric film on the first interface film,...

03/13/14 - 20140070326 - Method for producing semiconductor device and semiconductor device
A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper...

03/06/14 - 20140061805 - Semiconductor device and method for manufacturing
A semiconductor device includes a gate structure penetrating an interlayer insulating layer formed on a semiconductor substrate, an epitaxial growth layer grown on the interlayer insulating layer, a first transistor including a first channel region in the semiconductor substrate formed by a bias applied to source/drain contacts penetrating the interlayer...

03/06/14 - 20140061806 - Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate including a cell region and a peripheral circuit region, buried gates formed in the substrate of the cell region, a bit line formed over the cell region between the buried gates and including a first barrier layer, and a gate formed over the peripheral...

03/06/14 - 20140061807 - Semiconductor structures and fabrication method
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, and forming a shallow trench isolation structure in the semiconductor substrate. The method also includes forming a plurality of parallel gate structures on the semiconductor substrate surrounded by the shallow trench isolation structure. Further,...

03/06/14 - 20140061808 - Pass gate and semiconductor storage device having the same
According to an embodiment, a semiconductor storage device includes an SRAM cell. The SRAM cell includes first and second transfer gates each comprising a pass gate. The pass gate includes first and second tunnel transistors. The first tunnel transistor includes a first conductivity type first diffusion region as a source...

03/06/14 - 20140061809 - Semiconductor device
There is provided a semiconductor device comprising, at least one SRAM cell, wherein the SRAM cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (Tinv) of a gate stack of the pass-gate transistor is different from Tinv of a gate stack of the...

03/06/14 - 20140061810 - Semiconductor device and manufacturing method thereof
Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer,...

02/27/14 - 20140054710 - Reduction of proximity effects in field-effect transistors with embedded silicon-germanium source and drain regions
An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each...

02/27/14 - 20140054711 - System and method for a vertical tunneling field-effect transistor cell
A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is...

02/27/14 - 20140054712 - Semiconductor device and fabrication method
A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact structure formed on a semiconductor substrate of a peripheral circuit area, and includes a first gate insulating layer to...

02/27/14 - 20140054713 - Semiconductor device and a method for fabricating the same
A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate...

02/27/14 - 20140054714 - Replacement gate fabrication methods
Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between...

02/20/14 - 20140048884 - Disposable carbon-based template layer for formation of borderless contact structures
After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer. A pattern including openings is formed within the photoresist...

02/20/14 - 20140048885 - Dual workfunction semiconductor devices and methods for forming thereof
Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein...

02/13/14 - 20140042545 - Mos transistors having reduced leakage well-substrate junctions
A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A...

02/13/14 - 20140042546 - Structure and method to form input/output devices
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on...

02/13/14 - 20140042547 - High density bulk fin capacitor
A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors....

02/13/14 - 20140042548 - Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer....

02/06/14 - 20140035045 - Method of manufacturing dummy gates of a different material as insulation between adjacent devices
Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial...

02/06/14 - 20140035046 - Semiconductor device and manufacturing method of semiconductor device
A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in...

02/06/14 - 20140035047 - Power device integration on a common substrate
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an...

02/06/14 - 20140035048 - Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop...

02/06/14 - 20140035049 - Semiconductor device and fabricating method thereof
A semiconductor device and a fabricating method thereof are provided. The semiconductor device is formed on a substrate and includes a first first-type metal-oxide-semiconductor field effect transistor (MOSFET) and a second first-type MOSFET. The first first-type MOSFET includes a first gate structure, a first source area and a first drain...

02/06/14 - 20140035050 - Semiconductor devices having a diffusion barrier layer and methods of manufacturing the same
Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in...

02/06/14 - 20140035051 - Semiconductor device and associated methods
A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate,...

02/06/14 - 20140035052 - Electronic device including a tapered trench and a conductive structure therein
An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of...

02/06/14 - 20140035053 - Finfet cell architecture with insulator structure
A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first...

02/06/14 - 20140035054 - Device and methods for small trench patterning
A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with...

02/06/14 - 20140035055 - Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET....