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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > With Plural, Separately Connected, Gate Electrodes In Same Device With Plural, Separately Connected, Gate Electrodes In Same DeviceWith Plural, Separately Connected, Gate Electrodes In Same Device patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/31/08 - 20080023770 - Stacked semiconductor devices and methods of manufacturing the same The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and ... 12/27/07 - 20070296041 - Semiconductor device and method of manufacturing the same A semiconductor device including a semiconductor substrate, a memory cell transistor formed in a memory cell region of the semiconductor substrate; a transistor formed in a peripheral circuit region of the semiconductor substrate and having an LDD (Lightly Doped Drain) structure; and the memory cell transistor has a same film ... 12/20/07 - 20070290268 - Method of fabricating semiconductor device In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including ... 12/20/07 - 20070290267 - Semiconductor device and method of manufacturing the same A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the ... 12/06/07 - 20070278582 - Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of ... 11/22/07 - 20070267702 - Dynamic threshold p-channel mosfet for ultra-low voltage ultra-low power applications A dynamic threshold voltage p-channel MOSFET (PMOS) for ultra-low power ultra-low voltage applications is disclosed. These applications are of low-to-moderate performance requirements; hence ultra-low voltage subthreshold operation, where the supply voltage is less than the transistors threshold voltage, is suitable. By tying the PMOS body to the output node of ... 11/15/07 - 20070262389 - Tri-gate transistors and methods to fabricate same Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor ... 10/25/07 - 20070246779 - Dual gate oxide structure in semiconductor device and method thereof In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of ... 09/13/07 - 20070210388 - Semiconductor device and manufacturing method thereof To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned ... 08/09/07 - 20070181949 - Transistor and novolatile memory device including the same A transistor includes a gate electrode on a substrate, source/drain regions in the substrate at both sides of the gate electrode, and a channel region defined between the source/drain regions, wherein the channel region includes a recessed region and at least one of the source/drain regions is spaced away from ... 07/12/07 - 20070158749 - Low resistance peripheral contacts while maintaining dram array integrity An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide ... 06/28/07 - 20070145486 - Semiconductor memory device and method of manufacturing the same A semiconductor memory device has a memory cell and a peripheral transistor formed on a substrate. The memory cell is provided with a select transistor formed on the substrate and a capacitor connected to the select transistor. A diffusion layer of the peripheral transistor is connected to an upper layer ... 05/17/07 - 20070108528 - Sram cell Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise ... 04/05/07 - 20070075374 - Semicondutor device and method for fabricating the same A semiconductor device includes: a first field-effect transistor including a first gate electrode; and a second field-effect transistor including a second gate electrode. The first and second gate electrodes are fully silicided with metal and have different gate lengths. A trench is formed in an upper portion of the first ... 03/22/07 - 20070063286 - Semiconductor device and method for manufacturing the same In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS ... 03/08/07 - 20070052034 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate ... 03/01/07 - 20070045747 - Reduction of short-circuiting between contacts at or near a tensile-compressive boundary Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at ... 02/15/07 - 20070034961 - Semiconductor device, display device, and electronic device It is an object of the invention to provide a semiconductor device having a level shifter, a differential amplifier circuit, and the like, where power consumption is reduced by reducing an unnecessary through current and distortion of an output waveform can be suppressed. A gate terminal of a first transistor ... 02/08/07 - 20070029616 - Semiconductor integrated circuit device and method of fabricating the same A semiconductor integrated circuit device and a method of fabricating the same are provided. An embodiment of the semiconductor integrated circuit device includes a substrate having a cell region and a peripheral circuit region. A recess channel transistor may be formed in the cell region and include a source/drain region, ... 12/28/06 - 20060289938 - Non-volatile memory devices and related methods A semiconductor device may include a semiconductor substrate having an active region on a surface thereof. First, second, and third gate lines may cross the active region of the semiconductor substrate, and the first, second, and third gate lines may be arranged in parallel across the active region, and the ... 12/21/06 - 20060284259 - Semiconductor device and method of manufacturing the same In a semiconductor device having asymmetric bit lines and a method of manufacturing the same, a plurality of active regions are electrically isolated from one another by an isolation layer. Each active region extends in a first direction and has a central portion between end portions. The device includes a ... 12/14/06 - 20060278931 - Electrostatic protection device for semiconductor circuit The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and ... 10/12/06 - 20060226490 - Interlayer dielectric under stress for an integrated circuit An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD ... 10/12/06 - 20060226489 - System and methods for retention-enhanced programmable shared gate logic circuit Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities ... 09/14/06 - 20060202275 - Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than ... 09/14/06 - 20060202274 - Semiconductor integrated circuit and nonvolatile memory element A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The ... 09/07/06 - 20060197160 - Nonvolatile semiconductor memory device A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in ... 08/03/06 - 20060170057 - Semiconductor device with omega gate and method for fabricating a semiconductor device A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending ... 08/03/06 - 20060170056 - Drain extended pmos transistor with increased breakdown voltage A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of ... 06/15/06 - 20060125017 - Stacked memory cell utilizing negative differential resistance devices A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more ... 06/08/06 - 20060118876 - Fin field effect transistor and method of manufacturing the same In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern ... 06/01/06 - 20060113601 - Dual-gate metal-oxide semiconductor device An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region ... 05/04/06 - 20060091466 - Nonvolatile semiconductor memory device A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in ... 04/27/06 - 20060086985 - Semiconductor device A semiconductor device includes first integrated circuit comprising first to third MOSFET having same channel type, and first to third MOSFETs including gate electrode and gate sidewall insulating film on sidewall of gate electrode, and distance between gate electrodes of first and second MOSFETs, and distance between gate electrodes of ... 04/20/06 - 20060081936 - Semiconductor device for low power operation A semiconductor device for low power operation includes a channel region having a channel length greater than a standard minimum channel length. The voltage supply of the device is less than the threshold voltage of the device. A gate terminal of the device may have a raised height relative to ... 04/06/06 - 20060071279 - Semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device A semiconductor device includes a semiconductor substrate that has an oxide film selectively formed on a part thereof; a semiconductor layer that is formed on the oxide film by epitaxial growth; a first gate electrode that is formed on the semiconductor layer; first source/drain layers that are formed on the ... 04/06/06 - 20060071278 - Semiconductor device and method for fabricating the same The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, ... 03/30/06 - 20060065934 - Semiconductor device and method for manufacturing the same A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface ... 02/23/06 - 20060038233 - Semiconductor device and method of manufacturing the same A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate ... 02/23/06 - 20060038232 - High-voltage transistor having shielding gate A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode ... 02/09/06 - 20060027874 - Novel isolated ldmos ic technology A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate ... 01/26/06 - 20060017110 - Semiconductor device with low resistance contacts An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to ... 12/29/05 - 20050285201 - Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of ... 12/08/05 - 20050269643 - Semiconductor element and method of manufacturing the same A field-effect transistor includes a substrate of a first conductivity type, and a channel diffusion region of a second conductivity type provided in the first conductivity type substrate. The transistor also includes a first conductivity type contact region provided in the second conductivity type channel diffusion region, and an electrode ... 10/13/05 - 20050224884 - Double-gate mos transistor, double-gate cmos transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined ... 09/15/05 - 20050199957 - Double gate field effect transistor with diamond film A double gate silicon over insulator transistor may be formed wherein the bottom gate electrode is formed of a doped diamond film. The doped diamond film may be formed in the process of semiconductor manufacture resulting in an embedded electrode. The diamond film may be advantageous as a heat spreader. ... 09/15/05 - 20050199956 - Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness ... ### FreshPatents.com Support |