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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Single Crystal Semiconductor Layer On Insulating Substrate (soi) > Insulated Electrode Device Is Combined With Diverse Type Device (e.g., Complementary Mosfets, Fet With Resistor, Etc.) > Complementary Field Effect Transistor Structures Only (i.e., Not Including Bipolar Transistors, Resistors, Or Other Components) Complementary Field Effect Transistor Structures Only (i.e., Not Including Bipolar Transistors, Resistors, Or Other Components)Complementary Field Effect Transistor Structures Only (i.e., Not Including Bipolar Transistors, Resistors, Or Other Components) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/03/08 - 20080001226 - Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically ... 12/20/07 - 20070290265 - Method of fabricating heterojunction photodiodes with cmos An epitaxial device module monolithically integrated with a CMOS structure in a bulk or thick-film SOI substrate, comprising an active area on which epitaxial layers are formed by selective or non-selective epitaxial growth and a separate active area in which the CMOS structure is formed. A hard mask for epitaxy ... 11/15/07 - 20070262385 - Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from ... 11/08/07 - 20070257317 - Method of forming a body-tie A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of ... 11/01/07 - 20070252211 - Semiconductor device and manufacturing method for semiconductor device A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, ... 10/18/07 - 20070241404 - Semiconductor device and manufacturing method thereof A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline semiconductor film. A semiconductor layer includes a region containing an impurity element ... 10/18/07 - 20070241403 - Integrated circuit with different channel materials for p and n channel transistors and method therefor A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type ... 10/11/07 - 20070235807 - Semiconductor device structure and method therefor Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially ... 10/04/07 - 20070228472 - Silicon device on si: c-oi and sgoi and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal ... 08/16/07 - 20070187761 - Semiconductor device and method of manufacturing the same The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare ... 08/09/07 - 20070181947 - Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a ... 07/12/07 - 20070158747 - Soi cmos circuits with substrate bias The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS ... 07/05/07 - 20070152273 - High performance circuit with metal and polygate electrodes A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That ... 06/21/07 - 20070138560 - Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an ... 06/21/07 - 20070138559 - Replacement gates to enhance transistor strain Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. ... 06/14/07 - 20070132028 - Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an ... 06/14/07 - 20070132027 - Transistor device containing carbon doped silicon in a recess next to mdd to create strain in channel A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral ... 05/17/07 - 20070108526 - Strained silicon cmos devices Improved ways of controlling the boundaries between the compressive and tensile portions of a dual-stress liner in a semiconductor device are described. The boundaries may be appropriately designed to be located by a predetermined distance as measured from a PFET feature, such as the channel or the active area boundary, ... 05/17/07 - 20070108525 - Structure and method to increase strain enhancement with spacerless fet and dual liner process A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be ... 04/12/07 - 20070080402 - Semiconductor device and method for manufacturing the same A semiconductor device includes a first insulator formed at a part under a semiconductor layer, a second insulator formed under the semiconductor layer in an arranged manner avoiding the first insulator and having a relative dielectric constant different from that of the first insulator, a backgate electrode formed under the ... 03/29/07 - 20070069296 - High-density high current device cell A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size ... 03/29/07 - 20070069295 - Process to integrate fabrication of bipolar devices into a cmos process flow A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the ... 03/29/07 - 20070069294 - Stress engineering using dual pad nitride with selective soi device architecture A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of ... 03/22/07 - 20070063284 - Semiconductor device and semiconductor integrated circuit using the same The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used ... 03/08/07 - 20070052028 - Semiconductor memory device including an soi substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain ... 03/08/07 - 20070052027 - Hybrid schottky source-drain cmos for high mobility and low barrier A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of ... 03/01/07 - 20070045742 - Fully-depleted (fd) (soi) mosfet access transistor and method of fabrication A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. ... 03/01/07 - 20070045741 - Dram tunneling access transistor In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into ... 01/25/07 - 20070018248 - Power gating schemes in soi circuits in hybrid soi-epitaxial cmos structures Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or ... 12/21/06 - 20060284255 - Complementary field-effect transistors having enhanced performance with a single capping layer Performance of a complementary metal-oxide-semiconductor (CMOS) device having n-channel MOS transistors and p-channel MOS transistors is enhanced by providing a single capping layer overlying the MOS transistors with the single capping layer inducing stress in the transistor channel regions to enhance carrier mobility. The n-channel transistor is preferably fabricated in ... 11/30/06 - 20060267100 - Semiconductor device including single crystal silicon layer and method of manufacturing semiconductor device A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected ... 11/02/06 - 20060244069 - Semiconductor device having a gate dielectric of different blocking characteristics By locally adapting the blocking capability of gate insulation layers for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a ... 11/02/06 - 20060244068 - Field effect transistor with mixed-crystal-orientation channel and source/drain regions Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for ... 10/05/06 - 20060220134 - Cmos sram cells employing multiple-gate transistors and methods fabricating the same Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor ... 09/28/06 - 20060214232 - Semiconductor-on-insulator (soi) strained active areas Differentially strained active regions for forming strained channel semiconductor devices and a method of forming the same, the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; forming a doped area ... 09/14/06 - 20060202271 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a first power supply interconnect formed of a first single-crystal semiconductor layer and coupled to a first potential, and a second power supply interconnect formed of a second single-crystal semiconductor layer and coupled to a second potential, the second single-crystal semiconductor layer being deposited over the ... 09/07/06 - 20060197158 - Advanced cmos using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of ... 09/07/06 - 20060197157 - Semiconductor device and method for manufacturing the same There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate ... 08/03/06 - 20060170052 - Semiconductor device, method of manufacture thereof and semiconductor integrated circuit An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth ... 07/20/06 - 20060157788 - Sram memories and microprocessors having logic portions implemented in high-performance silicon substrates and sram array portions having field effect transistors with linked bodies and methods for making same The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an ... 07/06/06 - 20060145259 - Fin field-effect transistor and method for fabricating the same A fin field-effect transistor and a method of fabricating the same provide a fin structure with rounded edges that may prevent a localized thinning of a gate insulating layer formed over the fin structure and to thereby prevent the occurrence of electrical shorts between the fin and a conductive layer ... 07/06/06 - 20060145258 - Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconductor substrate, and a gate electrode formed on the first gate ... 06/15/06 - 20060125013 - Double silicon-on-insulator (soi) metal oxide semiconductor field effect transistor (mosfet) structures A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated ... 06/15/06 - 20060125012 - Varactor A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of ... 06/08/06 - 20060118875 - Method of manufacturing semiconductor device A gate electrode in an NMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function smaller than that of intrinsic silicon. A gate electrode in a PMOS region is one of intrinsic silicon ... 03/30/06 - 20060065930 - Growing [110] silicon on [001]-oriented substrate with rare-earth oxide buffer film An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The ... 03/23/06 - 20060060923 - Semiconductor device The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b ... 02/23/06 - 20060038230 - Transistor and method of manufacturing the same A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second ... 02/23/06 - 20060038229 - Semiconductor device Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions, and a MIS transistor comprising a gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of contact layers formed on the semiconductor substrate sandwiching the gate electrode, the contact layers ... 02/09/06 - 20060027869 - Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions ... 02/09/06 - 20060027868 - High mobility cmos circuits Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to ... 02/02/06 - 20060022271 - Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples. ... 02/02/06 - 20060022270 - Ultra-thin body super-steep retrograde well (ssrw) fet devices A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ... 01/26/06 - 20060017107 - Metal gate engineering for surface p-channel devices A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in ... 01/12/06 - 20060006470 - Mos field-effect transistor A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bidirectional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings. ... 01/12/06 - 20060006469 - Method of fabricating cmos thin film transistor (tft) and cmos tft fabricated using the same A method of fabricating a CMOS thin film transistor (TFT) and a CMOS TFT fabricated using the method involve provision of a substrate having a first region and a second region. A first semiconductor layer and a second semiconductor layer are formed on the first and second regions, respectively. A ... 12/08/05 - 20050269640 - Semiconductor device and manufacturing method thereof A technique for forming a plurality of MISFETs having desired threshold voltages on a SOI substrate is provided. Each gate electrodes of pMIS and nMIS is made of a metal film having a work function approximate to that of a channel region of the pMIS, such as a molybdenum or ... 10/20/05 - 20050230756 - Cmos device and method of manufacture A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the ... 08/25/05 - 20050184343 - Mesfets integrated with mosfets on common substrate and methods of forming the same An integrated circuit has first and second complementary MOSFETs and first and second complementary MESFETs fabricated on a common substrate. An insulating layer is disposed on the common substrate. The active region uses salicide block oxide layers to align the drain and source regions to the gate. Alternatively, the active ... 07/07/05 - 20050145944 - Transistor gate electrode having conductor material layer Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between ... 06/30/05 - 20050139926 - Semiconductor device and method for manufacturing same The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can ... 06/30/05 - 20050139925 - Laser mask and crystallization method using the same A crystallization method includes providing a substrate having a silicon thin film; positioning a laser mask having first to fourth blocks on the substrate, each block having a periodic pattern including a plurality of transmitting regions and a blocking region; and crystallizing the silicon thin film by irradiating a laser ... 06/23/05 - 20050133867 - Semiconductor device and method of fabricating the same There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects. ... 06/02/05 - 20050116294 - Semiconductor device and method for manufacturing the same An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride ... ### FreshPatents.com Support |